1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2088A family SoC.
5 * Copyright 2016 Freescale Semiconductor, Inc.
8 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include "fsl-ls208xa.dtsi"
18 compatible = "arm,cortex-a72";
20 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
21 cpu-idle-states = <&CPU_PW20>;
22 next-level-cache = <&cluster0_l2>;
28 compatible = "arm,cortex-a72";
30 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
31 cpu-idle-states = <&CPU_PW20>;
32 next-level-cache = <&cluster0_l2>;
38 compatible = "arm,cortex-a72";
40 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
41 cpu-idle-states = <&CPU_PW20>;
42 next-level-cache = <&cluster1_l2>;
48 compatible = "arm,cortex-a72";
50 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
51 cpu-idle-states = <&CPU_PW20>;
52 next-level-cache = <&cluster1_l2>;
58 compatible = "arm,cortex-a72";
60 clocks = <&clockgen QORIQ_CLK_CMUX 2>;
61 next-level-cache = <&cluster2_l2>;
62 cpu-idle-states = <&CPU_PW20>;
68 compatible = "arm,cortex-a72";
70 clocks = <&clockgen QORIQ_CLK_CMUX 2>;
71 cpu-idle-states = <&CPU_PW20>;
72 next-level-cache = <&cluster2_l2>;
78 compatible = "arm,cortex-a72";
80 clocks = <&clockgen QORIQ_CLK_CMUX 3>;
81 cpu-idle-states = <&CPU_PW20>;
82 next-level-cache = <&cluster3_l2>;
88 compatible = "arm,cortex-a72";
90 clocks = <&clockgen QORIQ_CLK_CMUX 3>;
91 cpu-idle-states = <&CPU_PW20>;
92 next-level-cache = <&cluster3_l2>;
96 cluster0_l2: l2-cache0 {
100 cluster1_l2: l2-cache1 {
101 compatible = "cache";
104 cluster2_l2: l2-cache2 {
105 compatible = "cache";
108 cluster3_l2: l2-cache3 {
109 compatible = "cache";
113 compatible = "arm,idle-state";
114 idle-state-name = "PW20";
115 arm,psci-suspend-param = <0x0>;
116 entry-latency-us = <2000>;
117 exit-latency-us = <2000>;
118 min-residency-us = <6000>;
123 compatible = "fsl,ls2088a-pcie";
124 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
125 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
127 ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000
128 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>;
132 compatible = "fsl,ls2088a-pcie";
133 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
134 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
136 ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000
137 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>;
141 compatible = "fsl,ls2088a-pcie";
142 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
143 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
145 ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000
146 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>;
150 compatible = "fsl,ls2088a-pcie";
151 reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
152 0x38 0x00000000 0x0 0x00002000>; /* configuration space */
154 ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000
155 0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>;