1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for Travese Ten64 (LS1088) board
4 * Based on fsl-ls1088a-rdb.dts
5 * Copyright 2017-2020 NXP
6 * Copyright 2019-2021 Traverse Technologies
8 * Author: Mathew McBride <matt@traverse.com.au>
13 #include "fsl-ls1088a.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
19 model = "Traverse Ten64";
20 compatible = "traverse,ten64", "fsl,ls1088a";
28 stdout-path = "serial0:115200n8";
32 compatible = "gpio-keys";
34 /* Fired by system controller when
35 * external power off (e.g ATX Power Button)
39 label = "External Power Down";
40 gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
41 interrupts = <&gpio1 17 IRQ_TYPE_EDGE_FALLING>;
42 linux,code = <KEY_POWER>;
45 /* Rear Panel 'ADMIN' button (GPIO_H) */
47 label = "ADMIN button";
48 gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
49 interrupts = <&gpio3 8 IRQ_TYPE_EDGE_RISING>;
50 linux,code = <KEY_WPS_BUTTON>;
55 compatible = "gpio-leds";
58 label = "ten64:green:sfp1:down";
59 gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
63 label = "ten64:green:sfp2:up";
64 gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
68 label = "ten64:admin";
69 gpios = <&sfpgpio 12 GPIO_ACTIVE_HIGH>;
74 compatible = "sff,sfp";
75 i2c-bus = <&sfplower_i2c>;
76 tx-fault-gpios = <&sfpgpio 0 GPIO_ACTIVE_HIGH>;
77 tx-disable-gpios = <&sfpgpio 1 GPIO_ACTIVE_HIGH>;
78 mod-def0-gpios = <&sfpgpio 2 GPIO_ACTIVE_LOW>;
79 los-gpios = <&sfpgpio 3 GPIO_ACTIVE_HIGH>;
80 maximum-power-milliwatt = <2000>;
84 compatible = "sff,sfp";
85 i2c-bus = <&sfpupper_i2c>;
86 tx-fault-gpios = <&sfpgpio 4 GPIO_ACTIVE_HIGH>;
87 tx-disable-gpios = <&sfpgpio 5 GPIO_ACTIVE_HIGH>;
88 mod-def0-gpios = <&sfpgpio 6 GPIO_ACTIVE_LOW>;
89 los-gpios = <&sfpgpio 7 GPIO_ACTIVE_HIGH>;
90 maximum-power-milliwatt = <2000>;
98 phy-connection-type = "10gbase-r";
99 managed = "in-band-status";
102 /* XG0 - Lower SFP */
105 pcs-handle = <&pcs2>;
106 phy-connection-type = "10gbase-r";
107 managed = "in-band-status";
110 /* DPMAC3..6 is GE4 to GE8 */
112 phy-handle = <&mdio1_phy5>;
113 phy-connection-type = "qsgmii";
114 managed = "in-band-status";
115 pcs-handle = <&pcs3_0>;
119 phy-handle = <&mdio1_phy6>;
120 phy-connection-type = "qsgmii";
121 managed = "in-band-status";
122 pcs-handle = <&pcs3_1>;
126 phy-handle = <&mdio1_phy7>;
127 phy-connection-type = "qsgmii";
128 managed = "in-band-status";
129 pcs-handle = <&pcs3_2>;
133 phy-handle = <&mdio1_phy8>;
134 phy-connection-type = "qsgmii";
135 managed = "in-band-status";
136 pcs-handle = <&pcs3_3>;
139 /* DPMAC7..10 is GE0 to GE3 */
141 phy-handle = <&mdio1_phy1>;
142 phy-connection-type = "qsgmii";
143 managed = "in-band-status";
144 pcs-handle = <&pcs7_0>;
148 phy-handle = <&mdio1_phy2>;
149 phy-connection-type = "qsgmii";
150 managed = "in-band-status";
151 pcs-handle = <&pcs7_1>;
155 phy-handle = <&mdio1_phy3>;
156 phy-connection-type = "qsgmii";
157 managed = "in-band-status";
158 pcs-handle = <&pcs7_2>;
162 phy-handle = <&mdio1_phy4>;
163 phy-connection-type = "qsgmii";
164 managed = "in-band-status";
165 pcs-handle = <&pcs7_3>;
179 mdio1_phy5: ethernet-phy@c {
183 mdio1_phy6: ethernet-phy@d {
187 mdio1_phy7: ethernet-phy@e {
191 mdio1_phy8: ethernet-phy@f {
195 mdio1_phy1: ethernet-phy@1c {
199 mdio1_phy2: ethernet-phy@1d {
203 mdio1_phy3: ethernet-phy@1e {
207 mdio1_phy4: ethernet-phy@1f {
220 compatible = "ti,tca9539";
227 gpios = <13 GPIO_ACTIVE_HIGH>;
233 compatible = "atmel,at97sc3204t";
242 compatible = "epson,rx8035";
251 compatible = "nxp,pca9540";
252 #address-cells = <1>;
256 sfpupper_i2c: i2c@0 {
257 #address-cells = <1>;
262 sfplower_i2c: i2c@1 {
263 #address-cells = <1>;
290 compatible = "jedec,spi-nor";
291 #address-cells = <1>;
294 spi-max-frequency = <20000000>;
295 spi-rx-bus-width = <4>;
296 spi-tx-bus-width = <4>;
299 compatible = "fixed-partitions";
300 #address-cells = <1>;
310 reg = <0x100000 0x200000>;
314 label = "mcfirmware";
315 reg = <0x300000 0x200000>;
320 reg = <0x500000 0x80000>;
325 reg = <0x580000 0x40000>;
330 reg = <0x5C0000 0x40000>;
334 label = "devicetree";
335 reg = <0x600000 0x40000>;
341 compatible = "spi-nand";
342 #address-cells = <1>;
345 spi-max-frequency = <20000000>;
346 spi-rx-bus-width = <4>;
347 spi-tx-bus-width = <4>;
350 compatible = "fixed-partitions";
351 #address-cells = <1>;
354 /* reserved for future boot direct from NAND flash
355 * (this would use the same layout as the 8MiB NOR flash)
358 label = "nand-boot-reserved";
362 /* recovery / install environment */
365 reg = <0x800000 0x2000000>;
368 /* ubia (first OpenWrt) - a/b names to prevent confusion with ubi0/1/etc. */
371 reg = <0x2800000 0x6C00000>;
374 /* ubib (second OpenWrt) */
377 reg = <0x9400000 0x6C00000>;