1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
5 * Copyright 2016 Freescale Semiconductor, Inc.
6 * Copyright 2018, 2020 NXP
8 * Mingkai Hu <mingkai.hu@nxp.com>
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
16 compatible = "fsl,ls1046a";
17 interrupt-parent = <&gic>;
41 compatible = "arm,cortex-a72";
43 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
44 next-level-cache = <&l2>;
45 cpu-idle-states = <&CPU_PH20>;
51 compatible = "arm,cortex-a72";
53 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
54 next-level-cache = <&l2>;
55 cpu-idle-states = <&CPU_PH20>;
61 compatible = "arm,cortex-a72";
63 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
64 next-level-cache = <&l2>;
65 cpu-idle-states = <&CPU_PH20>;
71 compatible = "arm,cortex-a72";
73 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
74 next-level-cache = <&l2>;
75 cpu-idle-states = <&CPU_PH20>;
86 * PSCI node is not added default, U-boot will add missing
87 * parts if it determines to use PSCI.
89 entry-method = "psci";
92 compatible = "arm,idle-state";
93 idle-state-name = "PH20";
94 arm,psci-suspend-param = <0x0>;
95 entry-latency-us = <1000>;
96 exit-latency-us = <1000>;
97 min-residency-us = <3000>;
102 device_type = "memory";
103 /* Real size will be filled by bootloader */
104 reg = <0x0 0x80000000 0x0 0x0>;
108 compatible = "fixed-clock";
110 clock-frequency = <100000000>;
111 clock-output-names = "sysclk";
115 compatible ="syscon-reboot";
123 polling-delay-passive = <1000>;
124 polling-delay = <5000>;
125 thermal-sensors = <&tmu 0>;
129 temperature = <85000>;
135 temperature = <95000>;
143 polling-delay-passive = <1000>;
144 polling-delay = <5000>;
145 thermal-sensors = <&tmu 1>;
149 temperature = <85000>;
155 temperature = <95000>;
163 polling-delay-passive = <1000>;
164 polling-delay = <5000>;
165 thermal-sensors = <&tmu 2>;
169 temperature = <85000>;
175 temperature = <95000>;
183 polling-delay-passive = <1000>;
184 polling-delay = <5000>;
185 thermal-sensors = <&tmu 3>;
188 core_cluster_alert: core-cluster-alert {
189 temperature = <85000>;
194 core_cluster_crit: core-cluster-crit {
195 temperature = <95000>;
203 trip = <&core_cluster_alert>;
205 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
206 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
207 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
208 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
214 polling-delay-passive = <1000>;
215 polling-delay = <5000>;
216 thermal-sensors = <&tmu 4>;
220 temperature = <85000>;
226 temperature = <95000>;
235 compatible = "arm,armv8-timer";
236 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
237 IRQ_TYPE_LEVEL_LOW)>,
238 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
239 IRQ_TYPE_LEVEL_LOW)>,
240 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
241 IRQ_TYPE_LEVEL_LOW)>,
242 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
243 IRQ_TYPE_LEVEL_LOW)>;
247 compatible = "arm,cortex-a72-pmu";
248 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
252 interrupt-affinity = <&cpu0>,
258 gic: interrupt-controller@1400000 {
259 compatible = "arm,gic-400";
260 #interrupt-cells = <3>;
261 interrupt-controller;
262 reg = <0x0 0x1410000 0 0x10000>, /* GICD */
263 <0x0 0x1420000 0 0x20000>, /* GICC */
264 <0x0 0x1440000 0 0x20000>, /* GICH */
265 <0x0 0x1460000 0 0x20000>; /* GICV */
266 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
267 IRQ_TYPE_LEVEL_LOW)>;
271 compatible = "simple-bus";
272 #address-cells = <2>;
276 ddr: memory-controller@1080000 {
277 compatible = "fsl,qoriq-memory-controller";
278 reg = <0x0 0x1080000 0x0 0x1000>;
279 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
284 compatible = "fsl,ifc", "simple-bus";
285 reg = <0x0 0x1530000 0x0 0x10000>;
286 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
291 compatible = "fsl,ls1021a-qspi";
292 #address-cells = <1>;
294 reg = <0x0 0x1550000 0x0 0x10000>,
295 <0x0 0x40000000 0x0 0x10000000>;
296 reg-names = "QuadSPI", "QuadSPI-memory";
297 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
298 clock-names = "qspi_en", "qspi";
299 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
300 QORIQ_CLK_PLL_DIV(2)>,
301 <&clockgen QORIQ_CLK_PLATFORM_PLL
302 QORIQ_CLK_PLL_DIV(2)>;
306 esdhc: esdhc@1560000 {
307 compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
308 reg = <0x0 0x1560000 0x0 0x10000>;
309 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
311 voltage-ranges = <1800 1800 3300 3300>;
318 compatible = "fsl,ls1046a-scfg", "syscon";
319 reg = <0x0 0x1570000 0x0 0x10000>;
321 #address-cells = <1>;
323 ranges = <0x0 0x0 0x1570000 0x10000>;
325 extirq: interrupt-controller@1ac {
326 compatible = "fsl,ls1046a-extirq", "fsl,ls1043a-extirq";
327 #interrupt-cells = <2>;
328 #address-cells = <0>;
329 interrupt-controller;
332 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
333 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
334 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
335 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
336 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
337 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
338 <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
339 <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
340 <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
341 <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
342 <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
343 <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
344 interrupt-map-mask = <0xffffffff 0x0>;
348 crypto: crypto@1700000 {
349 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
352 #address-cells = <1>;
354 ranges = <0x0 0x00 0x1700000 0x100000>;
355 reg = <0x00 0x1700000 0x0 0x100000>;
356 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
360 compatible = "fsl,sec-v5.4-job-ring",
361 "fsl,sec-v5.0-job-ring",
362 "fsl,sec-v4.0-job-ring";
363 reg = <0x10000 0x10000>;
364 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
368 compatible = "fsl,sec-v5.4-job-ring",
369 "fsl,sec-v5.0-job-ring",
370 "fsl,sec-v4.0-job-ring";
371 reg = <0x20000 0x10000>;
372 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
376 compatible = "fsl,sec-v5.4-job-ring",
377 "fsl,sec-v5.0-job-ring",
378 "fsl,sec-v4.0-job-ring";
379 reg = <0x30000 0x10000>;
380 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
384 compatible = "fsl,sec-v5.4-job-ring",
385 "fsl,sec-v5.0-job-ring",
386 "fsl,sec-v4.0-job-ring";
387 reg = <0x40000 0x10000>;
388 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
393 compatible = "fsl,qman";
394 reg = <0x0 0x1880000 0x0 0x10000>;
395 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
396 memory-region = <&qman_fqd &qman_pfdr>;
401 compatible = "fsl,bman";
402 reg = <0x0 0x1890000 0x0 0x10000>;
403 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
404 memory-region = <&bman_fbpr>;
408 qportals: qman-portals@500000000 {
409 ranges = <0x0 0x5 0x00000000 0x8000000>;
412 bportals: bman-portals@508000000 {
413 ranges = <0x0 0x5 0x08000000 0x8000000>;
417 compatible = "fsl,ls1046a-dcfg", "syscon";
418 reg = <0x0 0x1ee0000 0x0 0x1000>;
422 clockgen: clocking@1ee1000 {
423 compatible = "fsl,ls1046a-clockgen";
424 reg = <0x0 0x1ee1000 0x0 0x1000>;
430 compatible = "fsl,qoriq-tmu";
431 reg = <0x0 0x1f00000 0x0 0x10000>;
432 interrupts = <0 33 0x4>;
433 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
434 fsl,tmu-calibration =
435 /* Calibration data group 1 */
436 <0x00000000 0x00000023
437 0x00000001 0x00000029
438 0x00000002 0x0000002f
439 0x00000003 0x00000036
440 0x00000004 0x0000003c
441 0x00000005 0x00000042
442 0x00000006 0x00000049
443 0x00000007 0x0000004f
444 0x00000008 0x00000055
445 0x00000009 0x0000005c
446 0x0000000a 0x00000062
447 0x0000000b 0x00000068
448 /* Calibration data group 2 */
449 0x00010000 0x00000022
450 0x00010001 0x0000002a
451 0x00010002 0x00000032
452 0x00010003 0x0000003a
453 0x00010004 0x00000042
454 0x00010005 0x0000004a
455 0x00010006 0x00000052
456 0x00010007 0x0000005a
457 0x00010008 0x00000062
458 0x00010009 0x0000006a
459 /* Calibration data group 3 */
460 0x00020000 0x00000021
461 0x00020001 0x0000002b
462 0x00020002 0x00000035
463 0x00020003 0x0000003e
464 0x00020004 0x00000048
465 0x00020005 0x00000052
466 0x00020006 0x0000005c
467 /* Calibration data group 4 */
468 0x00030000 0x00000011
469 0x00030001 0x0000001a
470 0x00030002 0x00000024
471 0x00030003 0x0000002e
472 0x00030004 0x00000038
473 0x00030005 0x00000042
474 0x00030006 0x0000004c
475 0x00030007 0x00000056>;
477 #thermal-sensor-cells = <1>;
481 compatible = "fsl,ls1021a-v1.0-dspi";
482 #address-cells = <1>;
484 reg = <0x0 0x2100000 0x0 0x10000>;
485 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
486 clock-names = "dspi";
487 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
488 QORIQ_CLK_PLL_DIV(2)>;
489 spi-num-chipselects = <5>;
495 compatible = "fsl,vf610-i2c";
496 #address-cells = <1>;
498 reg = <0x0 0x2180000 0x0 0x10000>;
499 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
500 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
501 QORIQ_CLK_PLL_DIV(2)>;
502 dmas = <&edma0 1 39>,
504 dma-names = "tx", "rx";
509 compatible = "fsl,vf610-i2c";
510 #address-cells = <1>;
512 reg = <0x0 0x2190000 0x0 0x10000>;
513 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
515 QORIQ_CLK_PLL_DIV(2)>;
520 compatible = "fsl,vf610-i2c";
521 #address-cells = <1>;
523 reg = <0x0 0x21a0000 0x0 0x10000>;
524 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
526 QORIQ_CLK_PLL_DIV(2)>;
531 compatible = "fsl,vf610-i2c";
532 #address-cells = <1>;
534 reg = <0x0 0x21b0000 0x0 0x10000>;
535 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
537 QORIQ_CLK_PLL_DIV(2)>;
541 duart0: serial@21c0500 {
542 compatible = "fsl,ns16550", "ns16550a";
543 reg = <0x00 0x21c0500 0x0 0x100>;
544 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
546 QORIQ_CLK_PLL_DIV(2)>;
550 duart1: serial@21c0600 {
551 compatible = "fsl,ns16550", "ns16550a";
552 reg = <0x00 0x21c0600 0x0 0x100>;
553 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
555 QORIQ_CLK_PLL_DIV(2)>;
559 duart2: serial@21d0500 {
560 compatible = "fsl,ns16550", "ns16550a";
561 reg = <0x0 0x21d0500 0x0 0x100>;
562 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
563 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
564 QORIQ_CLK_PLL_DIV(2)>;
568 duart3: serial@21d0600 {
569 compatible = "fsl,ns16550", "ns16550a";
570 reg = <0x0 0x21d0600 0x0 0x100>;
571 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
573 QORIQ_CLK_PLL_DIV(2)>;
577 gpio0: gpio@2300000 {
578 compatible = "fsl,qoriq-gpio";
579 reg = <0x0 0x2300000 0x0 0x10000>;
580 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
583 interrupt-controller;
584 #interrupt-cells = <2>;
587 gpio1: gpio@2310000 {
588 compatible = "fsl,qoriq-gpio";
589 reg = <0x0 0x2310000 0x0 0x10000>;
590 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
593 interrupt-controller;
594 #interrupt-cells = <2>;
597 gpio2: gpio@2320000 {
598 compatible = "fsl,qoriq-gpio";
599 reg = <0x0 0x2320000 0x0 0x10000>;
600 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
603 interrupt-controller;
604 #interrupt-cells = <2>;
607 gpio3: gpio@2330000 {
608 compatible = "fsl,qoriq-gpio";
609 reg = <0x0 0x2330000 0x0 0x10000>;
610 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
613 interrupt-controller;
614 #interrupt-cells = <2>;
617 lpuart0: serial@2950000 {
618 compatible = "fsl,ls1021a-lpuart";
619 reg = <0x0 0x2950000 0x0 0x1000>;
620 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
622 QORIQ_CLK_PLL_DIV(1)>;
627 lpuart1: serial@2960000 {
628 compatible = "fsl,ls1021a-lpuart";
629 reg = <0x0 0x2960000 0x0 0x1000>;
630 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
632 QORIQ_CLK_PLL_DIV(2)>;
637 lpuart2: serial@2970000 {
638 compatible = "fsl,ls1021a-lpuart";
639 reg = <0x0 0x2970000 0x0 0x1000>;
640 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
641 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
642 QORIQ_CLK_PLL_DIV(2)>;
647 lpuart3: serial@2980000 {
648 compatible = "fsl,ls1021a-lpuart";
649 reg = <0x0 0x2980000 0x0 0x1000>;
650 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
652 QORIQ_CLK_PLL_DIV(2)>;
657 lpuart4: serial@2990000 {
658 compatible = "fsl,ls1021a-lpuart";
659 reg = <0x0 0x2990000 0x0 0x1000>;
660 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
661 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
662 QORIQ_CLK_PLL_DIV(2)>;
667 lpuart5: serial@29a0000 {
668 compatible = "fsl,ls1021a-lpuart";
669 reg = <0x0 0x29a0000 0x0 0x1000>;
670 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
672 QORIQ_CLK_PLL_DIV(2)>;
677 wdog0: watchdog@2ad0000 {
678 compatible = "fsl,imx21-wdt";
679 reg = <0x0 0x2ad0000 0x0 0x10000>;
680 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
682 QORIQ_CLK_PLL_DIV(2)>;
686 edma0: edma@2c00000 {
688 compatible = "fsl,vf610-edma";
689 reg = <0x0 0x2c00000 0x0 0x10000>,
690 <0x0 0x2c10000 0x0 0x10000>,
691 <0x0 0x2c20000 0x0 0x10000>;
692 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
693 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
694 interrupt-names = "edma-tx", "edma-err";
697 clock-names = "dmamux0", "dmamux1";
698 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
699 QORIQ_CLK_PLL_DIV(2)>,
700 <&clockgen QORIQ_CLK_PLATFORM_PLL
701 QORIQ_CLK_PLL_DIV(2)>;
705 compatible = "snps,dwc3";
706 reg = <0x0 0x2f00000 0x0 0x10000>;
707 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
709 snps,quirk-frame-length-adjustment = <0x20>;
710 snps,dis_rxdet_inp3_quirk;
711 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
715 compatible = "snps,dwc3";
716 reg = <0x0 0x3000000 0x0 0x10000>;
717 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
719 snps,quirk-frame-length-adjustment = <0x20>;
720 snps,dis_rxdet_inp3_quirk;
721 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
725 compatible = "snps,dwc3";
726 reg = <0x0 0x3100000 0x0 0x10000>;
727 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
729 snps,quirk-frame-length-adjustment = <0x20>;
730 snps,dis_rxdet_inp3_quirk;
731 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
735 compatible = "fsl,ls1046a-ahci";
736 reg = <0x0 0x3200000 0x0 0x10000>,
737 <0x0 0x20140520 0x0 0x4>;
738 reg-names = "ahci", "sata-ecc";
739 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
740 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
741 QORIQ_CLK_PLL_DIV(2)>;
744 msi1: msi-controller@1580000 {
745 compatible = "fsl,ls1046a-msi";
747 reg = <0x0 0x1580000 0x0 0x10000>;
748 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
754 msi2: msi-controller@1590000 {
755 compatible = "fsl,ls1046a-msi";
757 reg = <0x0 0x1590000 0x0 0x10000>;
758 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
759 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
760 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
761 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
764 msi3: msi-controller@15a0000 {
765 compatible = "fsl,ls1046a-msi";
767 reg = <0x0 0x15a0000 0x0 0x10000>;
768 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
769 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
770 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
771 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
774 pcie1: pcie@3400000 {
775 compatible = "fsl,ls1046a-pcie";
776 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
777 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
778 reg-names = "regs", "config";
779 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
780 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
781 interrupt-names = "aer", "pme";
782 #address-cells = <3>;
787 bus-range = <0x0 0xff>;
788 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
789 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
790 msi-parent = <&msi1>, <&msi2>, <&msi3>;
791 #interrupt-cells = <1>;
792 interrupt-map-mask = <0 0 0 7>;
793 interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
794 <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
795 <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
796 <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
800 pcie_ep1: pcie_ep@3400000 {
801 compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
802 reg = <0x00 0x03400000 0x0 0x00100000
803 0x40 0x00000000 0x8 0x00000000>;
804 reg-names = "regs", "addr_space";
805 num-ib-windows = <6>;
806 num-ob-windows = <8>;
810 pcie2: pcie@3500000 {
811 compatible = "fsl,ls1046a-pcie";
812 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
813 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
814 reg-names = "regs", "config";
815 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
816 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
817 interrupt-names = "aer", "pme";
818 #address-cells = <3>;
823 bus-range = <0x0 0xff>;
824 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
825 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
826 msi-parent = <&msi2>, <&msi3>, <&msi1>;
827 #interrupt-cells = <1>;
828 interrupt-map-mask = <0 0 0 7>;
829 interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
830 <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
831 <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
832 <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
836 pcie_ep2: pcie_ep@3500000 {
837 compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
838 reg = <0x00 0x03500000 0x0 0x00100000
839 0x48 0x00000000 0x8 0x00000000>;
840 reg-names = "regs", "addr_space";
841 num-ib-windows = <6>;
842 num-ob-windows = <8>;
846 pcie3: pcie@3600000 {
847 compatible = "fsl,ls1046a-pcie";
848 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
849 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
850 reg-names = "regs", "config";
851 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
852 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
853 interrupt-names = "aer", "pme";
854 #address-cells = <3>;
859 bus-range = <0x0 0xff>;
860 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
861 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
862 msi-parent = <&msi3>, <&msi1>, <&msi2>;
863 #interrupt-cells = <1>;
864 interrupt-map-mask = <0 0 0 7>;
865 interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
866 <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
867 <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
868 <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
872 pcie_ep3: pcie_ep@3600000 {
873 compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep";
874 reg = <0x00 0x03600000 0x0 0x00100000
875 0x50 0x00000000 0x8 0x00000000>;
876 reg-names = "regs", "addr_space";
877 num-ib-windows = <6>;
878 num-ob-windows = <8>;
882 qdma: dma-controller@8380000 {
883 compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
884 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
885 <0x0 0x8390000 0x0 0x10000>, /* Status regs */
886 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
887 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
888 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
889 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
890 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
891 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
892 interrupt-names = "qdma-error", "qdma-queue0",
893 "qdma-queue1", "qdma-queue2", "qdma-queue3";
896 block-offset = <0x10000>;
897 fsl,dma-queues = <2>;
899 queue-sizes = <64 64>;
903 rcpm: power-controller@1ee2140 {
904 compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1+";
905 reg = <0x0 0x1ee2140 0x0 0x4>;
906 #fsl,rcpm-wakeup-cells = <1>;
909 ftm_alarm0: timer@29d0000 {
910 compatible = "fsl,ls1046a-ftm-alarm";
911 reg = <0x0 0x29d0000 0x0 0x10000>;
912 fsl,rcpm-wakeup = <&rcpm 0x20000>;
913 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
919 #address-cells = <2>;
923 bman_fbpr: bman-fbpr {
924 compatible = "shared-dma-pool";
925 size = <0 0x1000000>;
926 alignment = <0 0x1000000>;
931 compatible = "shared-dma-pool";
933 alignment = <0 0x800000>;
937 qman_pfdr: qman-pfdr {
938 compatible = "shared-dma-pool";
939 size = <0 0x2000000>;
940 alignment = <0 0x2000000>;
947 compatible = "linaro,optee-tz";
953 #include "qoriq-qman-portals.dtsi"
954 #include "qoriq-bman-portals.dtsi"