1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
11 #include "fsl-ls1046a.dtsi"
14 model = "LS1046A FRWY Board";
15 compatible = "fsl,ls1046a-frwy", "fsl,ls1046a";
25 stdout-path = "serial0:115200n8";
28 sb_3v3: regulator-sb3v3 {
29 compatible = "regulator-fixed";
30 regulator-name = "LT8642SEV-3.3V";
31 regulator-min-microvolt = <3300000>;
32 regulator-max-microvolt = <3300000>;
58 compatible = "nxp,pca9546";
69 compatible = "ti,ina220";
71 shunt-resistor = <1000>;
74 temperature-sensor@4c {
75 compatible = "nxp,sa56004";
77 vcc-supply = <&sb_3v3>;
81 compatible = "nxp,pcf2129";
86 compatible = "onnn,cat24c04", "atmel,24c04";
97 ranges = <0x0 0x0 0x0 0x7e800000 0x00010000>;
101 compatible = "fsl,ifc-nand";
102 #address-cells = <1>;
104 reg = <0x0 0x0 0x10000>;
112 mt25qu512a0: flash@0 {
113 compatible = "jedec,spi-nor";
114 #address-cells = <1>;
116 spi-max-frequency = <50000000>;
117 spi-rx-bus-width = <4>;
118 spi-tx-bus-width = <1>;
123 #include "fsl-ls1046-post.dtsi"
127 phy-handle = <&qsgmii_phy4>;
128 phy-connection-type = "qsgmii";
132 phy-handle = <&qsgmii_phy2>;
133 phy-connection-type = "qsgmii";
137 phy-handle = <&qsgmii_phy1>;
138 phy-connection-type = "qsgmii";
142 phy-handle = <&qsgmii_phy3>;
143 phy-connection-type = "qsgmii";
147 qsgmii_phy1: ethernet-phy@1c {
151 qsgmii_phy2: ethernet-phy@1d {
155 qsgmii_phy3: ethernet-phy@1e {
159 qsgmii_phy4: ethernet-phy@1f {