arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Include file for NXP Layerscape-1028A family SoC.
   4  *
   5  * Copyright 2018-2020 NXP
   6  *
   7  * Harninder Rai <harninder.rai@nxp.com>
   8  *
   9  */
  10
  11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         compatible = "fsl,ls1028a";
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu0: cpu@0 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a72";
  28                         reg = <0x0>;
  29                         enable-method = "psci";
  30                         clocks = <&clockgen QORIQ_CLK_CMUX 0>;
  31                         next-level-cache = <&l2>;
  32                         cpu-idle-states = <&CPU_PW20>;
  33                         #cooling-cells = <2>;
  34                 };
  35
  36                 cpu1: cpu@1 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a72";
  39                         reg = <0x1>;
  40                         enable-method = "psci";
  41                         clocks = <&clockgen QORIQ_CLK_CMUX 0>;
  42                         next-level-cache = <&l2>;
  43                         cpu-idle-states = <&CPU_PW20>;
  44                         #cooling-cells = <2>;
  45                 };
  46
  47                 l2: l2-cache {
  48                         compatible = "cache";
  49                 };
  50         };
  51
  52         idle-states {
  53                 /*
  54                  * PSCI node is not added default, U-boot will add missing
  55                  * parts if it determines to use PSCI.
  56                  */
  57                 entry-method = "psci";
  58
  59                 CPU_PW20: cpu-pw20 {
  60                           compatible = "arm,idle-state";
  61                           idle-state-name = "PW20";
  62                           arm,psci-suspend-param = <0x0>;
  63                           entry-latency-us = <2000>;
  64                           exit-latency-us = <2000>;
  65                           min-residency-us = <6000>;
  66                 };
  67         };
  68
  69         rtc_clk: rtc-clk {
  70                 compatible = "fixed-clock";
  71                 #clock-cells = <0>;
  72                 clock-frequency = <32768>;
  73                 clock-output-names = "rtc_clk";
  74         };
  75
  76         sysclk: sysclk {
  77                 compatible = "fixed-clock";
  78                 #clock-cells = <0>;
  79                 clock-frequency = <100000000>;
  80                 clock-output-names = "sysclk";
  81         };
  82
  83         osc_27m: clock-osc-27m {
  84                 compatible = "fixed-clock";
  85                 #clock-cells = <0>;
  86                 clock-frequency = <27000000>;
  87                 clock-output-names = "phy_27m";
  88         };
  89
  90         firmware {
  91                 optee: optee  {
  92                         compatible = "linaro,optee-tz";
  93                         method = "smc";
  94                         status = "disabled";
  95                 };
  96         };
  97
  98         reboot {
  99                 compatible = "syscon-reboot";
 100                 regmap = <&rst>;
 101                 offset = <0>;
 102                 mask = <0x02>;
 103         };
 104
 105         timer {
 106                 compatible = "arm,armv8-timer";
 107                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
 108                                           IRQ_TYPE_LEVEL_LOW)>,
 109                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
 110                                           IRQ_TYPE_LEVEL_LOW)>,
 111                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
 112                                           IRQ_TYPE_LEVEL_LOW)>,
 113                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
 114                                           IRQ_TYPE_LEVEL_LOW)>;
 115         };
 116
 117         pmu {
 118                 compatible = "arm,cortex-a72-pmu";
 119                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 120         };
 121
 122         gic: interrupt-controller@6000000 {
 123                 compatible = "arm,gic-v3";
 124                 #address-cells = <2>;
 125                 #size-cells = <2>;
 126                 ranges;
 127                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
 128                         <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */
 129                 #interrupt-cells = <3>;
 130                 interrupt-controller;
 131                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
 132                                          IRQ_TYPE_LEVEL_LOW)>;
 133                 its: gic-its@6020000 {
 134                         compatible = "arm,gic-v3-its";
 135                         msi-controller;
 136                         reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */
 137                 };
 138         };
 139
 140         thermal-zones {
 141                 ddr-controller {
 142                         polling-delay-passive = <1000>;
 143                         polling-delay = <5000>;
 144                         thermal-sensors = <&tmu 0>;
 145
 146                         trips {
 147                                 ddr-ctrler-alert {
 148                                         temperature = <85000>;
 149                                         hysteresis = <2000>;
 150                                         type = "passive";
 151                                 };
 152
 153                                 ddr-ctrler-crit {
 154                                         temperature = <95000>;
 155                                         hysteresis = <2000>;
 156                                         type = "critical";
 157                                 };
 158                         };
 159                 };
 160
 161                 core-cluster {
 162                         polling-delay-passive = <1000>;
 163                         polling-delay = <5000>;
 164                         thermal-sensors = <&tmu 1>;
 165
 166                         trips {
 167                                 core_cluster_alert: core-cluster-alert {
 168                                         temperature = <85000>;
 169                                         hysteresis = <2000>;
 170                                         type = "passive";
 171                                 };
 172
 173                                 core_cluster_crit: core-cluster-crit {
 174                                         temperature = <95000>;
 175                                         hysteresis = <2000>;
 176                                         type = "critical";
 177                                 };
 178                         };
 179
 180                         cooling-maps {
 181                                 map0 {
 182                                         trip = <&core_cluster_alert>;
 183                                         cooling-device =
 184                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 185                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 186                                 };
 187                         };
 188                 };
 189         };
 190
 191         soc: soc {
 192                 compatible = "simple-bus";
 193                 #address-cells = <2>;
 194                 #size-cells = <2>;
 195                 ranges;
 196
 197                 ddr: memory-controller@1080000 {
 198                         compatible = "fsl,qoriq-memory-controller";
 199                         reg = <0x0 0x1080000 0x0 0x1000>;
 200                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 201                         little-endian;
 202                 };
 203
 204                 dcfg: syscon@1e00000 {
 205                         #address-cells = <1>;
 206                         #size-cells = <1>;
 207                         compatible = "fsl,ls1028a-dcfg", "syscon", "simple-mfd";
 208                         reg = <0x0 0x1e00000 0x0 0x10000>;
 209                         ranges = <0x0 0x0 0x1e00000 0x10000>;
 210                         little-endian;
 211
 212                         fspi_clk: clock-controller@900 {
 213                                 compatible = "fsl,ls1028a-flexspi-clk";
 214                                 reg = <0x900 0x4>;
 215                                 #clock-cells = <0>;
 216                                 clocks = <&clockgen QORIQ_CLK_HWACCEL 0>;
 217                                 clock-output-names = "fspi_clk";
 218                         };
 219                 };
 220
 221                 rst: syscon@1e60000 {
 222                         compatible = "syscon";
 223                         reg = <0x0 0x1e60000 0x0 0x10000>;
 224                         little-endian;
 225                 };
 226
 227                 efuse@1e80000 {
 228                         compatible = "fsl,ls1028a-sfp";
 229                         reg = <0x0 0x1e80000 0x0 0x10000>;
 230                         #address-cells = <1>;
 231                         #size-cells = <1>;
 232
 233                         ls1028a_uid: unique-id@1c {
 234                                 reg = <0x1c 0x8>;
 235                         };
 236                 };
 237
 238                 scfg: syscon@1fc0000 {
 239                         compatible = "fsl,ls1028a-scfg", "syscon";
 240                         reg = <0x0 0x1fc0000 0x0 0x10000>;
 241                         big-endian;
 242                 };
 243
 244                 clockgen: clock-controller@1300000 {
 245                         compatible = "fsl,ls1028a-clockgen";
 246                         reg = <0x0 0x1300000 0x0 0xa0000>;
 247                         #clock-cells = <2>;
 248                         clocks = <&sysclk>;
 249                 };
 250
 251                 i2c0: i2c@2000000 {
 252                         compatible = "fsl,vf610-i2c";
 253                         #address-cells = <1>;
 254                         #size-cells = <0>;
 255                         reg = <0x0 0x2000000 0x0 0x10000>;
 256                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 257                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 258                                             QORIQ_CLK_PLL_DIV(4)>;
 259                         status = "disabled";
 260                 };
 261
 262                 i2c1: i2c@2010000 {
 263                         compatible = "fsl,vf610-i2c";
 264                         #address-cells = <1>;
 265                         #size-cells = <0>;
 266                         reg = <0x0 0x2010000 0x0 0x10000>;
 267                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 268                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 269                                             QORIQ_CLK_PLL_DIV(4)>;
 270                         status = "disabled";
 271                 };
 272
 273                 i2c2: i2c@2020000 {
 274                         compatible = "fsl,vf610-i2c";
 275                         #address-cells = <1>;
 276                         #size-cells = <0>;
 277                         reg = <0x0 0x2020000 0x0 0x10000>;
 278                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 279                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 280                                             QORIQ_CLK_PLL_DIV(4)>;
 281                         status = "disabled";
 282                 };
 283
 284                 i2c3: i2c@2030000 {
 285                         compatible = "fsl,vf610-i2c";
 286                         #address-cells = <1>;
 287                         #size-cells = <0>;
 288                         reg = <0x0 0x2030000 0x0 0x10000>;
 289                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 290                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 291                                             QORIQ_CLK_PLL_DIV(4)>;
 292                         status = "disabled";
 293                 };
 294
 295                 i2c4: i2c@2040000 {
 296                         compatible = "fsl,vf610-i2c";
 297                         #address-cells = <1>;
 298                         #size-cells = <0>;
 299                         reg = <0x0 0x2040000 0x0 0x10000>;
 300                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 301                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 302                                             QORIQ_CLK_PLL_DIV(4)>;
 303                         status = "disabled";
 304                 };
 305
 306                 i2c5: i2c@2050000 {
 307                         compatible = "fsl,vf610-i2c";
 308                         #address-cells = <1>;
 309                         #size-cells = <0>;
 310                         reg = <0x0 0x2050000 0x0 0x10000>;
 311                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 312                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 313                                             QORIQ_CLK_PLL_DIV(4)>;
 314                         status = "disabled";
 315                 };
 316
 317                 i2c6: i2c@2060000 {
 318                         compatible = "fsl,vf610-i2c";
 319                         #address-cells = <1>;
 320                         #size-cells = <0>;
 321                         reg = <0x0 0x2060000 0x0 0x10000>;
 322                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 323                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 324                                             QORIQ_CLK_PLL_DIV(4)>;
 325                         status = "disabled";
 326                 };
 327
 328                 i2c7: i2c@2070000 {
 329                         compatible = "fsl,vf610-i2c";
 330                         #address-cells = <1>;
 331                         #size-cells = <0>;
 332                         reg = <0x0 0x2070000 0x0 0x10000>;
 333                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 334                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 335                                             QORIQ_CLK_PLL_DIV(4)>;
 336                         status = "disabled";
 337                 };
 338
 339                 fspi: spi@20c0000 {
 340                         compatible = "nxp,lx2160a-fspi";
 341                         #address-cells = <1>;
 342                         #size-cells = <0>;
 343                         reg = <0x0 0x20c0000 0x0 0x10000>,
 344                               <0x0 0x20000000 0x0 0x10000000>;
 345                         reg-names = "fspi_base", "fspi_mmap";
 346                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 347                         clocks = <&fspi_clk>, <&fspi_clk>;
 348                         clock-names = "fspi_en", "fspi";
 349                         status = "disabled";
 350                 };
 351
 352                 dspi0: spi@2100000 {
 353                         compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
 354                         #address-cells = <1>;
 355                         #size-cells = <0>;
 356                         reg = <0x0 0x2100000 0x0 0x10000>;
 357                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 358                         clock-names = "dspi";
 359                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 360                                             QORIQ_CLK_PLL_DIV(2)>;
 361                         dmas = <&edma0 0 62>, <&edma0 0 60>;
 362                         dma-names = "tx", "rx";
 363                         spi-num-chipselects = <4>;
 364                         little-endian;
 365                         status = "disabled";
 366                 };
 367
 368                 dspi1: spi@2110000 {
 369                         compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
 370                         #address-cells = <1>;
 371                         #size-cells = <0>;
 372                         reg = <0x0 0x2110000 0x0 0x10000>;
 373                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 374                         clock-names = "dspi";
 375                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 376                                             QORIQ_CLK_PLL_DIV(2)>;
 377                         dmas = <&edma0 0 58>, <&edma0 0 56>;
 378                         dma-names = "tx", "rx";
 379                         spi-num-chipselects = <4>;
 380                         little-endian;
 381                         status = "disabled";
 382                 };
 383
 384                 dspi2: spi@2120000 {
 385                         compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
 386                         #address-cells = <1>;
 387                         #size-cells = <0>;
 388                         reg = <0x0 0x2120000 0x0 0x10000>;
 389                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 390                         clock-names = "dspi";
 391                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 392                                             QORIQ_CLK_PLL_DIV(2)>;
 393                         dmas = <&edma0 0 54>, <&edma0 0 2>;
 394                         dma-names = "tx", "rx";
 395                         spi-num-chipselects = <3>;
 396                         little-endian;
 397                         status = "disabled";
 398                 };
 399
 400                 esdhc: mmc@2140000 {
 401                         compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
 402                         reg = <0x0 0x2140000 0x0 0x10000>;
 403                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 404                         clock-frequency = <0>; /* fixed up by bootloader */
 405                         clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
 406                         voltage-ranges = <1800 1800 3300 3300>;
 407                         sdhci,auto-cmd12;
 408                         little-endian;
 409                         bus-width = <4>;
 410                         status = "disabled";
 411                 };
 412
 413                 esdhc1: mmc@2150000 {
 414                         compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
 415                         reg = <0x0 0x2150000 0x0 0x10000>;
 416                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 417                         clock-frequency = <0>; /* fixed up by bootloader */
 418                         clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
 419                         voltage-ranges = <1800 1800>;
 420                         sdhci,auto-cmd12;
 421                         non-removable;
 422                         little-endian;
 423                         bus-width = <4>;
 424                         status = "disabled";
 425                 };
 426
 427                 can0: can@2180000 {
 428                         compatible = "fsl,lx2160ar1-flexcan";
 429                         reg = <0x0 0x2180000 0x0 0x10000>;
 430                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 431                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 432                                             QORIQ_CLK_PLL_DIV(2)>,
 433                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 434                                             QORIQ_CLK_PLL_DIV(2)>;
 435                         clock-names = "ipg", "per";
 436                         status = "disabled";
 437                 };
 438
 439                 can1: can@2190000 {
 440                         compatible = "fsl,lx2160ar1-flexcan";
 441                         reg = <0x0 0x2190000 0x0 0x10000>;
 442                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 443                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 444                                             QORIQ_CLK_PLL_DIV(2)>,
 445                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 446                                             QORIQ_CLK_PLL_DIV(2)>;
 447                         clock-names = "ipg", "per";
 448                         status = "disabled";
 449                 };
 450
 451                 duart0: serial@21c0500 {
 452                         compatible = "fsl,ns16550", "ns16550a";
 453                         reg = <0x00 0x21c0500 0x0 0x100>;
 454                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 455                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 456                                             QORIQ_CLK_PLL_DIV(2)>;
 457                         status = "disabled";
 458                 };
 459
 460                 duart1: serial@21c0600 {
 461                         compatible = "fsl,ns16550", "ns16550a";
 462                         reg = <0x00 0x21c0600 0x0 0x100>;
 463                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 464                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 465                                             QORIQ_CLK_PLL_DIV(2)>;
 466                         status = "disabled";
 467                 };
 468
 469
 470                 lpuart0: serial@2260000 {
 471                         compatible = "fsl,ls1028a-lpuart";
 472                         reg = <0x0 0x2260000 0x0 0x1000>;
 473                         interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
 474                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 475                                             QORIQ_CLK_PLL_DIV(2)>;
 476                         clock-names = "ipg";
 477                         dma-names = "rx","tx";
 478                         dmas = <&edma0 1 32>,
 479                                <&edma0 1 33>;
 480                         status = "disabled";
 481                 };
 482
 483                 lpuart1: serial@2270000 {
 484                         compatible = "fsl,ls1028a-lpuart";
 485                         reg = <0x0 0x2270000 0x0 0x1000>;
 486                         interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
 487                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 488                                             QORIQ_CLK_PLL_DIV(2)>;
 489                         clock-names = "ipg";
 490                         dma-names = "rx","tx";
 491                         dmas = <&edma0 1 30>,
 492                                <&edma0 1 31>;
 493                         status = "disabled";
 494                 };
 495
 496                 lpuart2: serial@2280000 {
 497                         compatible = "fsl,ls1028a-lpuart";
 498                         reg = <0x0 0x2280000 0x0 0x1000>;
 499                         interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
 500                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 501                                             QORIQ_CLK_PLL_DIV(2)>;
 502                         clock-names = "ipg";
 503                         dma-names = "rx","tx";
 504                         dmas = <&edma0 1 28>,
 505                                <&edma0 1 29>;
 506                         status = "disabled";
 507                 };
 508
 509                 lpuart3: serial@2290000 {
 510                         compatible = "fsl,ls1028a-lpuart";
 511                         reg = <0x0 0x2290000 0x0 0x1000>;
 512                         interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
 513                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 514                                             QORIQ_CLK_PLL_DIV(2)>;
 515                         clock-names = "ipg";
 516                         dma-names = "rx","tx";
 517                         dmas = <&edma0 1 26>,
 518                                <&edma0 1 27>;
 519                         status = "disabled";
 520                 };
 521
 522                 lpuart4: serial@22a0000 {
 523                         compatible = "fsl,ls1028a-lpuart";
 524                         reg = <0x0 0x22a0000 0x0 0x1000>;
 525                         interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
 526                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 527                                             QORIQ_CLK_PLL_DIV(2)>;
 528                         clock-names = "ipg";
 529                         dma-names = "rx","tx";
 530                         dmas = <&edma0 1 24>,
 531                                <&edma0 1 25>;
 532                         status = "disabled";
 533                 };
 534
 535                 lpuart5: serial@22b0000 {
 536                         compatible = "fsl,ls1028a-lpuart";
 537                         reg = <0x0 0x22b0000 0x0 0x1000>;
 538                         interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
 539                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 540                                             QORIQ_CLK_PLL_DIV(2)>;
 541                         clock-names = "ipg";
 542                         dma-names = "rx","tx";
 543                         dmas = <&edma0 1 22>,
 544                                <&edma0 1 23>;
 545                         status = "disabled";
 546                 };
 547
 548                 edma0: dma-controller@22c0000 {
 549                         #dma-cells = <2>;
 550                         compatible = "fsl,ls1028a-edma", "fsl,vf610-edma";
 551                         reg = <0x0 0x22c0000 0x0 0x10000>,
 552                               <0x0 0x22d0000 0x0 0x10000>,
 553                               <0x0 0x22e0000 0x0 0x10000>;
 554                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 555                                      <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 556                         interrupt-names = "edma-tx", "edma-err";
 557                         dma-channels = <32>;
 558                         clock-names = "dmamux0", "dmamux1";
 559                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 560                                             QORIQ_CLK_PLL_DIV(2)>,
 561                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 562                                             QORIQ_CLK_PLL_DIV(2)>;
 563                 };
 564
 565                 gpio1: gpio@2300000 {
 566                         compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
 567                         reg = <0x0 0x2300000 0x0 0x10000>;
 568                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 569                         gpio-controller;
 570                         #gpio-cells = <2>;
 571                         interrupt-controller;
 572                         #interrupt-cells = <2>;
 573                         little-endian;
 574                 };
 575
 576                 gpio2: gpio@2310000 {
 577                         compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
 578                         reg = <0x0 0x2310000 0x0 0x10000>;
 579                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 580                         gpio-controller;
 581                         #gpio-cells = <2>;
 582                         interrupt-controller;
 583                         #interrupt-cells = <2>;
 584                         little-endian;
 585                 };
 586
 587                 gpio3: gpio@2320000 {
 588                         compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
 589                         reg = <0x0 0x2320000 0x0 0x10000>;
 590                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 591                         gpio-controller;
 592                         #gpio-cells = <2>;
 593                         interrupt-controller;
 594                         #interrupt-cells = <2>;
 595                         little-endian;
 596                 };
 597
 598                 usb0: usb@3100000 {
 599                         compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
 600                         reg = <0x0 0x3100000 0x0 0x10000>;
 601                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 602                         snps,dis_rxdet_inp3_quirk;
 603                         snps,quirk-frame-length-adjustment = <0x20>;
 604                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 605                         status = "disabled";
 606                 };
 607
 608                 usb1: usb@3110000 {
 609                         compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
 610                         reg = <0x0 0x3110000 0x0 0x10000>;
 611                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 612                         snps,dis_rxdet_inp3_quirk;
 613                         snps,quirk-frame-length-adjustment = <0x20>;
 614                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 615                         status = "disabled";
 616                 };
 617
 618                 sata: sata@3200000 {
 619                         compatible = "fsl,ls1028a-ahci";
 620                         reg = <0x0 0x3200000 0x0 0x10000>,
 621                                 <0x7 0x100520 0x0 0x4>;
 622                         reg-names = "ahci", "sata-ecc";
 623                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 624                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 625                                             QORIQ_CLK_PLL_DIV(2)>;
 626                         status = "disabled";
 627                 };
 628
 629                 pcie1: pcie@3400000 {
 630                         compatible = "fsl,ls1028a-pcie";
 631                         reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
 632                               <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
 633                         reg-names = "regs", "config";
 634                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
 635                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
 636                         interrupt-names = "pme", "aer";
 637                         #address-cells = <3>;
 638                         #size-cells = <2>;
 639                         device_type = "pci";
 640                         dma-coherent;
 641                         num-viewport = <8>;
 642                         bus-range = <0x0 0xff>;
 643                         ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000   /* downstream I/O */
 644                                   0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 645                         msi-parent = <&its>;
 646                         #interrupt-cells = <1>;
 647                         interrupt-map-mask = <0 0 0 7>;
 648                         interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 649                                         <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 650                                         <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 651                                         <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 652                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
 653                         status = "disabled";
 654                 };
 655
 656                 pcie_ep1: pcie-ep@3400000 {
 657                         compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep";
 658                         reg = <0x00 0x03400000 0x0 0x00100000
 659                                0x80 0x00000000 0x8 0x00000000>;
 660                         reg-names = "regs", "addr_space";
 661                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
 662                         interrupt-names = "pme";
 663                         num-ib-windows = <6>;
 664                         num-ob-windows = <8>;
 665                         status = "disabled";
 666                 };
 667
 668                 pcie2: pcie@3500000 {
 669                         compatible = "fsl,ls1028a-pcie";
 670                         reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
 671                               <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
 672                         reg-names = "regs", "config";
 673                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 674                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 675                         interrupt-names = "pme", "aer";
 676                         #address-cells = <3>;
 677                         #size-cells = <2>;
 678                         device_type = "pci";
 679                         dma-coherent;
 680                         num-viewport = <8>;
 681                         bus-range = <0x0 0xff>;
 682                         ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000   /* downstream I/O */
 683                                   0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 684                         msi-parent = <&its>;
 685                         #interrupt-cells = <1>;
 686                         interrupt-map-mask = <0 0 0 7>;
 687                         interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 688                                         <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 689                                         <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 690                                         <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 691                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
 692                         status = "disabled";
 693                 };
 694
 695                 pcie_ep2: pcie-ep@3500000 {
 696                         compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep";
 697                         reg = <0x00 0x03500000 0x0 0x00100000
 698                                0x88 0x00000000 0x8 0x00000000>;
 699                         reg-names = "regs", "addr_space";
 700                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
 701                         interrupt-names = "pme";
 702                         num-ib-windows = <6>;
 703                         num-ob-windows = <8>;
 704                         status = "disabled";
 705                 };
 706
 707                 smmu: iommu@5000000 {
 708                         compatible = "arm,mmu-500";
 709                         reg = <0 0x5000000 0 0x800000>;
 710                         #global-interrupts = <8>;
 711                         #iommu-cells = <1>;
 712                         stream-match-mask = <0x7c00>;
 713                         /* global secure fault */
 714                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 715                         /* combined secure interrupt */
 716                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 717                         /* global non-secure fault */
 718                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 719                         /* combined non-secure interrupt */
 720                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 721                         /* performance counter interrupts 0-7 */
 722                                      <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
 723                                      <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 724                         /* per context interrupt, 64 interrupts */
 725                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 726                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 727                                      <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
 728                                      <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 729                                      <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 730                                      <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 731                                      <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
 732                                      <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 733                                      <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 734                                      <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
 735                                      <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
 736                                      <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
 737                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
 738                                      <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
 739                                      <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
 740                                      <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
 741                                      <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
 742                                      <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
 743                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
 744                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
 745                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
 746                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
 747                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
 748                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
 749                                      <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
 750                                      <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
 751                                      <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
 752                                      <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
 753                                      <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
 754                                      <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
 755                                      <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
 756                                      <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
 757                 };
 758
 759                 crypto: crypto@8000000 {
 760                         compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
 761                         fsl,sec-era = <10>;
 762                         #address-cells = <1>;
 763                         #size-cells = <1>;
 764                         ranges = <0x0 0x00 0x8000000 0x100000>;
 765                         reg = <0x00 0x8000000 0x0 0x100000>;
 766                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 767                         dma-coherent;
 768
 769                         sec_jr0: jr@10000 {
 770                                 compatible = "fsl,sec-v5.0-job-ring",
 771                                              "fsl,sec-v4.0-job-ring";
 772                                 reg = <0x10000 0x10000>;
 773                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 774                         };
 775
 776                         sec_jr1: jr@20000 {
 777                                 compatible = "fsl,sec-v5.0-job-ring",
 778                                              "fsl,sec-v4.0-job-ring";
 779                                 reg = <0x20000 0x10000>;
 780                                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 781                         };
 782
 783                         sec_jr2: jr@30000 {
 784                                 compatible = "fsl,sec-v5.0-job-ring",
 785                                              "fsl,sec-v4.0-job-ring";
 786                                 reg = <0x30000 0x10000>;
 787                                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 788                         };
 789
 790                         sec_jr3: jr@40000 {
 791                                 compatible = "fsl,sec-v5.0-job-ring",
 792                                              "fsl,sec-v4.0-job-ring";
 793                                 reg = <0x40000 0x10000>;
 794                                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 795                         };
 796                 };
 797
 798                 qdma: dma-controller@8380000 {
 799                         compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma";
 800                         reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
 801                               <0x0 0x8390000 0x0 0x10000>, /* Status regs */
 802                               <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
 803                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 804                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 805                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
 806                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 807                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
 808                         interrupt-names = "qdma-error", "qdma-queue0",
 809                                 "qdma-queue1", "qdma-queue2", "qdma-queue3";
 810                         dma-channels = <8>;
 811                         block-number = <1>;
 812                         block-offset = <0x10000>;
 813                         fsl,dma-queues = <2>;
 814                         status-sizes = <64>;
 815                         queue-sizes = <64 64>;
 816                 };
 817
 818                 cluster1_core0_watchdog: watchdog@c000000 {
 819                         compatible = "arm,sp805", "arm,primecell";
 820                         reg = <0x0 0xc000000 0x0 0x1000>;
 821                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 822                                             QORIQ_CLK_PLL_DIV(16)>,
 823                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 824                                             QORIQ_CLK_PLL_DIV(16)>;
 825                         clock-names = "wdog_clk", "apb_pclk";
 826                 };
 827
 828                 cluster1_core1_watchdog: watchdog@c010000 {
 829                         compatible = "arm,sp805", "arm,primecell";
 830                         reg = <0x0 0xc010000 0x0 0x1000>;
 831                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 832                                             QORIQ_CLK_PLL_DIV(16)>,
 833                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 834                                             QORIQ_CLK_PLL_DIV(16)>;
 835                         clock-names = "wdog_clk", "apb_pclk";
 836                 };
 837
 838                 malidp0: display@f080000 {
 839                         compatible = "arm,mali-dp500";
 840                         reg = <0x0 0xf080000 0x0 0x10000>;
 841                         interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
 842                                      <0 223 IRQ_TYPE_LEVEL_HIGH>;
 843                         interrupt-names = "DE", "SE";
 844                         clocks = <&dpclk>,
 845                                  <&clockgen QORIQ_CLK_HWACCEL 2>,
 846                                  <&clockgen QORIQ_CLK_HWACCEL 2>,
 847                                  <&clockgen QORIQ_CLK_HWACCEL 2>;
 848                         clock-names = "pxlclk", "mclk", "aclk", "pclk";
 849                         arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
 850                         arm,malidp-arqos-value = <0xd000d000>;
 851
 852                         port {
 853                                 dpi0_out: endpoint {
 854
 855                                 };
 856                         };
 857                 };
 858
 859                 gpu: gpu@f0c0000 {
 860                         compatible = "vivante,gc";
 861                         reg = <0x0 0xf0c0000 0x0 0x10000>;
 862                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 863                         clocks = <&clockgen QORIQ_CLK_HWACCEL 2>,
 864                                  <&clockgen QORIQ_CLK_HWACCEL 2>,
 865                                  <&clockgen QORIQ_CLK_HWACCEL 2>;
 866                         clock-names = "core", "shader", "bus";
 867                         #cooling-cells = <2>;
 868                 };
 869
 870                 sai1: audio-controller@f100000 {
 871                         #sound-dai-cells = <0>;
 872                         compatible = "fsl,vf610-sai";
 873                         reg = <0x0 0xf100000 0x0 0x10000>;
 874                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 875                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 876                                             QORIQ_CLK_PLL_DIV(2)>,
 877                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 878                                             QORIQ_CLK_PLL_DIV(2)>,
 879                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 880                                             QORIQ_CLK_PLL_DIV(2)>,
 881                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 882                                             QORIQ_CLK_PLL_DIV(2)>;
 883                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 884                         dma-names = "tx", "rx";
 885                         dmas = <&edma0 1 4>,
 886                                <&edma0 1 3>;
 887                         fsl,sai-asynchronous;
 888                         status = "disabled";
 889                 };
 890
 891                 sai2: audio-controller@f110000 {
 892                         #sound-dai-cells = <0>;
 893                         compatible = "fsl,vf610-sai";
 894                         reg = <0x0 0xf110000 0x0 0x10000>;
 895                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 896                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 897                                             QORIQ_CLK_PLL_DIV(2)>,
 898                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 899                                             QORIQ_CLK_PLL_DIV(2)>,
 900                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 901                                             QORIQ_CLK_PLL_DIV(2)>,
 902                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 903                                             QORIQ_CLK_PLL_DIV(2)>;
 904                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 905                         dma-names = "tx", "rx";
 906                         dmas = <&edma0 1 6>,
 907                                <&edma0 1 5>;
 908                         fsl,sai-asynchronous;
 909                         status = "disabled";
 910                 };
 911
 912                 sai3: audio-controller@f120000 {
 913                         #sound-dai-cells = <0>;
 914                         compatible = "fsl,vf610-sai";
 915                         reg = <0x0 0xf120000 0x0 0x10000>;
 916                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 917                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 918                                             QORIQ_CLK_PLL_DIV(2)>,
 919                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 920                                             QORIQ_CLK_PLL_DIV(2)>,
 921                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 922                                             QORIQ_CLK_PLL_DIV(2)>,
 923                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 924                                             QORIQ_CLK_PLL_DIV(2)>;
 925                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 926                         dma-names = "tx", "rx";
 927                         dmas = <&edma0 1 8>,
 928                                <&edma0 1 7>;
 929                         fsl,sai-asynchronous;
 930                         status = "disabled";
 931                 };
 932
 933                 sai4: audio-controller@f130000 {
 934                         #sound-dai-cells = <0>;
 935                         compatible = "fsl,vf610-sai";
 936                         reg = <0x0 0xf130000 0x0 0x10000>;
 937                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 938                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 939                                             QORIQ_CLK_PLL_DIV(2)>,
 940                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 941                                             QORIQ_CLK_PLL_DIV(2)>,
 942                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 943                                             QORIQ_CLK_PLL_DIV(2)>,
 944                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 945                                             QORIQ_CLK_PLL_DIV(2)>;
 946                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 947                         dma-names = "tx", "rx";
 948                         dmas = <&edma0 1 10>,
 949                                <&edma0 1 9>;
 950                         fsl,sai-asynchronous;
 951                         status = "disabled";
 952                 };
 953
 954                 sai5: audio-controller@f140000 {
 955                         #sound-dai-cells = <0>;
 956                         compatible = "fsl,vf610-sai";
 957                         reg = <0x0 0xf140000 0x0 0x10000>;
 958                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 959                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 960                                             QORIQ_CLK_PLL_DIV(2)>,
 961                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 962                                             QORIQ_CLK_PLL_DIV(2)>,
 963                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 964                                             QORIQ_CLK_PLL_DIV(2)>,
 965                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 966                                             QORIQ_CLK_PLL_DIV(2)>;
 967                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 968                         dma-names = "tx", "rx";
 969                         dmas = <&edma0 1 12>,
 970                                <&edma0 1 11>;
 971                         fsl,sai-asynchronous;
 972                         status = "disabled";
 973                 };
 974
 975                 sai6: audio-controller@f150000 {
 976                         #sound-dai-cells = <0>;
 977                         compatible = "fsl,vf610-sai";
 978                         reg = <0x0 0xf150000 0x0 0x10000>;
 979                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 980                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 981                                             QORIQ_CLK_PLL_DIV(2)>,
 982                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 983                                             QORIQ_CLK_PLL_DIV(2)>,
 984                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 985                                             QORIQ_CLK_PLL_DIV(2)>,
 986                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 987                                             QORIQ_CLK_PLL_DIV(2)>;
 988                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 989                         dma-names = "tx", "rx";
 990                         dmas = <&edma0 1 14>,
 991                                <&edma0 1 13>;
 992                         fsl,sai-asynchronous;
 993                         status = "disabled";
 994                 };
 995
 996                 dpclk: clock-controller@f1f0000 {
 997                         compatible = "fsl,ls1028a-plldig";
 998                         reg = <0x0 0xf1f0000 0x0 0x10000>;
 999                         #clock-cells = <0>;
1000                         clocks = <&osc_27m>;
1001                 };
1002
1003                 tmu: tmu@1f80000 {
1004                         compatible = "fsl,qoriq-tmu";
1005                         reg = <0x0 0x1f80000 0x0 0x10000>;
1006                         interrupts = <0 23 0x4>;
1007                         fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
1008                         fsl,tmu-calibration = <0x00000000 0x00000024
1009                                                0x00000001 0x0000002b
1010                                                0x00000002 0x00000031
1011                                                0x00000003 0x00000038
1012                                                0x00000004 0x0000003f
1013                                                0x00000005 0x00000045
1014                                                0x00000006 0x0000004c
1015                                                0x00000007 0x00000053
1016                                                0x00000008 0x00000059
1017                                                0x00000009 0x00000060
1018                                                0x0000000a 0x00000066
1019                                                0x0000000b 0x0000006d
1020
1021                                                0x00010000 0x0000001c
1022                                                0x00010001 0x00000024
1023                                                0x00010002 0x0000002c
1024                                                0x00010003 0x00000035
1025                                                0x00010004 0x0000003d
1026                                                0x00010005 0x00000045
1027                                                0x00010006 0x0000004d
1028                                                0x00010007 0x00000055
1029                                                0x00010008 0x0000005e
1030                                                0x00010009 0x00000066
1031                                                0x0001000a 0x0000006e
1032
1033                                                0x00020000 0x00000018
1034                                                0x00020001 0x00000022
1035                                                0x00020002 0x0000002d
1036                                                0x00020003 0x00000038
1037                                                0x00020004 0x00000043
1038                                                0x00020005 0x0000004d
1039                                                0x00020006 0x00000058
1040                                                0x00020007 0x00000063
1041                                                0x00020008 0x0000006e
1042
1043                                                0x00030000 0x00000010
1044                                                0x00030001 0x0000001c
1045                                                0x00030002 0x00000029
1046                                                0x00030003 0x00000036
1047                                                0x00030004 0x00000042
1048                                                0x00030005 0x0000004f
1049                                                0x00030006 0x0000005b
1050                                                0x00030007 0x00000068>;
1051                         little-endian;
1052                         #thermal-sensor-cells = <1>;
1053                 };
1054
1055                 pcie@1f0000000 { /* Integrated Endpoint Root Complex */
1056                         compatible = "pci-host-ecam-generic";
1057                         reg = <0x01 0xf0000000 0x0 0x100000>;
1058                         #address-cells = <3>;
1059                         #size-cells = <2>;
1060                         msi-parent = <&its>;
1061                         device_type = "pci";
1062                         bus-range = <0x0 0x0>;
1063                         dma-coherent;
1064                         msi-map = <0 &its 0x17 0xe>;
1065                         iommu-map = <0 &smmu 0x17 0xe>;
1066                                   /* PF0-6 BAR0 - non-prefetchable memory */
1067                         ranges = <0x82000000 0x1 0xf8000000  0x1 0xf8000000  0x0 0x160000
1068                                   /* PF0-6 BAR2 - prefetchable memory */
1069                                   0xc2000000 0x1 0xf8160000  0x1 0xf8160000  0x0 0x070000
1070                                   /* PF0: VF0-1 BAR0 - non-prefetchable memory */
1071                                   0x82000000 0x1 0xf81d0000  0x1 0xf81d0000  0x0 0x020000
1072                                   /* PF0: VF0-1 BAR2 - prefetchable memory */
1073                                   0xc2000000 0x1 0xf81f0000  0x1 0xf81f0000  0x0 0x020000
1074                                   /* PF1: VF0-1 BAR0 - non-prefetchable memory */
1075                                   0x82000000 0x1 0xf8210000  0x1 0xf8210000  0x0 0x020000
1076                                   /* PF1: VF0-1 BAR2 - prefetchable memory */
1077                                   0xc2000000 0x1 0xf8230000  0x1 0xf8230000  0x0 0x020000
1078                                   /* BAR4 (PF5) - non-prefetchable memory */
1079                                   0x82000000 0x1 0xfc000000  0x1 0xfc000000  0x0 0x400000>;
1080
1081                         enetc_port0: ethernet@0,0 {
1082                                 compatible = "fsl,enetc";
1083                                 reg = <0x000000 0 0 0 0>;
1084                                 status = "disabled";
1085                         };
1086
1087                         enetc_port1: ethernet@0,1 {
1088                                 compatible = "fsl,enetc";
1089                                 reg = <0x000100 0 0 0 0>;
1090                                 status = "disabled";
1091                         };
1092
1093                         enetc_port2: ethernet@0,2 {
1094                                 compatible = "fsl,enetc";
1095                                 reg = <0x000200 0 0 0 0>;
1096                                 phy-mode = "internal";
1097                                 status = "disabled";
1098
1099                                 fixed-link {
1100                                         speed = <2500>;
1101                                         full-duplex;
1102                                         pause;
1103                                 };
1104                         };
1105
1106                         enetc_mdio_pf3: mdio@0,3 {
1107                                 compatible = "fsl,enetc-mdio";
1108                                 reg = <0x000300 0 0 0 0>;
1109                                 #address-cells = <1>;
1110                                 #size-cells = <0>;
1111                         };
1112
1113                         ethernet@0,4 {
1114                                 compatible = "fsl,enetc-ptp";
1115                                 reg = <0x000400 0 0 0 0>;
1116                                 clocks = <&clockgen QORIQ_CLK_HWACCEL 3>;
1117                                 little-endian;
1118                                 fsl,extts-fifo;
1119                         };
1120
1121                         mscc_felix: ethernet-switch@0,5 {
1122                                 reg = <0x000500 0 0 0 0>;
1123                                 /* IEP INT_B */
1124                                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1125                                 status = "disabled";
1126
1127                                 mscc_felix_ports: ports {
1128                                         #address-cells = <1>;
1129                                         #size-cells = <0>;
1130
1131                                         /* External ports */
1132                                         mscc_felix_port0: port@0 {
1133                                                 reg = <0>;
1134                                                 status = "disabled";
1135                                         };
1136
1137                                         mscc_felix_port1: port@1 {
1138                                                 reg = <1>;
1139                                                 status = "disabled";
1140                                         };
1141
1142                                         mscc_felix_port2: port@2 {
1143                                                 reg = <2>;
1144                                                 status = "disabled";
1145                                         };
1146
1147                                         mscc_felix_port3: port@3 {
1148                                                 reg = <3>;
1149                                                 status = "disabled";
1150                                         };
1151
1152                                         /* Internal ports */
1153                                         mscc_felix_port4: port@4 {
1154                                                 reg = <4>;
1155                                                 phy-mode = "internal";
1156                                                 status = "disabled";
1157
1158                                                 fixed-link {
1159                                                         speed = <2500>;
1160                                                         full-duplex;
1161                                                         pause;
1162                                                 };
1163                                         };
1164
1165                                         mscc_felix_port5: port@5 {
1166                                                 reg = <5>;
1167                                                 phy-mode = "internal";
1168                                                 status = "disabled";
1169
1170                                                 fixed-link {
1171                                                         speed = <1000>;
1172                                                         full-duplex;
1173                                                         pause;
1174                                                 };
1175                                         };
1176                                 };
1177                         };
1178
1179                         enetc_port3: ethernet@0,6 {
1180                                 compatible = "fsl,enetc";
1181                                 reg = <0x000600 0 0 0 0>;
1182                                 phy-mode = "internal";
1183                                 status = "disabled";
1184
1185                                 fixed-link {
1186                                         speed = <1000>;
1187                                         full-duplex;
1188                                         pause;
1189                                 };
1190                         };
1191
1192                         rcec@1f,0 {
1193                                 reg = <0x00f800 0 0 0 0>;
1194                                 /* IEP INT_A */
1195                                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1196                         };
1197                 };
1198
1199                 /* Integrated Endpoint Register Block */
1200                 ierb@1f0800000 {
1201                         compatible = "fsl,ls1028a-enetc-ierb";
1202                         reg = <0x01 0xf0800000 0x0 0x10000>;
1203                 };
1204
1205                 pwm0: pwm@2800000 {
1206                         compatible = "fsl,vf610-ftm-pwm";
1207                         #pwm-cells = <3>;
1208                         reg = <0x0 0x2800000 0x0 0x10000>;
1209                         clock-names = "ftm_sys", "ftm_ext",
1210                                       "ftm_fix", "ftm_cnt_clk_en";
1211                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1212                                  <&rtc_clk>, <&clockgen 4 1>;
1213                         status = "disabled";
1214                 };
1215
1216                 pwm1: pwm@2810000 {
1217                         compatible = "fsl,vf610-ftm-pwm";
1218                         #pwm-cells = <3>;
1219                         reg = <0x0 0x2810000 0x0 0x10000>;
1220                         clock-names = "ftm_sys", "ftm_ext",
1221                                       "ftm_fix", "ftm_cnt_clk_en";
1222                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1223                                  <&rtc_clk>, <&clockgen 4 1>;
1224                         status = "disabled";
1225                 };
1226
1227                 pwm2: pwm@2820000 {
1228                         compatible = "fsl,vf610-ftm-pwm";
1229                         #pwm-cells = <3>;
1230                         reg = <0x0 0x2820000 0x0 0x10000>;
1231                         clock-names = "ftm_sys", "ftm_ext",
1232                                       "ftm_fix", "ftm_cnt_clk_en";
1233                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1234                                  <&rtc_clk>, <&clockgen 4 1>;
1235                         status = "disabled";
1236                 };
1237
1238                 pwm3: pwm@2830000 {
1239                         compatible = "fsl,vf610-ftm-pwm";
1240                         #pwm-cells = <3>;
1241                         reg = <0x0 0x2830000 0x0 0x10000>;
1242                         clock-names = "ftm_sys", "ftm_ext",
1243                                       "ftm_fix", "ftm_cnt_clk_en";
1244                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1245                                  <&rtc_clk>, <&clockgen 4 1>;
1246                         status = "disabled";
1247                 };
1248
1249                 pwm4: pwm@2840000 {
1250                         compatible = "fsl,vf610-ftm-pwm";
1251                         #pwm-cells = <3>;
1252                         reg = <0x0 0x2840000 0x0 0x10000>;
1253                         clock-names = "ftm_sys", "ftm_ext",
1254                                       "ftm_fix", "ftm_cnt_clk_en";
1255                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1256                                  <&rtc_clk>, <&clockgen 4 1>;
1257                         status = "disabled";
1258                 };
1259
1260                 pwm5: pwm@2850000 {
1261                         compatible = "fsl,vf610-ftm-pwm";
1262                         #pwm-cells = <3>;
1263                         reg = <0x0 0x2850000 0x0 0x10000>;
1264                         clock-names = "ftm_sys", "ftm_ext",
1265                                       "ftm_fix", "ftm_cnt_clk_en";
1266                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1267                                  <&rtc_clk>, <&clockgen 4 1>;
1268                         status = "disabled";
1269                 };
1270
1271                 pwm6: pwm@2860000 {
1272                         compatible = "fsl,vf610-ftm-pwm";
1273                         #pwm-cells = <3>;
1274                         reg = <0x0 0x2860000 0x0 0x10000>;
1275                         clock-names = "ftm_sys", "ftm_ext",
1276                                       "ftm_fix", "ftm_cnt_clk_en";
1277                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1278                                  <&rtc_clk>, <&clockgen 4 1>;
1279                         status = "disabled";
1280                 };
1281
1282                 pwm7: pwm@2870000 {
1283                         compatible = "fsl,vf610-ftm-pwm";
1284                         #pwm-cells = <3>;
1285                         reg = <0x0 0x2870000 0x0 0x10000>;
1286                         clock-names = "ftm_sys", "ftm_ext",
1287                                       "ftm_fix", "ftm_cnt_clk_en";
1288                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1289                                  <&rtc_clk>, <&clockgen 4 1>;
1290                         status = "disabled";
1291                 };
1292
1293                 rcpm: power-controller@1e34040 {
1294                         compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+";
1295                         reg = <0x0 0x1e34040 0x0 0x1c>;
1296                         #fsl,rcpm-wakeup-cells = <7>;
1297                         little-endian;
1298                 };
1299
1300                 ftm_alarm0: timer@2800000 {
1301                         compatible = "fsl,ls1028a-ftm-alarm";
1302                         reg = <0x0 0x2800000 0x0 0x10000>;
1303                         fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
1304                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1305                         status = "disabled";
1306                 };
1307
1308                 ftm_alarm1: timer@2810000 {
1309                         compatible = "fsl,ls1028a-ftm-alarm";
1310                         reg = <0x0 0x2810000 0x0 0x10000>;
1311                         fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
1312                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1313                         status = "disabled";
1314                 };
1315         };
1316
1317 };