arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Include file for NXP Layerscape-1012A family SoC.
   4  *
   5  * Copyright 2016 Freescale Semiconductor, Inc.
   6  * Copyright 2019-2020 NXP
   7  *
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/thermal/thermal.h>
  12
  13 / {
  14         compatible = "fsl,ls1012a";
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 crypto = &crypto;
  21                 rtc1 = &ftm_alarm0;
  22                 rtic-a = &rtic_a;
  23                 rtic-b = &rtic_b;
  24                 rtic-c = &rtic_c;
  25                 rtic-d = &rtic_d;
  26                 sec-mon = &sec_mon;
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu0: cpu@0 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a53";
  36                         reg = <0x0>;
  37                         clocks = <&clockgen 1 0>;
  38                         #cooling-cells = <2>;
  39                         cpu-idle-states = <&CPU_PH20>;
  40                 };
  41         };
  42
  43         idle-states {
  44                 /*
  45                  * PSCI node is not added default, U-boot will add missing
  46                  * parts if it determines to use PSCI.
  47                  */
  48                 entry-method = "psci";
  49
  50                 CPU_PH20: cpu-ph20 {
  51                         compatible = "arm,idle-state";
  52                         idle-state-name = "PH20";
  53                         arm,psci-suspend-param = <0x0>;
  54                         entry-latency-us = <1000>;
  55                         exit-latency-us = <1000>;
  56                         min-residency-us = <3000>;
  57                 };
  58         };
  59
  60         sysclk: sysclk {
  61                 compatible = "fixed-clock";
  62                 #clock-cells = <0>;
  63                 clock-frequency = <125000000>;
  64                 clock-output-names = "sysclk";
  65         };
  66
  67         coreclk: coreclk {
  68                 compatible = "fixed-clock";
  69                 #clock-cells = <0>;
  70                 clock-frequency = <100000000>;
  71                 clock-output-names = "coreclk";
  72         };
  73
  74         timer {
  75                 compatible = "arm,armv8-timer";
  76                 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
  77                              <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
  78                              <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
  79                              <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
  80         };
  81
  82         pmu {
  83                 compatible = "arm,armv8-pmuv3";
  84                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
  85         };
  86
  87         gic: interrupt-controller@1400000 {
  88                 compatible = "arm,gic-400";
  89                 #interrupt-cells = <3>;
  90                 interrupt-controller;
  91                 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
  92                       <0x0 0x1402000 0 0x2000>, /* GICC */
  93                       <0x0 0x1404000 0 0x2000>, /* GICH */
  94                       <0x0 0x1406000 0 0x2000>; /* GICV */
  95                 interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
  96         };
  97
  98         reboot {
  99                 compatible = "syscon-reboot";
 100                 regmap = <&dcfg>;
 101                 offset = <0xb0>;
 102                 mask = <0x02>;
 103         };
 104
 105         thermal-zones {
 106                 cpu_thermal: cpu-thermal {
 107                         polling-delay-passive = <1000>;
 108                         polling-delay = <5000>;
 109                         thermal-sensors = <&tmu 0>;
 110
 111                         trips {
 112                                 cpu_alert: cpu-alert {
 113                                         temperature = <85000>;
 114                                         hysteresis = <2000>;
 115                                         type = "passive";
 116                                 };
 117
 118                                 cpu_crit: cpu-crit {
 119                                         temperature = <95000>;
 120                                         hysteresis = <2000>;
 121                                         type = "critical";
 122                                 };
 123                         };
 124
 125                         cooling-maps {
 126                                 map0 {
 127                                         trip = <&cpu_alert>;
 128                                         cooling-device =
 129                                                 <&cpu0 THERMAL_NO_LIMIT
 130                                                 THERMAL_NO_LIMIT>;
 131                                 };
 132                         };
 133                 };
 134         };
 135
 136         soc {
 137                 compatible = "simple-bus";
 138                 #address-cells = <2>;
 139                 #size-cells = <2>;
 140                 ranges;
 141
 142                 qspi: spi@1550000 {
 143                         compatible = "fsl,ls1021a-qspi";
 144                         #address-cells = <1>;
 145                         #size-cells = <0>;
 146                         reg = <0x0 0x1550000 0x0 0x10000>,
 147                                 <0x0 0x40000000 0x0 0x10000000>;
 148                         reg-names = "QuadSPI", "QuadSPI-memory";
 149                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 150                         clock-names = "qspi_en", "qspi";
 151                         clocks = <&clockgen 4 0>, <&clockgen 4 0>;
 152                         status = "disabled";
 153                 };
 154
 155                 esdhc0: esdhc@1560000 {
 156                         compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
 157                         reg = <0x0 0x1560000 0x0 0x10000>;
 158                         interrupts = <0 62 0x4>;
 159                         clocks = <&clockgen 4 0>;
 160                         voltage-ranges = <1800 1800 3300 3300>;
 161                         sdhci,auto-cmd12;
 162                         big-endian;
 163                         bus-width = <4>;
 164                         status = "disabled";
 165                 };
 166
 167                 scfg: scfg@1570000 {
 168                         compatible = "fsl,ls1012a-scfg", "syscon";
 169                         reg = <0x0 0x1570000 0x0 0x10000>;
 170                         big-endian;
 171                 };
 172
 173                 esdhc1: esdhc@1580000 {
 174                         compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
 175                         reg = <0x0 0x1580000 0x0 0x10000>;
 176                         interrupts = <0 65 0x4>;
 177                         clocks = <&clockgen 4 0>;
 178                         voltage-ranges = <1800 1800 3300 3300>;
 179                         sdhci,auto-cmd12;
 180                         big-endian;
 181                         broken-cd;
 182                         bus-width = <4>;
 183                         status = "disabled";
 184                 };
 185
 186                 crypto: crypto@1700000 {
 187                         compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
 188                                      "fsl,sec-v4.0";
 189                         fsl,sec-era = <8>;
 190                         #address-cells = <1>;
 191                         #size-cells = <1>;
 192                         ranges = <0x0 0x00 0x1700000 0x100000>;
 193                         reg = <0x00 0x1700000 0x0 0x100000>;
 194                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 195
 196                         sec_jr0: jr@10000 {
 197                                 compatible = "fsl,sec-v5.4-job-ring",
 198                                              "fsl,sec-v5.0-job-ring",
 199                                              "fsl,sec-v4.0-job-ring";
 200                                 reg        = <0x10000 0x10000>;
 201                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 202                         };
 203
 204                         sec_jr1: jr@20000 {
 205                                 compatible = "fsl,sec-v5.4-job-ring",
 206                                              "fsl,sec-v5.0-job-ring",
 207                                              "fsl,sec-v4.0-job-ring";
 208                                 reg        = <0x20000 0x10000>;
 209                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 210                         };
 211
 212                         sec_jr2: jr@30000 {
 213                                 compatible = "fsl,sec-v5.4-job-ring",
 214                                              "fsl,sec-v5.0-job-ring",
 215                                              "fsl,sec-v4.0-job-ring";
 216                                 reg        = <0x30000 0x10000>;
 217                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 218                         };
 219
 220                         sec_jr3: jr@40000 {
 221                                 compatible = "fsl,sec-v5.4-job-ring",
 222                                              "fsl,sec-v5.0-job-ring",
 223                                              "fsl,sec-v4.0-job-ring";
 224                                 reg        = <0x40000 0x10000>;
 225                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 226                         };
 227
 228                         rtic@60000 {
 229                                 compatible = "fsl,sec-v5.4-rtic",
 230                                              "fsl,sec-v5.0-rtic",
 231                                              "fsl,sec-v4.0-rtic";
 232                                 #address-cells = <1>;
 233                                 #size-cells = <1>;
 234                                 reg = <0x60000 0x100 0x60e00 0x18>;
 235                                 ranges = <0x0 0x60100 0x500>;
 236
 237                                 rtic_a: rtic-a@0 {
 238                                         compatible = "fsl,sec-v5.4-rtic-memory",
 239                                                      "fsl,sec-v5.0-rtic-memory",
 240                                                      "fsl,sec-v4.0-rtic-memory";
 241                                         reg = <0x00 0x20 0x100 0x100>;
 242                                 };
 243
 244                                 rtic_b: rtic-b@20 {
 245                                         compatible = "fsl,sec-v5.4-rtic-memory",
 246                                                      "fsl,sec-v5.0-rtic-memory",
 247                                                      "fsl,sec-v4.0-rtic-memory";
 248                                         reg = <0x20 0x20 0x200 0x100>;
 249                                 };
 250
 251                                 rtic_c: rtic-c@40 {
 252                                         compatible = "fsl,sec-v5.4-rtic-memory",
 253                                                      "fsl,sec-v5.0-rtic-memory",
 254                                                      "fsl,sec-v4.0-rtic-memory";
 255                                         reg = <0x40 0x20 0x300 0x100>;
 256                                 };
 257
 258                                 rtic_d: rtic-d@60 {
 259                                         compatible = "fsl,sec-v5.4-rtic-memory",
 260                                                      "fsl,sec-v5.0-rtic-memory",
 261                                                      "fsl,sec-v4.0-rtic-memory";
 262                                         reg = <0x60 0x20 0x400 0x100>;
 263                                 };
 264                         };
 265                 };
 266
 267                 sec_mon: sec_mon@1e90000 {
 268                         compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
 269                                      "fsl,sec-v4.0-mon";
 270                         reg = <0x0 0x1e90000 0x0 0x10000>;
 271                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 272                                      <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 273                 };
 274
 275                 dcfg: dcfg@1ee0000 {
 276                         compatible = "fsl,ls1012a-dcfg",
 277                                      "syscon";
 278                         reg = <0x0 0x1ee0000 0x0 0x10000>;
 279                         big-endian;
 280                 };
 281
 282                 clockgen: clocking@1ee1000 {
 283                         compatible = "fsl,ls1012a-clockgen";
 284                         reg = <0x0 0x1ee1000 0x0 0x1000>;
 285                         #clock-cells = <2>;
 286                         clocks = <&sysclk &coreclk>;
 287                         clock-names = "sysclk", "coreclk";
 288                 };
 289
 290                 tmu: tmu@1f00000 {
 291                         compatible = "fsl,qoriq-tmu";
 292                         reg = <0x0 0x1f00000 0x0 0x10000>;
 293                         interrupts = <0 33 0x4>;
 294                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
 295                         fsl,tmu-calibration = <0x00000000 0x00000026
 296                                                0x00000001 0x0000002d
 297                                                0x00000002 0x00000032
 298                                                0x00000003 0x00000039
 299                                                0x00000004 0x0000003f
 300                                                0x00000005 0x00000046
 301                                                0x00000006 0x0000004d
 302                                                0x00000007 0x00000054
 303                                                0x00000008 0x0000005a
 304                                                0x00000009 0x00000061
 305                                                0x0000000a 0x0000006a
 306                                                0x0000000b 0x00000071
 307
 308                                                0x00010000 0x00000025
 309                                                0x00010001 0x0000002c
 310                                                0x00010002 0x00000035
 311                                                0x00010003 0x0000003d
 312                                                0x00010004 0x00000045
 313                                                0x00010005 0x0000004e
 314                                                0x00010006 0x00000057
 315                                                0x00010007 0x00000061
 316                                                0x00010008 0x0000006b
 317                                                0x00010009 0x00000076
 318
 319                                                0x00020000 0x00000029
 320                                                0x00020001 0x00000033
 321                                                0x00020002 0x0000003d
 322                                                0x00020003 0x00000049
 323                                                0x00020004 0x00000056
 324                                                0x00020005 0x00000061
 325                                                0x00020006 0x0000006d
 326
 327                                                0x00030000 0x00000021
 328                                                0x00030001 0x0000002a
 329                                                0x00030002 0x0000003c
 330                                                0x00030003 0x0000004e>;
 331                         big-endian;
 332                         #thermal-sensor-cells = <1>;
 333                 };
 334
 335                 i2c0: i2c@2180000 {
 336                         compatible = "fsl,vf610-i2c";
 337                         #address-cells = <1>;
 338                         #size-cells = <0>;
 339                         reg = <0x0 0x2180000 0x0 0x10000>;
 340                         interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 341                         clocks = <&clockgen 4 3>;
 342                         status = "disabled";
 343                 };
 344
 345                 i2c1: i2c@2190000 {
 346                         compatible = "fsl,vf610-i2c";
 347                         #address-cells = <1>;
 348                         #size-cells = <0>;
 349                         reg = <0x0 0x2190000 0x0 0x10000>;
 350                         interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 351                         clocks = <&clockgen 4 3>;
 352                         status = "disabled";
 353                 };
 354
 355                 dspi: spi@2100000 {
 356                         compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi";
 357                         #address-cells = <1>;
 358                         #size-cells = <0>;
 359                         reg = <0x0 0x2100000 0x0 0x10000>;
 360                         interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
 361                         clock-names = "dspi";
 362                         clocks = <&clockgen 4 0>;
 363                         spi-num-chipselects = <5>;
 364                         big-endian;
 365                         status = "disabled";
 366                 };
 367
 368                 duart0: serial@21c0500 {
 369                         compatible = "fsl,ns16550", "ns16550a";
 370                         reg = <0x00 0x21c0500 0x0 0x100>;
 371                         interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
 372                         clocks = <&clockgen 4 0>;
 373                         status = "disabled";
 374                 };
 375
 376                 duart1: serial@21c0600 {
 377                         compatible = "fsl,ns16550", "ns16550a";
 378                         reg = <0x00 0x21c0600 0x0 0x100>;
 379                         interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
 380                         clocks = <&clockgen 4 0>;
 381                         status = "disabled";
 382                 };
 383
 384                 gpio0: gpio@2300000 {
 385                         compatible = "fsl,qoriq-gpio";
 386                         reg = <0x0 0x2300000 0x0 0x10000>;
 387                         interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
 388                         gpio-controller;
 389                         #gpio-cells = <2>;
 390                         interrupt-controller;
 391                         #interrupt-cells = <2>;
 392                 };
 393
 394                 gpio1: gpio@2310000 {
 395                         compatible = "fsl,qoriq-gpio";
 396                         reg = <0x0 0x2310000 0x0 0x10000>;
 397                         interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
 398                         gpio-controller;
 399                         #gpio-cells = <2>;
 400                         interrupt-controller;
 401                         #interrupt-cells = <2>;
 402                 };
 403
 404                 wdog0: wdog@2ad0000 {
 405                         compatible = "fsl,ls1012a-wdt",
 406                                      "fsl,imx21-wdt";
 407                         reg = <0x0 0x2ad0000 0x0 0x10000>;
 408                         interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 409                         clocks = <&clockgen 4 0>;
 410                         big-endian;
 411                 };
 412
 413                 sai1: sai@2b50000 {
 414                         #sound-dai-cells = <0>;
 415                         compatible = "fsl,vf610-sai";
 416                         reg = <0x0 0x2b50000 0x0 0x10000>;
 417                         interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 418                         clocks = <&clockgen 4 3>, <&clockgen 4 3>,
 419                                  <&clockgen 4 3>, <&clockgen 4 3>;
 420                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 421                         dma-names = "tx", "rx";
 422                         dmas = <&edma0 1 47>,
 423                                <&edma0 1 46>;
 424                         status = "disabled";
 425                 };
 426
 427                 sai2: sai@2b60000 {
 428                         #sound-dai-cells = <0>;
 429                         compatible = "fsl,vf610-sai";
 430                         reg = <0x0 0x2b60000 0x0 0x10000>;
 431                         interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 432                         clocks = <&clockgen 4 3>, <&clockgen 4 3>,
 433                                  <&clockgen 4 3>, <&clockgen 4 3>;
 434                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 435                         dma-names = "tx", "rx";
 436                         dmas = <&edma0 1 45>,
 437                                <&edma0 1 44>;
 438                         status = "disabled";
 439                 };
 440
 441                 edma0: edma@2c00000 {
 442                         #dma-cells = <2>;
 443                         compatible = "fsl,vf610-edma";
 444                         reg = <0x0 0x2c00000 0x0 0x10000>,
 445                               <0x0 0x2c10000 0x0 0x10000>,
 446                               <0x0 0x2c20000 0x0 0x10000>;
 447                         interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
 448                                      <0 103 IRQ_TYPE_LEVEL_HIGH>;
 449                         interrupt-names = "edma-tx", "edma-err";
 450                         dma-channels = <32>;
 451                         big-endian;
 452                         clock-names = "dmamux0", "dmamux1";
 453                         clocks = <&clockgen 4 3>,
 454                                  <&clockgen 4 3>;
 455                 };
 456
 457                 usb0: usb3@2f00000 {
 458                         compatible = "snps,dwc3";
 459                         reg = <0x0 0x2f00000 0x0 0x10000>;
 460                         interrupts = <0 60 0x4>;
 461                         dr_mode = "host";
 462                         snps,quirk-frame-length-adjustment = <0x20>;
 463                         snps,dis_rxdet_inp3_quirk;
 464                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 465                 };
 466
 467                 sata: sata@3200000 {
 468                         compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
 469                         reg = <0x0 0x3200000 0x0 0x10000>,
 470                                 <0x0 0x20140520 0x0 0x4>;
 471                         reg-names = "ahci", "sata-ecc";
 472                         interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 473                         clocks = <&clockgen 4 0>;
 474                         dma-coherent;
 475                         status = "disabled";
 476                 };
 477
 478                 usb1: usb2@8600000 {
 479                         compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 480                         reg = <0x0 0x8600000 0x0 0x1000>;
 481                         interrupts = <0 139 0x4>;
 482                         dr_mode = "host";
 483                         phy_type = "ulpi";
 484                 };
 485
 486                 msi: msi-controller1@1572000 {
 487                         compatible = "fsl,ls1012a-msi";
 488                         reg = <0x0 0x1572000 0x0 0x8>;
 489                         msi-controller;
 490                         interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
 491                 };
 492
 493                 pcie1: pcie@3400000 {
 494                         compatible = "fsl,ls1012a-pcie";
 495                         reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 496                                0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 497                         reg-names = "regs", "config";
 498                         interrupts = <0 118 0x4>, /* controller interrupt */
 499                                      <0 117 0x4>; /* PME interrupt */
 500                         interrupt-names = "aer", "pme";
 501                         #address-cells = <3>;
 502                         #size-cells = <2>;
 503                         device_type = "pci";
 504                         num-viewport = <2>;
 505                         bus-range = <0x0 0xff>;
 506                         ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
 507                                   0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 508                         msi-parent = <&msi>;
 509                         #interrupt-cells = <1>;
 510                         interrupt-map-mask = <0 0 0 7>;
 511                         interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
 512                                         <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
 513                                         <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
 514                                         <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
 515                         status = "disabled";
 516                 };
 517
 518                 rcpm: power-controller@1ee2140 {
 519                         compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1+";
 520                         reg = <0x0 0x1ee2140 0x0 0x4>;
 521                         #fsl,rcpm-wakeup-cells = <1>;
 522                 };
 523
 524                 ftm_alarm0: timer@29d0000 {
 525                         compatible = "fsl,ls1012a-ftm-alarm";
 526                         reg = <0x0 0x29d0000 0x0 0x10000>;
 527                         fsl,rcpm-wakeup = <&rcpm 0x20000>;
 528                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 529                         big-endian;
 530                 };
 531         };
 532
 533         firmware {
 534                 optee {
 535                         compatible = "linaro,optee-tz";
 536                         method = "smc";
 537                 };
 538         };
 539 };