1 // SPDX-License-Identifier: GPL-2.0
5 * Versatile Express (VE) system model
6 * Motherboard component
11 v2m_clk24mhz: clk24mhz {
12 compatible = "fixed-clock";
14 clock-frequency = <24000000>;
15 clock-output-names = "v2m:clk24mhz";
18 v2m_refclk1mhz: refclk1mhz {
19 compatible = "fixed-clock";
21 clock-frequency = <1000000>;
22 clock-output-names = "v2m:refclk1mhz";
25 v2m_refclk32khz: refclk32khz {
26 compatible = "fixed-clock";
28 clock-frequency = <32768>;
29 clock-output-names = "v2m:refclk32khz";
32 v2m_fixed_3v3: v2m-3v3 {
33 compatible = "regulator-fixed";
34 regulator-name = "3V3";
35 regulator-min-microvolt = <3300000>;
36 regulator-max-microvolt = <3300000>;
41 compatible = "arm,vexpress,config-bus";
42 arm,vexpress,config-bridge = <&v2m_sysreg>;
44 v2m_oscclk1: oscclk1 {
46 compatible = "arm,vexpress-osc";
47 arm,vexpress-sysreg,func = <1 1>;
48 freq-range = <23750000 63500000>;
50 clock-output-names = "v2m:oscclk1";
54 compatible = "arm,vexpress-reset";
55 arm,vexpress-sysreg,func = <5 0>;
59 compatible = "arm,vexpress-muxfpga";
60 arm,vexpress-sysreg,func = <7 0>;
64 compatible = "arm,vexpress-shutdown";
65 arm,vexpress-sysreg,func = <8 0>;
69 compatible = "arm,vexpress-reboot";
70 arm,vexpress-sysreg,func = <9 0>;
74 compatible = "arm,vexpress-dvimode";
75 arm,vexpress-sysreg,func = <11 0>;
81 arm,v2m-memory-map = "rs1";
82 compatible = "arm,vexpress,v2m-p1", "simple-bus";
83 #address-cells = <2>; /* SMB chipselect number and offset */
85 #interrupt-cells = <1>;
89 compatible = "arm,vexpress-flash", "cfi-flash";
90 reg = <0 0x00000000 0x04000000>,
91 <4 0x00000000 0x04000000>;
96 compatible = "smsc,lan91c111";
97 reg = <2 0x02000000 0x10000>;
101 iofpga-bus@300000000 {
102 compatible = "simple-bus";
103 #address-cells = <1>;
105 ranges = <0 3 0 0x200000>;
107 v2m_sysreg: sysreg@10000 {
108 compatible = "arm,vexpress-sysreg";
109 reg = <0x010000 0x1000>;
114 v2m_sysctl: sysctl@20000 {
115 compatible = "arm,sp810", "arm,primecell";
116 reg = <0x020000 0x1000>;
117 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
118 clock-names = "refclk", "timclk", "apb_pclk";
120 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
121 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
122 assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
126 compatible = "arm,pl041", "arm,primecell";
127 reg = <0x040000 0x1000>;
129 clocks = <&v2m_clk24mhz>;
130 clock-names = "apb_pclk";
134 compatible = "arm,pl180", "arm,primecell";
135 reg = <0x050000 0x1000>;
136 interrupts = <9>, <10>;
137 cd-gpios = <&v2m_sysreg 0 0>;
138 wp-gpios = <&v2m_sysreg 1 0>;
139 max-frequency = <12000000>;
140 vmmc-supply = <&v2m_fixed_3v3>;
141 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
142 clock-names = "mclk", "apb_pclk";
146 compatible = "arm,pl050", "arm,primecell";
147 reg = <0x060000 0x1000>;
149 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
150 clock-names = "KMIREFCLK", "apb_pclk";
154 compatible = "arm,pl050", "arm,primecell";
155 reg = <0x070000 0x1000>;
157 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
158 clock-names = "KMIREFCLK", "apb_pclk";
161 v2m_serial0: serial@90000 {
162 compatible = "arm,pl011", "arm,primecell";
163 reg = <0x090000 0x1000>;
165 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
166 clock-names = "uartclk", "apb_pclk";
169 v2m_serial1: serial@a0000 {
170 compatible = "arm,pl011", "arm,primecell";
171 reg = <0x0a0000 0x1000>;
173 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
174 clock-names = "uartclk", "apb_pclk";
177 v2m_serial2: serial@b0000 {
178 compatible = "arm,pl011", "arm,primecell";
179 reg = <0x0b0000 0x1000>;
181 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
182 clock-names = "uartclk", "apb_pclk";
185 v2m_serial3: serial@c0000 {
186 compatible = "arm,pl011", "arm,primecell";
187 reg = <0x0c0000 0x1000>;
189 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
190 clock-names = "uartclk", "apb_pclk";
194 compatible = "arm,sp805", "arm,primecell";
195 reg = <0x0f0000 0x1000>;
197 clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
198 clock-names = "wdog_clk", "apb_pclk";
201 v2m_timer01: timer@110000 {
202 compatible = "arm,sp804", "arm,primecell";
203 reg = <0x110000 0x1000>;
205 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
206 clock-names = "timclken1", "timclken2", "apb_pclk";
209 v2m_timer23: timer@120000 {
210 compatible = "arm,sp804", "arm,primecell";
211 reg = <0x120000 0x1000>;
213 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
214 clock-names = "timclken1", "timclken2", "apb_pclk";
217 virtio-block@130000 {
218 compatible = "virtio,mmio";
219 reg = <0x130000 0x200>;
224 compatible = "arm,pl031", "arm,primecell";
225 reg = <0x170000 0x1000>;
227 clocks = <&v2m_clk24mhz>;
228 clock-names = "apb_pclk";
232 compatible = "arm,pl111", "arm,primecell";
233 reg = <0x1f0000 0x1000>;
234 interrupt-names = "combined";
236 clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
237 clock-names = "clcdclk", "apb_pclk";
238 memory-region = <&vram>;
241 clcd_pads: endpoint {
242 remote-endpoint = <&panel_in>;
243 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;