1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi"
7 * Devices shared by all Juno boards
10 memtimer: timer@2a810000 {
11 compatible = "arm,armv7-timer-mem";
12 reg = <0x0 0x2a810000 0x0 0x10000>;
13 clock-frequency = <50000000>;
16 ranges = <0 0x0 0x2a820000 0x20000>;
20 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
21 reg = <0x10000 0x10000>;
25 mailbox: mhu@2b1f0000 {
26 compatible = "arm,mhu", "arm,primecell";
27 reg = <0x0 0x2b1f0000 0x0 0x1000>;
28 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
29 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
30 interrupt-names = "mhu_lpri_rx",
33 clocks = <&soc_refclk100mhz>;
34 clock-names = "apb_pclk";
37 smmu_gpu: iommu@2b400000 {
38 compatible = "arm,mmu-400", "arm,smmu-v1";
39 reg = <0x0 0x2b400000 0x0 0x10000>;
40 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
41 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
43 #global-interrupts = <1>;
44 power-domains = <&scpi_devpd 1>;
49 smmu_pcie: iommu@2b500000 {
50 compatible = "arm,mmu-401", "arm,smmu-v1";
51 reg = <0x0 0x2b500000 0x0 0x10000>;
52 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
53 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
55 #global-interrupts = <1>;
60 smmu_etr: iommu@2b600000 {
61 compatible = "arm,mmu-401", "arm,smmu-v1";
62 reg = <0x0 0x2b600000 0x0 0x10000>;
63 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
66 #global-interrupts = <1>;
68 power-domains = <&scpi_devpd 0>;
71 gic: interrupt-controller@2c010000 {
72 compatible = "arm,gic-400", "arm,cortex-a15-gic";
73 reg = <0x0 0x2c010000 0 0x1000>,
74 <0x0 0x2c02f000 0 0x2000>,
75 <0x0 0x2c04f000 0 0x2000>,
76 <0x0 0x2c06f000 0 0x2000>;
78 #interrupt-cells = <3>;
81 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
82 ranges = <0 0 0x2c1c0000 0x40000>;
85 compatible = "arm,gic-v2m-frame";
91 compatible = "arm,gic-v2m-frame";
93 reg = <0x10000 0x10000>;
97 compatible = "arm,gic-v2m-frame";
99 reg = <0x20000 0x10000>;
103 compatible = "arm,gic-v2m-frame";
105 reg = <0x30000 0x10000>;
110 compatible = "arm,armv8-timer";
111 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
112 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
113 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
114 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
118 * Juno TRMs specify the size for these coresight components as 64K.
119 * The actual size is just 4K though 64K is reserved. Access to the
120 * unmapped reserved region results in a DECERR response.
122 etf@20010000 { /* etf0 */
123 compatible = "arm,coresight-tmc", "arm,primecell";
124 reg = <0 0x20010000 0 0x1000>;
126 clocks = <&soc_smc50mhz>;
127 clock-names = "apb_pclk";
128 power-domains = <&scpi_devpd 0>;
132 etf0_in_port: endpoint {
133 remote-endpoint = <&main_funnel_out_port>;
140 etf0_out_port: endpoint {
147 compatible = "arm,coresight-tpiu", "arm,primecell";
148 reg = <0 0x20030000 0 0x1000>;
150 clocks = <&soc_smc50mhz>;
151 clock-names = "apb_pclk";
152 power-domains = <&scpi_devpd 0>;
155 tpiu_in_port: endpoint {
156 remote-endpoint = <&replicator_out_port0>;
162 /* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/
163 main_funnel: funnel@20040000 {
164 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
165 reg = <0 0x20040000 0 0x1000>;
167 clocks = <&soc_smc50mhz>;
168 clock-names = "apb_pclk";
169 power-domains = <&scpi_devpd 0>;
173 main_funnel_out_port: endpoint {
174 remote-endpoint = <&etf0_in_port>;
179 main_funnel_in_ports: in-ports {
180 #address-cells = <1>;
185 main_funnel_in_port0: endpoint {
186 remote-endpoint = <&cluster0_funnel_out_port>;
192 main_funnel_in_port1: endpoint {
193 remote-endpoint = <&cluster1_funnel_out_port>;
200 compatible = "arm,coresight-tmc", "arm,primecell";
201 reg = <0 0x20070000 0 0x1000>;
202 iommus = <&smmu_etr 0>;
204 clocks = <&soc_smc50mhz>;
205 clock-names = "apb_pclk";
206 power-domains = <&scpi_devpd 0>;
210 etr_in_port: endpoint {
211 remote-endpoint = <&replicator_out_port1>;
218 compatible = "arm,coresight-stm", "arm,primecell";
219 reg = <0 0x20100000 0 0x1000>,
220 <0 0x28000000 0 0x1000000>;
221 reg-names = "stm-base", "stm-stimulus-base";
223 clocks = <&soc_smc50mhz>;
224 clock-names = "apb_pclk";
225 power-domains = <&scpi_devpd 0>;
228 stm_out_port: endpoint {
234 replicator@20120000 {
235 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
236 reg = <0 0x20120000 0 0x1000>;
238 clocks = <&soc_smc50mhz>;
239 clock-names = "apb_pclk";
240 power-domains = <&scpi_devpd 0>;
243 #address-cells = <1>;
246 /* replicator output ports */
249 replicator_out_port0: endpoint {
250 remote-endpoint = <&tpiu_in_port>;
256 replicator_out_port1: endpoint {
257 remote-endpoint = <&etr_in_port>;
263 replicator_in_port0: endpoint {
269 cpu_debug0: cpu-debug@22010000 {
270 compatible = "arm,coresight-cpu-debug", "arm,primecell";
271 reg = <0x0 0x22010000 0x0 0x1000>;
273 clocks = <&soc_smc50mhz>;
274 clock-names = "apb_pclk";
275 power-domains = <&scpi_devpd 0>;
279 compatible = "arm,coresight-etm4x", "arm,primecell";
280 reg = <0 0x22040000 0 0x1000>;
282 clocks = <&soc_smc50mhz>;
283 clock-names = "apb_pclk";
284 power-domains = <&scpi_devpd 0>;
287 cluster0_etm0_out_port: endpoint {
288 remote-endpoint = <&cluster0_funnel_in_port0>;
294 funnel@220c0000 { /* cluster0 funnel */
295 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
296 reg = <0 0x220c0000 0 0x1000>;
298 clocks = <&soc_smc50mhz>;
299 clock-names = "apb_pclk";
300 power-domains = <&scpi_devpd 0>;
303 cluster0_funnel_out_port: endpoint {
304 remote-endpoint = <&main_funnel_in_port0>;
310 #address-cells = <1>;
315 cluster0_funnel_in_port0: endpoint {
316 remote-endpoint = <&cluster0_etm0_out_port>;
322 cluster0_funnel_in_port1: endpoint {
323 remote-endpoint = <&cluster0_etm1_out_port>;
329 cpu_debug1: cpu-debug@22110000 {
330 compatible = "arm,coresight-cpu-debug", "arm,primecell";
331 reg = <0x0 0x22110000 0x0 0x1000>;
333 clocks = <&soc_smc50mhz>;
334 clock-names = "apb_pclk";
335 power-domains = <&scpi_devpd 0>;
339 compatible = "arm,coresight-etm4x", "arm,primecell";
340 reg = <0 0x22140000 0 0x1000>;
342 clocks = <&soc_smc50mhz>;
343 clock-names = "apb_pclk";
344 power-domains = <&scpi_devpd 0>;
347 cluster0_etm1_out_port: endpoint {
348 remote-endpoint = <&cluster0_funnel_in_port1>;
354 cpu_debug2: cpu-debug@23010000 {
355 compatible = "arm,coresight-cpu-debug", "arm,primecell";
356 reg = <0x0 0x23010000 0x0 0x1000>;
358 clocks = <&soc_smc50mhz>;
359 clock-names = "apb_pclk";
360 power-domains = <&scpi_devpd 0>;
364 compatible = "arm,coresight-etm4x", "arm,primecell";
365 reg = <0 0x23040000 0 0x1000>;
367 clocks = <&soc_smc50mhz>;
368 clock-names = "apb_pclk";
369 power-domains = <&scpi_devpd 0>;
372 cluster1_etm0_out_port: endpoint {
373 remote-endpoint = <&cluster1_funnel_in_port0>;
379 funnel@230c0000 { /* cluster1 funnel */
380 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
381 reg = <0 0x230c0000 0 0x1000>;
383 clocks = <&soc_smc50mhz>;
384 clock-names = "apb_pclk";
385 power-domains = <&scpi_devpd 0>;
388 cluster1_funnel_out_port: endpoint {
389 remote-endpoint = <&main_funnel_in_port1>;
395 #address-cells = <1>;
400 cluster1_funnel_in_port0: endpoint {
401 remote-endpoint = <&cluster1_etm0_out_port>;
407 cluster1_funnel_in_port1: endpoint {
408 remote-endpoint = <&cluster1_etm1_out_port>;
413 cluster1_funnel_in_port2: endpoint {
414 remote-endpoint = <&cluster1_etm2_out_port>;
419 cluster1_funnel_in_port3: endpoint {
420 remote-endpoint = <&cluster1_etm3_out_port>;
426 cpu_debug3: cpu-debug@23110000 {
427 compatible = "arm,coresight-cpu-debug", "arm,primecell";
428 reg = <0x0 0x23110000 0x0 0x1000>;
430 clocks = <&soc_smc50mhz>;
431 clock-names = "apb_pclk";
432 power-domains = <&scpi_devpd 0>;
436 compatible = "arm,coresight-etm4x", "arm,primecell";
437 reg = <0 0x23140000 0 0x1000>;
439 clocks = <&soc_smc50mhz>;
440 clock-names = "apb_pclk";
441 power-domains = <&scpi_devpd 0>;
444 cluster1_etm1_out_port: endpoint {
445 remote-endpoint = <&cluster1_funnel_in_port1>;
451 cpu_debug4: cpu-debug@23210000 {
452 compatible = "arm,coresight-cpu-debug", "arm,primecell";
453 reg = <0x0 0x23210000 0x0 0x1000>;
455 clocks = <&soc_smc50mhz>;
456 clock-names = "apb_pclk";
457 power-domains = <&scpi_devpd 0>;
461 compatible = "arm,coresight-etm4x", "arm,primecell";
462 reg = <0 0x23240000 0 0x1000>;
464 clocks = <&soc_smc50mhz>;
465 clock-names = "apb_pclk";
466 power-domains = <&scpi_devpd 0>;
469 cluster1_etm2_out_port: endpoint {
470 remote-endpoint = <&cluster1_funnel_in_port2>;
476 cpu_debug5: cpu-debug@23310000 {
477 compatible = "arm,coresight-cpu-debug", "arm,primecell";
478 reg = <0x0 0x23310000 0x0 0x1000>;
480 clocks = <&soc_smc50mhz>;
481 clock-names = "apb_pclk";
482 power-domains = <&scpi_devpd 0>;
486 compatible = "arm,coresight-etm4x", "arm,primecell";
487 reg = <0 0x23340000 0 0x1000>;
489 clocks = <&soc_smc50mhz>;
490 clock-names = "apb_pclk";
491 power-domains = <&scpi_devpd 0>;
494 cluster1_etm3_out_port: endpoint {
495 remote-endpoint = <&cluster1_funnel_in_port3>;
502 compatible = "arm,juno-mali", "arm,mali-t624";
503 reg = <0 0x2d000000 0 0x10000>;
504 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
507 interrupt-names = "job", "mmu", "gpu";
508 clocks = <&scpi_dvfs 2>;
509 power-domains = <&scpi_devpd 1>;
511 /* The SMMU is only really of interest to bare-metal hypervisors */
512 /* iommus = <&smmu_gpu 0>; */
516 sram: sram@2e000000 {
517 compatible = "arm,juno-sram-ns", "mmio-sram";
518 reg = <0x0 0x2e000000 0x0 0x8000>;
520 #address-cells = <1>;
522 ranges = <0 0x0 0x2e000000 0x8000>;
524 cpu_scp_lpri: scp-sram@0 {
525 compatible = "arm,juno-scp-shmem";
529 cpu_scp_hpri: scp-sram@200 {
530 compatible = "arm,juno-scp-shmem";
535 pcie_ctlr: pcie@40000000 {
536 compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
538 reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */
540 linux,pci-domain = <0>;
541 #address-cells = <3>;
544 ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>,
545 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
546 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
547 /* Standard AXI Translation entries as programmed by EDK2 */
548 dma-ranges = <0x02000000 0x0 0x2c1c0000 0x0 0x2c1c0000 0x0 0x00040000>,
549 <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x80000000>,
550 <0x43000000 0x8 0x00000000 0x8 0x00000000 0x2 0x00000000>;
551 #interrupt-cells = <1>;
552 interrupt-map-mask = <0 0 0 7>;
553 interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
554 <0 0 0 2 &gic 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
555 <0 0 0 3 &gic 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
556 <0 0 0 4 &gic 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
557 msi-parent = <&v2m_0>;
559 iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
560 iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
564 compatible = "arm,scpi";
565 mboxes = <&mailbox 1>;
566 shmem = <&cpu_scp_hpri>;
569 compatible = "arm,scpi-clocks";
571 scpi_dvfs: scpi-dvfs {
572 compatible = "arm,scpi-dvfs-clocks";
574 clock-indices = <0>, <1>, <2>;
575 clock-output-names = "atlclk", "aplclk","gpuclk";
578 compatible = "arm,scpi-variable-clocks";
581 clock-output-names = "pxlclk";
585 scpi_devpd: scpi-power-domains {
586 compatible = "arm,scpi-power-domains";
588 #power-domain-cells = <1>;
591 scpi_sensors0: sensors {
592 compatible = "arm,scpi-sensors";
593 #thermal-sensor-cells = <1>;
599 polling-delay = <1000>;
600 polling-delay-passive = <100>;
601 thermal-sensors = <&scpi_sensors0 0>;
605 polling-delay = <1000>;
606 polling-delay-passive = <100>;
607 thermal-sensors = <&scpi_sensors0 3>;
610 big_cluster_thermal_zone: big-cluster {
611 polling-delay = <1000>;
612 polling-delay-passive = <100>;
613 thermal-sensors = <&scpi_sensors0 21>;
617 little_cluster_thermal_zone: little-cluster {
618 polling-delay = <1000>;
619 polling-delay-passive = <100>;
620 thermal-sensors = <&scpi_sensors0 22>;
624 gpu0_thermal_zone: gpu0 {
625 polling-delay = <1000>;
626 polling-delay-passive = <100>;
627 thermal-sensors = <&scpi_sensors0 23>;
631 gpu1_thermal_zone: gpu1 {
632 polling-delay = <1000>;
633 polling-delay-passive = <100>;
634 thermal-sensors = <&scpi_sensors0 24>;
639 smmu_dma: iommu@7fb00000 {
640 compatible = "arm,mmu-401", "arm,smmu-v1";
641 reg = <0x0 0x7fb00000 0x0 0x10000>;
642 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
643 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
645 #global-interrupts = <1>;
650 smmu_hdlcd1: iommu@7fb10000 {
651 compatible = "arm,mmu-401", "arm,smmu-v1";
652 reg = <0x0 0x7fb10000 0x0 0x10000>;
653 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
654 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
656 #global-interrupts = <1>;
659 smmu_hdlcd0: iommu@7fb20000 {
660 compatible = "arm,mmu-401", "arm,smmu-v1";
661 reg = <0x0 0x7fb20000 0x0 0x10000>;
662 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
663 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
665 #global-interrupts = <1>;
668 smmu_usb: iommu@7fb30000 {
669 compatible = "arm,mmu-401", "arm,smmu-v1";
670 reg = <0x0 0x7fb30000 0x0 0x10000>;
671 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
672 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
674 #global-interrupts = <1>;
679 compatible = "arm,pl330", "arm,primecell";
680 reg = <0x0 0x7ff00000 0 0x1000>;
683 #dma-requests = <32>;
684 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
685 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
686 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
687 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
688 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
689 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
690 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
691 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
692 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
693 iommus = <&smmu_dma 0>,
702 clocks = <&soc_faxiclk>;
703 clock-names = "apb_pclk";
707 compatible = "arm,hdlcd";
708 reg = <0 0x7ff50000 0 0x1000>;
709 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
710 iommus = <&smmu_hdlcd1 0>;
711 clocks = <&scpi_clk 3>;
712 clock-names = "pxlclk";
715 hdlcd1_output: endpoint {
716 remote-endpoint = <&tda998x_1_input>;
722 compatible = "arm,hdlcd";
723 reg = <0 0x7ff60000 0 0x1000>;
724 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
725 iommus = <&smmu_hdlcd0 0>;
726 clocks = <&scpi_clk 3>;
727 clock-names = "pxlclk";
730 hdlcd0_output: endpoint {
731 remote-endpoint = <&tda998x_0_input>;
736 soc_uart0: serial@7ff80000 {
737 compatible = "arm,pl011", "arm,primecell";
738 reg = <0x0 0x7ff80000 0x0 0x1000>;
739 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
740 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
741 clock-names = "uartclk", "apb_pclk";
745 compatible = "snps,designware-i2c";
746 reg = <0x0 0x7ffa0000 0x0 0x1000>;
747 #address-cells = <1>;
749 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
750 clock-frequency = <400000>;
751 i2c-sda-hold-time-ns = <500>;
752 clocks = <&soc_smc50mhz>;
754 hdmi-transmitter@70 {
755 compatible = "nxp,tda998x";
758 tda998x_0_input: endpoint {
759 remote-endpoint = <&hdlcd0_output>;
764 hdmi-transmitter@71 {
765 compatible = "nxp,tda998x";
768 tda998x_1_input: endpoint {
769 remote-endpoint = <&hdlcd1_output>;
776 compatible = "generic-ohci";
777 reg = <0x0 0x7ffb0000 0x0 0x10000>;
778 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
779 iommus = <&smmu_usb 0>;
780 clocks = <&soc_usb48mhz>;
784 compatible = "generic-ehci";
785 reg = <0x0 0x7ffc0000 0x0 0x10000>;
786 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
787 iommus = <&smmu_usb 0>;
788 clocks = <&soc_usb48mhz>;
791 memory-controller@7ffd0000 {
792 compatible = "arm,pl354", "arm,primecell";
793 reg = <0 0x7ffd0000 0 0x1000>;
794 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
795 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
796 clocks = <&soc_smc50mhz>;
797 clock-names = "apb_pclk";
801 device_type = "memory";
802 /* last 16MB of the first memory area is reserved for secure world use by firmware */
803 reg = <0x00000000 0x80000000 0x0 0x7f000000>,
804 <0x00000008 0x80000000 0x1 0x80000000>;
808 compatible = "simple-bus";
809 #address-cells = <2>;
811 ranges = <0 0 0 0x08000000 0x04000000>,
812 <1 0 0 0x14000000 0x04000000>,
813 <2 0 0 0x18000000 0x04000000>,
814 <3 0 0 0x1c000000 0x04000000>,
815 <4 0 0 0x0c000000 0x04000000>,
816 <5 0 0 0x10000000 0x04000000>;
818 #interrupt-cells = <1>;
819 interrupt-map-mask = <0 0 15>;
820 interrupt-map = <0 0 0 &gic 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
821 <0 0 1 &gic 0 GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
822 <0 0 2 &gic 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
823 <0 0 3 &gic 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
824 <0 0 4 &gic 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
825 <0 0 5 &gic 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
826 <0 0 6 &gic 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
827 <0 0 7 &gic 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
828 <0 0 8 &gic 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
829 <0 0 9 &gic 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
830 <0 0 10 &gic 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
831 <0 0 11 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
832 <0 0 12 &gic 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
835 site2: tlx-bus@60000000 {
836 compatible = "simple-bus";
837 #address-cells = <1>;
839 ranges = <0 0 0x60000000 0x10000000>;
840 #interrupt-cells = <1>;
841 interrupt-map-mask = <0 0>;
842 interrupt-map = <0 0 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;