arch/arm64/boot/dts/arm/foundation-v8.dtsi

   1 /*
   2  * ARM Ltd.
   3  *
   4  * ARMv8 Foundation model DTS
   5  */
   6
   7 /dts-v1/;
   8
   9 /memreserve/ 0x80000000 0x00010000;
  10
  11 / {
  12         model = "Foundation-v8A";
  13         compatible = "arm,foundation-aarch64", "arm,vexpress";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         chosen { };
  19
  20         aliases {
  21                 serial0 = &v2m_serial0;
  22                 serial1 = &v2m_serial1;
  23                 serial2 = &v2m_serial2;
  24                 serial3 = &v2m_serial3;
  25         };
  26
  27         cpus {
  28                 #address-cells = <2>;
  29                 #size-cells = <0>;
  30
  31                 cpu0: cpu@0 {
  32                         device_type = "cpu";
  33                         compatible = "arm,armv8";
  34                         reg = <0x0 0x0>;
  35                         next-level-cache = <&L2_0>;
  36                 };
  37                 cpu1: cpu@1 {
  38                         device_type = "cpu";
  39                         compatible = "arm,armv8";
  40                         reg = <0x0 0x1>;
  41                         next-level-cache = <&L2_0>;
  42                 };
  43                 cpu2: cpu@2 {
  44                         device_type = "cpu";
  45                         compatible = "arm,armv8";
  46                         reg = <0x0 0x2>;
  47                         next-level-cache = <&L2_0>;
  48                 };
  49                 cpu3: cpu@3 {
  50                         device_type = "cpu";
  51                         compatible = "arm,armv8";
  52                         reg = <0x0 0x3>;
  53                         next-level-cache = <&L2_0>;
  54                 };
  55
  56                 L2_0: l2-cache0 {
  57                         compatible = "cache";
  58                 };
  59         };
  60
  61         memory@80000000 {
  62                 device_type = "memory";
  63                 reg = <0x00000000 0x80000000 0 0x80000000>,
  64                       <0x00000008 0x80000000 0 0x80000000>;
  65         };
  66
  67         timer {
  68                 compatible = "arm,armv8-timer";
  69                 interrupts = <1 13 0xf08>,
  70                              <1 14 0xf08>,
  71                              <1 11 0xf08>,
  72                              <1 10 0xf08>;
  73                 clock-frequency = <100000000>;
  74         };
  75
  76         pmu {
  77                 compatible = "arm,armv8-pmuv3";
  78                 interrupts = <0 60 4>,
  79                              <0 61 4>,
  80                              <0 62 4>,
  81                              <0 63 4>;
  82         };
  83
  84         watchdog@2a440000 {
  85                 compatible = "arm,sbsa-gwdt";
  86                 reg = <0x0 0x2a440000 0 0x1000>,
  87                         <0x0 0x2a450000 0 0x1000>;
  88                 interrupts = <0 27 4>;
  89                 timeout-sec = <30>;
  90         };
  91
  92         smb@8000000 {
  93                 compatible = "arm,vexpress,v2m-p1", "simple-bus";
  94                 arm,v2m-memory-map = "rs1";
  95                 #address-cells = <2>; /* SMB chipselect number and offset */
  96                 #size-cells = <1>;
  97
  98                 ranges = <0 0 0 0x08000000 0x04000000>,
  99                          <1 0 0 0x14000000 0x04000000>,
 100                          <2 0 0 0x18000000 0x04000000>,
 101                          <3 0 0 0x1c000000 0x04000000>,
 102                          <4 0 0 0x0c000000 0x04000000>,
 103                          <5 0 0 0x10000000 0x04000000>;
 104
 105                 #interrupt-cells = <1>;
 106                 interrupt-map-mask = <0 0 63>;
 107                 interrupt-map = <0 0  0 &gic 0 0 0  0 4>,
 108                                 <0 0  1 &gic 0 0 0  1 4>,
 109                                 <0 0  2 &gic 0 0 0  2 4>,
 110                                 <0 0  3 &gic 0 0 0  3 4>,
 111                                 <0 0  4 &gic 0 0 0  4 4>,
 112                                 <0 0  5 &gic 0 0 0  5 4>,
 113                                 <0 0  6 &gic 0 0 0  6 4>,
 114                                 <0 0  7 &gic 0 0 0  7 4>,
 115                                 <0 0  8 &gic 0 0 0  8 4>,
 116                                 <0 0  9 &gic 0 0 0  9 4>,
 117                                 <0 0 10 &gic 0 0 0 10 4>,
 118                                 <0 0 11 &gic 0 0 0 11 4>,
 119                                 <0 0 12 &gic 0 0 0 12 4>,
 120                                 <0 0 13 &gic 0 0 0 13 4>,
 121                                 <0 0 14 &gic 0 0 0 14 4>,
 122                                 <0 0 15 &gic 0 0 0 15 4>,
 123                                 <0 0 16 &gic 0 0 0 16 4>,
 124                                 <0 0 17 &gic 0 0 0 17 4>,
 125                                 <0 0 18 &gic 0 0 0 18 4>,
 126                                 <0 0 19 &gic 0 0 0 19 4>,
 127                                 <0 0 20 &gic 0 0 0 20 4>,
 128                                 <0 0 21 &gic 0 0 0 21 4>,
 129                                 <0 0 22 &gic 0 0 0 22 4>,
 130                                 <0 0 23 &gic 0 0 0 23 4>,
 131                                 <0 0 24 &gic 0 0 0 24 4>,
 132                                 <0 0 25 &gic 0 0 0 25 4>,
 133                                 <0 0 26 &gic 0 0 0 26 4>,
 134                                 <0 0 27 &gic 0 0 0 27 4>,
 135                                 <0 0 28 &gic 0 0 0 28 4>,
 136                                 <0 0 29 &gic 0 0 0 29 4>,
 137                                 <0 0 30 &gic 0 0 0 30 4>,
 138                                 <0 0 31 &gic 0 0 0 31 4>,
 139                                 <0 0 32 &gic 0 0 0 32 4>,
 140                                 <0 0 33 &gic 0 0 0 33 4>,
 141                                 <0 0 34 &gic 0 0 0 34 4>,
 142                                 <0 0 35 &gic 0 0 0 35 4>,
 143                                 <0 0 36 &gic 0 0 0 36 4>,
 144                                 <0 0 37 &gic 0 0 0 37 4>,
 145                                 <0 0 38 &gic 0 0 0 38 4>,
 146                                 <0 0 39 &gic 0 0 0 39 4>,
 147                                 <0 0 40 &gic 0 0 0 40 4>,
 148                                 <0 0 41 &gic 0 0 0 41 4>,
 149                                 <0 0 42 &gic 0 0 0 42 4>;
 150
 151                 ethernet@2,02000000 {
 152                         compatible = "smsc,lan91c111";
 153                         reg = <2 0x02000000 0x10000>;
 154                         interrupts = <15>;
 155                 };
 156
 157                 v2m_clk24mhz: clk24mhz {
 158                         compatible = "fixed-clock";
 159                         #clock-cells = <0>;
 160                         clock-frequency = <24000000>;
 161                         clock-output-names = "v2m:clk24mhz";
 162                 };
 163
 164                 v2m_refclk1mhz: refclk1mhz {
 165                         compatible = "fixed-clock";
 166                         #clock-cells = <0>;
 167                         clock-frequency = <1000000>;
 168                         clock-output-names = "v2m:refclk1mhz";
 169                 };
 170
 171                 v2m_refclk32khz: refclk32khz {
 172                         compatible = "fixed-clock";
 173                         #clock-cells = <0>;
 174                         clock-frequency = <32768>;
 175                         clock-output-names = "v2m:refclk32khz";
 176                 };
 177
 178                 iofpga@3,00000000 {
 179                         compatible = "simple-bus";
 180                         #address-cells = <1>;
 181                         #size-cells = <1>;
 182                         ranges = <0 3 0 0x200000>;
 183
 184                         v2m_sysreg: sysreg@10000 {
 185                                 compatible = "arm,vexpress-sysreg";
 186                                 reg = <0x010000 0x1000>;
 187                         };
 188
 189                         v2m_serial0: uart@90000 {
 190                                 compatible = "arm,pl011", "arm,primecell";
 191                                 reg = <0x090000 0x1000>;
 192                                 interrupts = <5>;
 193                                 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
 194                                 clock-names = "uartclk", "apb_pclk";
 195                         };
 196
 197                         v2m_serial1: uart@a0000 {
 198                                 compatible = "arm,pl011", "arm,primecell";
 199                                 reg = <0x0a0000 0x1000>;
 200                                 interrupts = <6>;
 201                                 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
 202                                 clock-names = "uartclk", "apb_pclk";
 203                         };
 204
 205                         v2m_serial2: uart@b0000 {
 206                                 compatible = "arm,pl011", "arm,primecell";
 207                                 reg = <0x0b0000 0x1000>;
 208                                 interrupts = <7>;
 209                                 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
 210                                 clock-names = "uartclk", "apb_pclk";
 211                         };
 212
 213                         v2m_serial3: uart@c0000 {
 214                                 compatible = "arm,pl011", "arm,primecell";
 215                                 reg = <0x0c0000 0x1000>;
 216                                 interrupts = <8>;
 217                                 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
 218                                 clock-names = "uartclk", "apb_pclk";
 219                         };
 220
 221                         virtio-block@130000 {
 222                                 compatible = "virtio,mmio";
 223                                 reg = <0x130000 0x200>;
 224                                 interrupts = <42>;
 225                         };
 226                 };
 227         };
 228 };