2 * dts file for AppliedMicro (APM) X-Gene Storm SOC
4 * Copyright (C) 2013, Applied Micro Circuits Corporation
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
13 compatible = "apm,xgene-storm";
14 interrupt-parent = <&gic>;
24 compatible = "apm,potenza", "arm,armv8";
26 enable-method = "spin-table";
27 cpu-release-addr = <0x1 0x0000fff8>;
31 compatible = "apm,potenza", "arm,armv8";
33 enable-method = "spin-table";
34 cpu-release-addr = <0x1 0x0000fff8>;
38 compatible = "apm,potenza", "arm,armv8";
40 enable-method = "spin-table";
41 cpu-release-addr = <0x1 0x0000fff8>;
45 compatible = "apm,potenza", "arm,armv8";
47 enable-method = "spin-table";
48 cpu-release-addr = <0x1 0x0000fff8>;
52 compatible = "apm,potenza", "arm,armv8";
54 enable-method = "spin-table";
55 cpu-release-addr = <0x1 0x0000fff8>;
59 compatible = "apm,potenza", "arm,armv8";
61 enable-method = "spin-table";
62 cpu-release-addr = <0x1 0x0000fff8>;
66 compatible = "apm,potenza", "arm,armv8";
68 enable-method = "spin-table";
69 cpu-release-addr = <0x1 0x0000fff8>;
73 compatible = "apm,potenza", "arm,armv8";
75 enable-method = "spin-table";
76 cpu-release-addr = <0x1 0x0000fff8>;
80 gic: interrupt-controller@78010000 {
81 compatible = "arm,cortex-a15-gic";
82 #interrupt-cells = <3>;
84 reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */
85 <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */
86 <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */
87 <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */
88 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
92 compatible = "arm,armv8-timer";
93 interrupts = <1 0 0xff01>, /* Secure Phys IRQ */
94 <1 13 0xff01>, /* Non-secure Phys IRQ */
95 <1 14 0xff01>, /* Virt IRQ */
96 <1 15 0xff01>; /* Hyp IRQ */
97 clock-frequency = <50000000>;
101 compatible = "simple-bus";
102 #address-cells = <2>;
105 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
108 #address-cells = <2>;
112 compatible = "fixed-clock";
114 clock-frequency = <100000000>;
115 clock-output-names = "refclk";
118 pcppll: pcppll@17000100 {
119 compatible = "apm,xgene-pcppll-clock";
121 clocks = <&refclk 0>;
122 clock-names = "pcppll";
123 reg = <0x0 0x17000100 0x0 0x1000>;
124 clock-output-names = "pcppll";
128 socpll: socpll@17000120 {
129 compatible = "apm,xgene-socpll-clock";
131 clocks = <&refclk 0>;
132 clock-names = "socpll";
133 reg = <0x0 0x17000120 0x0 0x1000>;
134 clock-output-names = "socpll";
138 socplldiv2: socplldiv2 {
139 compatible = "fixed-factor-clock";
141 clocks = <&socpll 0>;
142 clock-names = "socplldiv2";
145 clock-output-names = "socplldiv2";
149 compatible = "apm,xgene-device-clock";
151 clocks = <&socplldiv2 0>;
152 clock-names = "qmlclk";
153 reg = <0x0 0x1703C000 0x0 0x1000>;
154 reg-names = "csr-reg";
155 clock-output-names = "qmlclk";
159 compatible = "apm,xgene-device-clock";
161 clocks = <&socplldiv2 0>;
162 clock-names = "ethclk";
163 reg = <0x0 0x17000000 0x0 0x1000>;
164 reg-names = "div-reg";
165 divider-offset = <0x238>;
166 divider-width = <0x9>;
167 divider-shift = <0x0>;
168 clock-output-names = "ethclk";
172 compatible = "apm,xgene-device-clock";
174 clocks = <ðclk 0>;
175 reg = <0x0 0x1702C000 0x0 0x1000>;
176 reg-names = "csr-reg";
177 clock-output-names = "menetclk";
180 sge0clk: sge0clk@1f21c000 {
181 compatible = "apm,xgene-device-clock";
183 clocks = <&socplldiv2 0>;
184 reg = <0x0 0x1f21c000 0x0 0x1000>;
185 reg-names = "csr-reg";
187 clock-output-names = "sge0clk";
190 sge1clk: sge1clk@1f21c000 {
191 compatible = "apm,xgene-device-clock";
193 clocks = <&socplldiv2 0>;
194 reg = <0x0 0x1f21c000 0x0 0x1000>;
195 reg-names = "csr-reg";
197 clock-output-names = "sge1clk";
200 xge0clk: xge0clk@1f61c000 {
201 compatible = "apm,xgene-device-clock";
203 clocks = <&socplldiv2 0>;
204 reg = <0x0 0x1f61c000 0x0 0x1000>;
205 reg-names = "csr-reg";
207 clock-output-names = "xge0clk";
210 xge1clk: xge1clk@1f62c000 {
211 compatible = "apm,xgene-device-clock";
214 clocks = <&socplldiv2 0>;
215 reg = <0x0 0x1f62c000 0x0 0x1000>;
216 reg-names = "csr-reg";
218 clock-output-names = "xge1clk";
221 sataphy1clk: sataphy1clk@1f21c000 {
222 compatible = "apm,xgene-device-clock";
224 clocks = <&socplldiv2 0>;
225 reg = <0x0 0x1f21c000 0x0 0x1000>;
226 reg-names = "csr-reg";
227 clock-output-names = "sataphy1clk";
231 enable-offset = <0x0>;
232 enable-mask = <0x06>;
235 sataphy2clk: sataphy1clk@1f22c000 {
236 compatible = "apm,xgene-device-clock";
238 clocks = <&socplldiv2 0>;
239 reg = <0x0 0x1f22c000 0x0 0x1000>;
240 reg-names = "csr-reg";
241 clock-output-names = "sataphy2clk";
245 enable-offset = <0x0>;
246 enable-mask = <0x06>;
249 sataphy3clk: sataphy1clk@1f23c000 {
250 compatible = "apm,xgene-device-clock";
252 clocks = <&socplldiv2 0>;
253 reg = <0x0 0x1f23c000 0x0 0x1000>;
254 reg-names = "csr-reg";
255 clock-output-names = "sataphy3clk";
259 enable-offset = <0x0>;
260 enable-mask = <0x06>;
263 sata01clk: sata01clk@1f21c000 {
264 compatible = "apm,xgene-device-clock";
266 clocks = <&socplldiv2 0>;
267 reg = <0x0 0x1f21c000 0x0 0x1000>;
268 reg-names = "csr-reg";
269 clock-output-names = "sata01clk";
272 enable-offset = <0x0>;
273 enable-mask = <0x39>;
276 sata23clk: sata23clk@1f22c000 {
277 compatible = "apm,xgene-device-clock";
279 clocks = <&socplldiv2 0>;
280 reg = <0x0 0x1f22c000 0x0 0x1000>;
281 reg-names = "csr-reg";
282 clock-output-names = "sata23clk";
285 enable-offset = <0x0>;
286 enable-mask = <0x39>;
289 sata45clk: sata45clk@1f23c000 {
290 compatible = "apm,xgene-device-clock";
292 clocks = <&socplldiv2 0>;
293 reg = <0x0 0x1f23c000 0x0 0x1000>;
294 reg-names = "csr-reg";
295 clock-output-names = "sata45clk";
298 enable-offset = <0x0>;
299 enable-mask = <0x39>;
302 rtcclk: rtcclk@17000000 {
303 compatible = "apm,xgene-device-clock";
305 clocks = <&socplldiv2 0>;
306 reg = <0x0 0x17000000 0x0 0x2000>;
307 reg-names = "csr-reg";
310 enable-offset = <0x10>;
312 clock-output-names = "rtcclk";
315 rngpkaclk: rngpkaclk@17000000 {
316 compatible = "apm,xgene-device-clock";
318 clocks = <&socplldiv2 0>;
319 reg = <0x0 0x17000000 0x0 0x2000>;
320 reg-names = "csr-reg";
323 enable-offset = <0x10>;
324 enable-mask = <0x10>;
325 clock-output-names = "rngpkaclk";
328 pcie0clk: pcie0clk@1f2bc000 {
330 compatible = "apm,xgene-device-clock";
332 clocks = <&socplldiv2 0>;
333 reg = <0x0 0x1f2bc000 0x0 0x1000>;
334 reg-names = "csr-reg";
335 clock-output-names = "pcie0clk";
338 pcie1clk: pcie1clk@1f2cc000 {
340 compatible = "apm,xgene-device-clock";
342 clocks = <&socplldiv2 0>;
343 reg = <0x0 0x1f2cc000 0x0 0x1000>;
344 reg-names = "csr-reg";
345 clock-output-names = "pcie1clk";
348 pcie2clk: pcie2clk@1f2dc000 {
350 compatible = "apm,xgene-device-clock";
352 clocks = <&socplldiv2 0>;
353 reg = <0x0 0x1f2dc000 0x0 0x1000>;
354 reg-names = "csr-reg";
355 clock-output-names = "pcie2clk";
358 pcie3clk: pcie3clk@1f50c000 {
360 compatible = "apm,xgene-device-clock";
362 clocks = <&socplldiv2 0>;
363 reg = <0x0 0x1f50c000 0x0 0x1000>;
364 reg-names = "csr-reg";
365 clock-output-names = "pcie3clk";
368 pcie4clk: pcie4clk@1f51c000 {
370 compatible = "apm,xgene-device-clock";
372 clocks = <&socplldiv2 0>;
373 reg = <0x0 0x1f51c000 0x0 0x1000>;
374 reg-names = "csr-reg";
375 clock-output-names = "pcie4clk";
378 dmaclk: dmaclk@1f27c000 {
379 compatible = "apm,xgene-device-clock";
381 clocks = <&socplldiv2 0>;
382 reg = <0x0 0x1f27c000 0x0 0x1000>;
383 reg-names = "csr-reg";
384 clock-output-names = "dmaclk";
389 compatible = "apm,xgene1-msi";
391 reg = <0x00 0x79000000 0x0 0x900000>;
392 interrupts = < 0x0 0x10 0x4
411 compatible = "apm,xgene-csw", "syscon";
412 reg = <0x0 0x7e200000 0x0 0x1000>;
415 mcba: mcba@7e700000 {
416 compatible = "apm,xgene-mcb", "syscon";
417 reg = <0x0 0x7e700000 0x0 0x1000>;
420 mcbb: mcbb@7e720000 {
421 compatible = "apm,xgene-mcb", "syscon";
422 reg = <0x0 0x7e720000 0x0 0x1000>;
425 efuse: efuse@1054a000 {
426 compatible = "apm,xgene-efuse", "syscon";
427 reg = <0x0 0x1054a000 0x0 0x20>;
431 compatible = "apm,xgene-edac";
432 #address-cells = <2>;
436 regmap-mcba = <&mcba>;
437 regmap-mcbb = <&mcbb>;
438 regmap-efuse = <&efuse>;
439 reg = <0x0 0x78800000 0x0 0x100>;
440 interrupts = <0x0 0x20 0x4>,
445 compatible = "apm,xgene-edac-mc";
446 reg = <0x0 0x7e800000 0x0 0x1000>;
447 memory-controller = <0>;
451 compatible = "apm,xgene-edac-mc";
452 reg = <0x0 0x7e840000 0x0 0x1000>;
453 memory-controller = <1>;
457 compatible = "apm,xgene-edac-mc";
458 reg = <0x0 0x7e880000 0x0 0x1000>;
459 memory-controller = <2>;
463 compatible = "apm,xgene-edac-mc";
464 reg = <0x0 0x7e8c0000 0x0 0x1000>;
465 memory-controller = <3>;
469 compatible = "apm,xgene-edac-pmd";
470 reg = <0x0 0x7c000000 0x0 0x200000>;
471 pmd-controller = <0>;
475 compatible = "apm,xgene-edac-pmd";
476 reg = <0x0 0x7c200000 0x0 0x200000>;
477 pmd-controller = <1>;
481 compatible = "apm,xgene-edac-pmd";
482 reg = <0x0 0x7c400000 0x0 0x200000>;
483 pmd-controller = <2>;
487 compatible = "apm,xgene-edac-pmd";
488 reg = <0x0 0x7c600000 0x0 0x200000>;
489 pmd-controller = <3>;
493 compatible = "apm,xgene-edac-l3";
494 reg = <0x0 0x7e600000 0x0 0x1000>;
498 compatible = "apm,xgene-edac-soc-v1";
499 reg = <0x0 0x7e930000 0x0 0x1000>;
503 pcie0: pcie@1f2b0000 {
506 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
507 #interrupt-cells = <1>;
509 #address-cells = <3>;
510 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
511 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
512 reg-names = "csr", "cfg";
513 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
514 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000 /* mem */
515 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
516 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
517 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
518 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
519 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
520 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
521 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
522 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
524 clocks = <&pcie0clk 0>;
528 pcie1: pcie@1f2c0000 {
531 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
532 #interrupt-cells = <1>;
534 #address-cells = <3>;
535 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
536 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
537 reg-names = "csr", "cfg";
538 ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */
539 0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000 /* mem */
540 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
541 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
542 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
543 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
544 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1
545 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1
546 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1
547 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>;
549 clocks = <&pcie1clk 0>;
553 pcie2: pcie@1f2d0000 {
556 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
557 #interrupt-cells = <1>;
559 #address-cells = <3>;
560 reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */
561 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
562 reg-names = "csr", "cfg";
563 ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000 /* io */
564 0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000 /* mem */
565 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
566 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
567 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
568 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
569 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1
570 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1
571 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1
572 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>;
574 clocks = <&pcie2clk 0>;
578 pcie3: pcie@1f500000 {
581 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
582 #interrupt-cells = <1>;
584 #address-cells = <3>;
585 reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */
586 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
587 reg-names = "csr", "cfg";
588 ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */
589 0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000 /* mem */
590 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
591 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
592 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
593 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
594 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1
595 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1
596 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1
597 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>;
599 clocks = <&pcie3clk 0>;
603 pcie4: pcie@1f510000 {
606 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
607 #interrupt-cells = <1>;
609 #address-cells = <3>;
610 reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */
611 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
612 reg-names = "csr", "cfg";
613 ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */
614 0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000 /* mem */
615 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
616 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
617 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
618 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
619 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1
620 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1
621 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1
622 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>;
624 clocks = <&pcie4clk 0>;
628 serial0: serial@1c020000 {
630 device_type = "serial";
631 compatible = "ns16550a";
632 reg = <0 0x1c020000 0x0 0x1000>;
634 clock-frequency = <10000000>; /* Updated by bootloader */
635 interrupt-parent = <&gic>;
636 interrupts = <0x0 0x4c 0x4>;
639 serial1: serial@1c021000 {
641 device_type = "serial";
642 compatible = "ns16550a";
643 reg = <0 0x1c021000 0x0 0x1000>;
645 clock-frequency = <10000000>; /* Updated by bootloader */
646 interrupt-parent = <&gic>;
647 interrupts = <0x0 0x4d 0x4>;
650 serial2: serial@1c022000 {
652 device_type = "serial";
653 compatible = "ns16550a";
654 reg = <0 0x1c022000 0x0 0x1000>;
656 clock-frequency = <10000000>; /* Updated by bootloader */
657 interrupt-parent = <&gic>;
658 interrupts = <0x0 0x4e 0x4>;
661 serial3: serial@1c023000 {
663 device_type = "serial";
664 compatible = "ns16550a";
665 reg = <0 0x1c023000 0x0 0x1000>;
667 clock-frequency = <10000000>; /* Updated by bootloader */
668 interrupt-parent = <&gic>;
669 interrupts = <0x0 0x4f 0x4>;
673 compatible = "apm,xgene-phy";
674 reg = <0x0 0x1f21a000 0x0 0x100>;
676 clocks = <&sataphy1clk 0>;
678 apm,tx-boost-gain = <30 30 30 30 30 30>;
679 apm,tx-eye-tuning = <2 10 10 2 10 10>;
683 compatible = "apm,xgene-phy";
684 reg = <0x0 0x1f22a000 0x0 0x100>;
686 clocks = <&sataphy2clk 0>;
688 apm,tx-boost-gain = <30 30 30 30 30 30>;
689 apm,tx-eye-tuning = <1 10 10 2 10 10>;
693 compatible = "apm,xgene-phy";
694 reg = <0x0 0x1f23a000 0x0 0x100>;
696 clocks = <&sataphy3clk 0>;
698 apm,tx-boost-gain = <31 31 31 31 31 31>;
699 apm,tx-eye-tuning = <2 10 10 2 10 10>;
702 sata1: sata@1a000000 {
703 compatible = "apm,xgene-ahci";
704 reg = <0x0 0x1a000000 0x0 0x1000>,
705 <0x0 0x1f210000 0x0 0x1000>,
706 <0x0 0x1f21d000 0x0 0x1000>,
707 <0x0 0x1f21e000 0x0 0x1000>,
708 <0x0 0x1f217000 0x0 0x1000>;
709 interrupts = <0x0 0x86 0x4>;
712 clocks = <&sata01clk 0>;
714 phy-names = "sata-phy";
717 sata2: sata@1a400000 {
718 compatible = "apm,xgene-ahci";
719 reg = <0x0 0x1a400000 0x0 0x1000>,
720 <0x0 0x1f220000 0x0 0x1000>,
721 <0x0 0x1f22d000 0x0 0x1000>,
722 <0x0 0x1f22e000 0x0 0x1000>,
723 <0x0 0x1f227000 0x0 0x1000>;
724 interrupts = <0x0 0x87 0x4>;
727 clocks = <&sata23clk 0>;
729 phy-names = "sata-phy";
732 sata3: sata@1a800000 {
733 compatible = "apm,xgene-ahci";
734 reg = <0x0 0x1a800000 0x0 0x1000>,
735 <0x0 0x1f230000 0x0 0x1000>,
736 <0x0 0x1f23d000 0x0 0x1000>,
737 <0x0 0x1f23e000 0x0 0x1000>;
738 interrupts = <0x0 0x88 0x4>;
741 clocks = <&sata45clk 0>;
743 phy-names = "sata-phy";
746 sbgpio: sbgpio@17001000{
747 compatible = "apm,xgene-gpio-sb";
748 reg = <0x0 0x17001000 0x0 0x400>;
751 interrupts = <0x0 0x28 0x1>,
760 compatible = "apm,xgene-rtc";
761 reg = <0x0 0x10510000 0x0 0x400>;
762 interrupts = <0x0 0x46 0x4>;
764 clocks = <&rtcclk 0>;
767 menet: ethernet@17020000 {
768 compatible = "apm,xgene-enet";
770 reg = <0x0 0x17020000 0x0 0xd100>,
771 <0x0 0X17030000 0x0 0Xc300>,
772 <0x0 0X10000000 0x0 0X200>;
773 reg-names = "enet_csr", "ring_csr", "ring_cmd";
774 interrupts = <0x0 0x3c 0x4>;
776 clocks = <&menetclk 0>;
777 /* mac address will be overwritten by the bootloader */
778 local-mac-address = [00 00 00 00 00 00];
779 phy-connection-type = "rgmii";
780 phy-handle = <&menetphy>;
782 compatible = "apm,xgene-mdio";
783 #address-cells = <1>;
785 menetphy: menetphy@3 {
786 compatible = "ethernet-phy-id001c.c915";
793 sgenet0: ethernet@1f210000 {
794 compatible = "apm,xgene1-sgenet";
796 reg = <0x0 0x1f210000 0x0 0xd100>,
797 <0x0 0x1f200000 0x0 0Xc300>,
798 <0x0 0x1B000000 0x0 0X200>;
799 reg-names = "enet_csr", "ring_csr", "ring_cmd";
800 interrupts = <0x0 0xA0 0x4>,
803 clocks = <&sge0clk 0>;
804 local-mac-address = [00 00 00 00 00 00];
805 phy-connection-type = "sgmii";
808 sgenet1: ethernet@1f210030 {
809 compatible = "apm,xgene1-sgenet";
811 reg = <0x0 0x1f210030 0x0 0xd100>,
812 <0x0 0x1f200000 0x0 0Xc300>,
813 <0x0 0x1B000000 0x0 0X8000>;
814 reg-names = "enet_csr", "ring_csr", "ring_cmd";
815 interrupts = <0x0 0xAC 0x4>,
819 clocks = <&sge1clk 0>;
820 local-mac-address = [00 00 00 00 00 00];
821 phy-connection-type = "sgmii";
824 xgenet: ethernet@1f610000 {
825 compatible = "apm,xgene1-xgenet";
827 reg = <0x0 0x1f610000 0x0 0xd100>,
828 <0x0 0x1f600000 0x0 0Xc300>,
829 <0x0 0x18000000 0x0 0X200>;
830 reg-names = "enet_csr", "ring_csr", "ring_cmd";
831 interrupts = <0x0 0x60 0x4>,
834 clocks = <&xge0clk 0>;
835 /* mac address will be overwritten by the bootloader */
836 local-mac-address = [00 00 00 00 00 00];
837 phy-connection-type = "xgmii";
840 xgenet1: ethernet@1f620000 {
841 compatible = "apm,xgene1-xgenet";
843 reg = <0x0 0x1f620000 0x0 0xd100>,
844 <0x0 0x1f600000 0x0 0Xc300>,
845 <0x0 0x18000000 0x0 0X8000>;
846 reg-names = "enet_csr", "ring_csr", "ring_cmd";
847 interrupts = <0x0 0x6C 0x4>,
851 clocks = <&xge1clk 0>;
852 /* mac address will be overwritten by the bootloader */
853 local-mac-address = [00 00 00 00 00 00];
854 phy-connection-type = "xgmii";
858 compatible = "apm,xgene-rng";
859 reg = <0x0 0x10520000 0x0 0x100>;
860 interrupts = <0x0 0x41 0x4>;
861 clocks = <&rngpkaclk 0>;
865 compatible = "apm,xgene-storm-dma";
867 reg = <0x0 0x1f270000 0x0 0x10000>,
868 <0x0 0x1f200000 0x0 0x10000>,
869 <0x0 0x1b000000 0x0 0x400000>,
870 <0x0 0x1054a000 0x0 0x100>;
871 interrupts = <0x0 0x82 0x4>,
877 clocks = <&dmaclk 0>;