2 * dts file for AppliedMicro (APM) X-Gene Storm SOC
4 * Copyright (C) 2013, Applied Micro Circuits Corporation
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
13 compatible = "apm,xgene-storm";
14 interrupt-parent = <&gic>;
24 compatible = "apm,potenza", "arm,armv8";
26 enable-method = "spin-table";
27 cpu-release-addr = <0x1 0x0000fff8>;
28 next-level-cache = <&xgene_L2_0>;
32 compatible = "apm,potenza", "arm,armv8";
34 enable-method = "spin-table";
35 cpu-release-addr = <0x1 0x0000fff8>;
36 next-level-cache = <&xgene_L2_0>;
40 compatible = "apm,potenza", "arm,armv8";
42 enable-method = "spin-table";
43 cpu-release-addr = <0x1 0x0000fff8>;
44 next-level-cache = <&xgene_L2_1>;
48 compatible = "apm,potenza", "arm,armv8";
50 enable-method = "spin-table";
51 cpu-release-addr = <0x1 0x0000fff8>;
52 next-level-cache = <&xgene_L2_1>;
56 compatible = "apm,potenza", "arm,armv8";
58 enable-method = "spin-table";
59 cpu-release-addr = <0x1 0x0000fff8>;
60 next-level-cache = <&xgene_L2_2>;
64 compatible = "apm,potenza", "arm,armv8";
66 enable-method = "spin-table";
67 cpu-release-addr = <0x1 0x0000fff8>;
68 next-level-cache = <&xgene_L2_2>;
72 compatible = "apm,potenza", "arm,armv8";
74 enable-method = "spin-table";
75 cpu-release-addr = <0x1 0x0000fff8>;
76 next-level-cache = <&xgene_L2_3>;
80 compatible = "apm,potenza", "arm,armv8";
82 enable-method = "spin-table";
83 cpu-release-addr = <0x1 0x0000fff8>;
84 next-level-cache = <&xgene_L2_3>;
86 xgene_L2_0: l2-cache-0 {
89 xgene_L2_1: l2-cache-1 {
92 xgene_L2_2: l2-cache-2 {
95 xgene_L2_3: l2-cache-3 {
100 gic: interrupt-controller@78010000 {
101 compatible = "arm,cortex-a15-gic";
102 #interrupt-cells = <3>;
103 interrupt-controller;
104 reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */
105 <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */
106 <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */
107 <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */
108 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
112 compatible = "arm,armv8-timer";
113 interrupts = <1 0 0xff01>, /* Secure Phys IRQ */
114 <1 13 0xff01>, /* Non-secure Phys IRQ */
115 <1 14 0xff01>, /* Virt IRQ */
116 <1 15 0xff01>; /* Hyp IRQ */
117 clock-frequency = <50000000>;
121 compatible = "apm,potenza-pmu", "arm,armv8-pmuv3";
122 interrupts = <1 12 0xff04>;
126 compatible = "simple-bus";
127 #address-cells = <2>;
130 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
133 #address-cells = <2>;
137 compatible = "fixed-clock";
139 clock-frequency = <100000000>;
140 clock-output-names = "refclk";
143 pcppll: pcppll@17000100 {
144 compatible = "apm,xgene-pcppll-clock";
146 clocks = <&refclk 0>;
147 clock-names = "pcppll";
148 reg = <0x0 0x17000100 0x0 0x1000>;
149 clock-output-names = "pcppll";
153 socpll: socpll@17000120 {
154 compatible = "apm,xgene-socpll-clock";
156 clocks = <&refclk 0>;
157 clock-names = "socpll";
158 reg = <0x0 0x17000120 0x0 0x1000>;
159 clock-output-names = "socpll";
163 socplldiv2: socplldiv2 {
164 compatible = "fixed-factor-clock";
166 clocks = <&socpll 0>;
167 clock-names = "socplldiv2";
170 clock-output-names = "socplldiv2";
173 ahbclk: ahbclk@17000000 {
174 compatible = "apm,xgene-device-clock";
176 clocks = <&socplldiv2 0>;
177 reg = <0x0 0x17000000 0x0 0x2000>;
178 reg-names = "div-reg";
179 divider-offset = <0x164>;
180 divider-width = <0x5>;
181 divider-shift = <0x0>;
182 clock-output-names = "ahbclk";
185 sdioclk: sdioclk@1f2ac000 {
186 compatible = "apm,xgene-device-clock";
188 clocks = <&socplldiv2 0>;
189 reg = <0x0 0x1f2ac000 0x0 0x1000
190 0x0 0x17000000 0x0 0x2000>;
191 reg-names = "csr-reg", "div-reg";
194 enable-offset = <0x8>;
196 divider-offset = <0x178>;
197 divider-width = <0x8>;
198 divider-shift = <0x0>;
199 clock-output-names = "sdioclk";
203 compatible = "apm,xgene-device-clock";
205 clocks = <&socplldiv2 0>;
206 clock-names = "qmlclk";
207 reg = <0x0 0x1703C000 0x0 0x1000>;
208 reg-names = "csr-reg";
209 clock-output-names = "qmlclk";
213 compatible = "apm,xgene-device-clock";
215 clocks = <&socplldiv2 0>;
216 clock-names = "ethclk";
217 reg = <0x0 0x17000000 0x0 0x1000>;
218 reg-names = "div-reg";
219 divider-offset = <0x238>;
220 divider-width = <0x9>;
221 divider-shift = <0x0>;
222 clock-output-names = "ethclk";
226 compatible = "apm,xgene-device-clock";
228 clocks = <ðclk 0>;
229 reg = <0x0 0x1702C000 0x0 0x1000>;
230 reg-names = "csr-reg";
231 clock-output-names = "menetclk";
234 sge0clk: sge0clk@1f21c000 {
235 compatible = "apm,xgene-device-clock";
237 clocks = <&socplldiv2 0>;
238 reg = <0x0 0x1f21c000 0x0 0x1000>;
239 reg-names = "csr-reg";
241 clock-output-names = "sge0clk";
244 sge1clk: sge1clk@1f21c000 {
245 compatible = "apm,xgene-device-clock";
247 clocks = <&socplldiv2 0>;
248 reg = <0x0 0x1f21c000 0x0 0x1000>;
249 reg-names = "csr-reg";
251 clock-output-names = "sge1clk";
254 xge0clk: xge0clk@1f61c000 {
255 compatible = "apm,xgene-device-clock";
257 clocks = <&socplldiv2 0>;
258 reg = <0x0 0x1f61c000 0x0 0x1000>;
259 reg-names = "csr-reg";
261 clock-output-names = "xge0clk";
264 xge1clk: xge1clk@1f62c000 {
265 compatible = "apm,xgene-device-clock";
268 clocks = <&socplldiv2 0>;
269 reg = <0x0 0x1f62c000 0x0 0x1000>;
270 reg-names = "csr-reg";
272 clock-output-names = "xge1clk";
275 sataphy1clk: sataphy1clk@1f21c000 {
276 compatible = "apm,xgene-device-clock";
278 clocks = <&socplldiv2 0>;
279 reg = <0x0 0x1f21c000 0x0 0x1000>;
280 reg-names = "csr-reg";
281 clock-output-names = "sataphy1clk";
285 enable-offset = <0x0>;
286 enable-mask = <0x06>;
289 sataphy2clk: sataphy1clk@1f22c000 {
290 compatible = "apm,xgene-device-clock";
292 clocks = <&socplldiv2 0>;
293 reg = <0x0 0x1f22c000 0x0 0x1000>;
294 reg-names = "csr-reg";
295 clock-output-names = "sataphy2clk";
299 enable-offset = <0x0>;
300 enable-mask = <0x06>;
303 sataphy3clk: sataphy1clk@1f23c000 {
304 compatible = "apm,xgene-device-clock";
306 clocks = <&socplldiv2 0>;
307 reg = <0x0 0x1f23c000 0x0 0x1000>;
308 reg-names = "csr-reg";
309 clock-output-names = "sataphy3clk";
313 enable-offset = <0x0>;
314 enable-mask = <0x06>;
317 sata01clk: sata01clk@1f21c000 {
318 compatible = "apm,xgene-device-clock";
320 clocks = <&socplldiv2 0>;
321 reg = <0x0 0x1f21c000 0x0 0x1000>;
322 reg-names = "csr-reg";
323 clock-output-names = "sata01clk";
326 enable-offset = <0x0>;
327 enable-mask = <0x39>;
330 sata23clk: sata23clk@1f22c000 {
331 compatible = "apm,xgene-device-clock";
333 clocks = <&socplldiv2 0>;
334 reg = <0x0 0x1f22c000 0x0 0x1000>;
335 reg-names = "csr-reg";
336 clock-output-names = "sata23clk";
339 enable-offset = <0x0>;
340 enable-mask = <0x39>;
343 sata45clk: sata45clk@1f23c000 {
344 compatible = "apm,xgene-device-clock";
346 clocks = <&socplldiv2 0>;
347 reg = <0x0 0x1f23c000 0x0 0x1000>;
348 reg-names = "csr-reg";
349 clock-output-names = "sata45clk";
352 enable-offset = <0x0>;
353 enable-mask = <0x39>;
356 rtcclk: rtcclk@17000000 {
357 compatible = "apm,xgene-device-clock";
359 clocks = <&socplldiv2 0>;
360 reg = <0x0 0x17000000 0x0 0x2000>;
361 reg-names = "csr-reg";
364 enable-offset = <0x10>;
366 clock-output-names = "rtcclk";
369 rngpkaclk: rngpkaclk@17000000 {
370 compatible = "apm,xgene-device-clock";
372 clocks = <&socplldiv2 0>;
373 reg = <0x0 0x17000000 0x0 0x2000>;
374 reg-names = "csr-reg";
377 enable-offset = <0x10>;
378 enable-mask = <0x10>;
379 clock-output-names = "rngpkaclk";
382 pcie0clk: pcie0clk@1f2bc000 {
384 compatible = "apm,xgene-device-clock";
386 clocks = <&socplldiv2 0>;
387 reg = <0x0 0x1f2bc000 0x0 0x1000>;
388 reg-names = "csr-reg";
389 clock-output-names = "pcie0clk";
392 pcie1clk: pcie1clk@1f2cc000 {
394 compatible = "apm,xgene-device-clock";
396 clocks = <&socplldiv2 0>;
397 reg = <0x0 0x1f2cc000 0x0 0x1000>;
398 reg-names = "csr-reg";
399 clock-output-names = "pcie1clk";
402 pcie2clk: pcie2clk@1f2dc000 {
404 compatible = "apm,xgene-device-clock";
406 clocks = <&socplldiv2 0>;
407 reg = <0x0 0x1f2dc000 0x0 0x1000>;
408 reg-names = "csr-reg";
409 clock-output-names = "pcie2clk";
412 pcie3clk: pcie3clk@1f50c000 {
414 compatible = "apm,xgene-device-clock";
416 clocks = <&socplldiv2 0>;
417 reg = <0x0 0x1f50c000 0x0 0x1000>;
418 reg-names = "csr-reg";
419 clock-output-names = "pcie3clk";
422 pcie4clk: pcie4clk@1f51c000 {
424 compatible = "apm,xgene-device-clock";
426 clocks = <&socplldiv2 0>;
427 reg = <0x0 0x1f51c000 0x0 0x1000>;
428 reg-names = "csr-reg";
429 clock-output-names = "pcie4clk";
432 dmaclk: dmaclk@1f27c000 {
433 compatible = "apm,xgene-device-clock";
435 clocks = <&socplldiv2 0>;
436 reg = <0x0 0x1f27c000 0x0 0x1000>;
437 reg-names = "csr-reg";
438 clock-output-names = "dmaclk";
443 compatible = "apm,xgene1-msi";
445 reg = <0x00 0x79000000 0x0 0x900000>;
446 interrupts = < 0x0 0x10 0x4
464 scu: system-clk-controller@17000000 {
465 compatible = "apm,xgene-scu","syscon";
466 reg = <0x0 0x17000000 0x0 0x400>;
469 reboot: reboot@17000014 {
470 compatible = "syscon-reboot";
477 compatible = "apm,xgene-csw", "syscon";
478 reg = <0x0 0x7e200000 0x0 0x1000>;
481 mcba: mcba@7e700000 {
482 compatible = "apm,xgene-mcb", "syscon";
483 reg = <0x0 0x7e700000 0x0 0x1000>;
486 mcbb: mcbb@7e720000 {
487 compatible = "apm,xgene-mcb", "syscon";
488 reg = <0x0 0x7e720000 0x0 0x1000>;
491 efuse: efuse@1054a000 {
492 compatible = "apm,xgene-efuse", "syscon";
493 reg = <0x0 0x1054a000 0x0 0x20>;
497 compatible = "apm,xgene-rb", "syscon";
498 reg = <0x0 0x7e000000 0x0 0x10>;
502 compatible = "apm,xgene-edac";
503 #address-cells = <2>;
507 regmap-mcba = <&mcba>;
508 regmap-mcbb = <&mcbb>;
509 regmap-efuse = <&efuse>;
511 reg = <0x0 0x78800000 0x0 0x100>;
512 interrupts = <0x0 0x20 0x4>,
517 compatible = "apm,xgene-edac-mc";
518 reg = <0x0 0x7e800000 0x0 0x1000>;
519 memory-controller = <0>;
523 compatible = "apm,xgene-edac-mc";
524 reg = <0x0 0x7e840000 0x0 0x1000>;
525 memory-controller = <1>;
529 compatible = "apm,xgene-edac-mc";
530 reg = <0x0 0x7e880000 0x0 0x1000>;
531 memory-controller = <2>;
535 compatible = "apm,xgene-edac-mc";
536 reg = <0x0 0x7e8c0000 0x0 0x1000>;
537 memory-controller = <3>;
541 compatible = "apm,xgene-edac-pmd";
542 reg = <0x0 0x7c000000 0x0 0x200000>;
543 pmd-controller = <0>;
547 compatible = "apm,xgene-edac-pmd";
548 reg = <0x0 0x7c200000 0x0 0x200000>;
549 pmd-controller = <1>;
553 compatible = "apm,xgene-edac-pmd";
554 reg = <0x0 0x7c400000 0x0 0x200000>;
555 pmd-controller = <2>;
559 compatible = "apm,xgene-edac-pmd";
560 reg = <0x0 0x7c600000 0x0 0x200000>;
561 pmd-controller = <3>;
565 compatible = "apm,xgene-edac-l3";
566 reg = <0x0 0x7e600000 0x0 0x1000>;
570 compatible = "apm,xgene-edac-soc-v1";
571 reg = <0x0 0x7e930000 0x0 0x1000>;
575 pcie0: pcie@1f2b0000 {
578 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
579 #interrupt-cells = <1>;
581 #address-cells = <3>;
582 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
583 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
584 reg-names = "csr", "cfg";
585 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
586 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000 /* mem */
587 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
588 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
589 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
590 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
591 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
592 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
593 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
594 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
596 clocks = <&pcie0clk 0>;
600 pcie1: pcie@1f2c0000 {
603 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
604 #interrupt-cells = <1>;
606 #address-cells = <3>;
607 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
608 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
609 reg-names = "csr", "cfg";
610 ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */
611 0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000 /* mem */
612 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
613 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
614 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
615 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
616 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1
617 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1
618 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1
619 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>;
621 clocks = <&pcie1clk 0>;
625 pcie2: pcie@1f2d0000 {
628 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
629 #interrupt-cells = <1>;
631 #address-cells = <3>;
632 reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */
633 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
634 reg-names = "csr", "cfg";
635 ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000 /* io */
636 0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000 /* mem */
637 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
638 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
639 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
640 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
641 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1
642 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1
643 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1
644 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>;
646 clocks = <&pcie2clk 0>;
650 pcie3: pcie@1f500000 {
653 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
654 #interrupt-cells = <1>;
656 #address-cells = <3>;
657 reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */
658 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
659 reg-names = "csr", "cfg";
660 ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */
661 0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000 /* mem */
662 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
663 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
664 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
665 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
666 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1
667 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1
668 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1
669 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>;
671 clocks = <&pcie3clk 0>;
675 pcie4: pcie@1f510000 {
678 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
679 #interrupt-cells = <1>;
681 #address-cells = <3>;
682 reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */
683 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
684 reg-names = "csr", "cfg";
685 ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */
686 0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000 /* mem */
687 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
688 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
689 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
690 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
691 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1
692 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1
693 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1
694 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>;
696 clocks = <&pcie4clk 0>;
700 serial0: serial@1c020000 {
702 device_type = "serial";
703 compatible = "ns16550a";
704 reg = <0 0x1c020000 0x0 0x1000>;
706 clock-frequency = <10000000>; /* Updated by bootloader */
707 interrupt-parent = <&gic>;
708 interrupts = <0x0 0x4c 0x4>;
711 serial1: serial@1c021000 {
713 device_type = "serial";
714 compatible = "ns16550a";
715 reg = <0 0x1c021000 0x0 0x1000>;
717 clock-frequency = <10000000>; /* Updated by bootloader */
718 interrupt-parent = <&gic>;
719 interrupts = <0x0 0x4d 0x4>;
722 serial2: serial@1c022000 {
724 device_type = "serial";
725 compatible = "ns16550a";
726 reg = <0 0x1c022000 0x0 0x1000>;
728 clock-frequency = <10000000>; /* Updated by bootloader */
729 interrupt-parent = <&gic>;
730 interrupts = <0x0 0x4e 0x4>;
733 serial3: serial@1c023000 {
735 device_type = "serial";
736 compatible = "ns16550a";
737 reg = <0 0x1c023000 0x0 0x1000>;
739 clock-frequency = <10000000>; /* Updated by bootloader */
740 interrupt-parent = <&gic>;
741 interrupts = <0x0 0x4f 0x4>;
745 compatible = "arasan,sdhci-4.9a";
746 reg = <0x0 0x1c000000 0x0 0x100>;
747 interrupts = <0x0 0x49 0x4>;
750 clock-names = "clk_xin", "clk_ahb";
751 clocks = <&sdioclk 0>, <&ahbclk 0>;
754 gfcgpio: gpio0@1701c000 {
755 compatible = "apm,xgene-gpio";
756 reg = <0x0 0x1701c000 0x0 0x40>;
761 dwgpio: gpio@1c024000 {
762 compatible = "snps,dw-apb-gpio";
763 reg = <0x0 0x1c024000 0x0 0x1000>;
765 #address-cells = <1>;
768 porta: gpio-controller@0 {
769 compatible = "snps,dw-apb-gpio-port";
771 snps,nr-gpios = <32>;
778 #address-cells = <1>;
780 compatible = "snps,designware-i2c";
781 reg = <0x0 0x10512000 0x0 0x1000>;
782 interrupts = <0 0x44 0x4>;
784 clocks = <&ahbclk 0>;
789 compatible = "apm,xgene-phy";
790 reg = <0x0 0x1f21a000 0x0 0x100>;
792 clocks = <&sataphy1clk 0>;
794 apm,tx-boost-gain = <30 30 30 30 30 30>;
795 apm,tx-eye-tuning = <2 10 10 2 10 10>;
799 compatible = "apm,xgene-phy";
800 reg = <0x0 0x1f22a000 0x0 0x100>;
802 clocks = <&sataphy2clk 0>;
804 apm,tx-boost-gain = <30 30 30 30 30 30>;
805 apm,tx-eye-tuning = <1 10 10 2 10 10>;
809 compatible = "apm,xgene-phy";
810 reg = <0x0 0x1f23a000 0x0 0x100>;
812 clocks = <&sataphy3clk 0>;
814 apm,tx-boost-gain = <31 31 31 31 31 31>;
815 apm,tx-eye-tuning = <2 10 10 2 10 10>;
818 sata1: sata@1a000000 {
819 compatible = "apm,xgene-ahci";
820 reg = <0x0 0x1a000000 0x0 0x1000>,
821 <0x0 0x1f210000 0x0 0x1000>,
822 <0x0 0x1f21d000 0x0 0x1000>,
823 <0x0 0x1f21e000 0x0 0x1000>,
824 <0x0 0x1f217000 0x0 0x1000>;
825 interrupts = <0x0 0x86 0x4>;
828 clocks = <&sata01clk 0>;
830 phy-names = "sata-phy";
833 sata2: sata@1a400000 {
834 compatible = "apm,xgene-ahci";
835 reg = <0x0 0x1a400000 0x0 0x1000>,
836 <0x0 0x1f220000 0x0 0x1000>,
837 <0x0 0x1f22d000 0x0 0x1000>,
838 <0x0 0x1f22e000 0x0 0x1000>,
839 <0x0 0x1f227000 0x0 0x1000>;
840 interrupts = <0x0 0x87 0x4>;
843 clocks = <&sata23clk 0>;
845 phy-names = "sata-phy";
848 sata3: sata@1a800000 {
849 compatible = "apm,xgene-ahci";
850 reg = <0x0 0x1a800000 0x0 0x1000>,
851 <0x0 0x1f230000 0x0 0x1000>,
852 <0x0 0x1f23d000 0x0 0x1000>,
853 <0x0 0x1f23e000 0x0 0x1000>;
854 interrupts = <0x0 0x88 0x4>;
857 clocks = <&sata45clk 0>;
859 phy-names = "sata-phy";
862 /* Do not change dwusb name, coded for backward compatibility */
863 usb0: dwusb@19000000 {
865 compatible = "snps,dwc3";
866 reg = <0x0 0x19000000 0x0 0x100000>;
867 interrupts = <0x0 0x89 0x4>;
872 usb1: dwusb@19800000 {
874 compatible = "snps,dwc3";
875 reg = <0x0 0x19800000 0x0 0x100000>;
876 interrupts = <0x0 0x8a 0x4>;
881 sbgpio: gpio@17001000{
882 compatible = "apm,xgene-gpio-sb";
883 reg = <0x0 0x17001000 0x0 0x400>;
886 interrupts = <0x0 0x28 0x1>,
895 compatible = "apm,xgene-rtc";
896 reg = <0x0 0x10510000 0x0 0x400>;
897 interrupts = <0x0 0x46 0x4>;
899 clocks = <&rtcclk 0>;
902 menet: ethernet@17020000 {
903 compatible = "apm,xgene-enet";
905 reg = <0x0 0x17020000 0x0 0xd100>,
906 <0x0 0X17030000 0x0 0Xc300>,
907 <0x0 0X10000000 0x0 0X200>;
908 reg-names = "enet_csr", "ring_csr", "ring_cmd";
909 interrupts = <0x0 0x3c 0x4>;
911 clocks = <&menetclk 0>;
912 /* mac address will be overwritten by the bootloader */
913 local-mac-address = [00 00 00 00 00 00];
914 phy-connection-type = "rgmii";
915 phy-handle = <&menetphy>;
917 compatible = "apm,xgene-mdio";
918 #address-cells = <1>;
920 menetphy: menetphy@3 {
921 compatible = "ethernet-phy-id001c.c915";
928 sgenet0: ethernet@1f210000 {
929 compatible = "apm,xgene1-sgenet";
931 reg = <0x0 0x1f210000 0x0 0xd100>,
932 <0x0 0x1f200000 0x0 0Xc300>,
933 <0x0 0x1B000000 0x0 0X200>;
934 reg-names = "enet_csr", "ring_csr", "ring_cmd";
935 interrupts = <0x0 0xA0 0x4>,
938 clocks = <&sge0clk 0>;
939 local-mac-address = [00 00 00 00 00 00];
940 phy-connection-type = "sgmii";
943 sgenet1: ethernet@1f210030 {
944 compatible = "apm,xgene1-sgenet";
946 reg = <0x0 0x1f210030 0x0 0xd100>,
947 <0x0 0x1f200000 0x0 0Xc300>,
948 <0x0 0x1B000000 0x0 0X8000>;
949 reg-names = "enet_csr", "ring_csr", "ring_cmd";
950 interrupts = <0x0 0xAC 0x4>,
954 clocks = <&sge1clk 0>;
955 local-mac-address = [00 00 00 00 00 00];
956 phy-connection-type = "sgmii";
959 xgenet: ethernet@1f610000 {
960 compatible = "apm,xgene1-xgenet";
962 reg = <0x0 0x1f610000 0x0 0xd100>,
963 <0x0 0x1f600000 0x0 0Xc300>,
964 <0x0 0x18000000 0x0 0X200>;
965 reg-names = "enet_csr", "ring_csr", "ring_cmd";
966 interrupts = <0x0 0x60 0x4>,
975 clocks = <&xge0clk 0>;
976 /* mac address will be overwritten by the bootloader */
977 local-mac-address = [00 00 00 00 00 00];
978 phy-connection-type = "xgmii";
981 xgenet1: ethernet@1f620000 {
982 compatible = "apm,xgene1-xgenet";
984 reg = <0x0 0x1f620000 0x0 0xd100>,
985 <0x0 0x1f600000 0x0 0Xc300>,
986 <0x0 0x18000000 0x0 0X8000>;
987 reg-names = "enet_csr", "ring_csr", "ring_cmd";
988 interrupts = <0x0 0x6C 0x4>,
992 clocks = <&xge1clk 0>;
993 /* mac address will be overwritten by the bootloader */
994 local-mac-address = [00 00 00 00 00 00];
995 phy-connection-type = "xgmii";
999 compatible = "apm,xgene-rng";
1000 reg = <0x0 0x10520000 0x0 0x100>;
1001 interrupts = <0x0 0x41 0x4>;
1002 clocks = <&rngpkaclk 0>;
1006 compatible = "apm,xgene-storm-dma";
1007 device_type = "dma";
1008 reg = <0x0 0x1f270000 0x0 0x10000>,
1009 <0x0 0x1f200000 0x0 0x10000>,
1010 <0x0 0x1b000000 0x0 0x400000>,
1011 <0x0 0x1054a000 0x0 0x100>;
1012 interrupts = <0x0 0x82 0x4>,
1018 clocks = <&dmaclk 0>;