arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2019 BayLibre, SAS
   4  * Author: Neil Armstrong <narmstrong@baylibre.com>
   5  */
   6
   7 /dts-v1/;
   8
   9 #include "meson-sm1.dtsi"
  10 #include "meson-khadas-vim3.dtsi"
  11 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
  12
  13 / {
  14         compatible = "khadas,vim3l", "amlogic,sm1";
  15         model = "Khadas VIM3L";
  16
  17         vddcpu: regulator-vddcpu {
  18                 /*
  19                  * Silergy SY8030DEC Regulator.
  20                  */
  21                 compatible = "pwm-regulator";
  22
  23                 regulator-name = "VDDCPU";
  24                 regulator-min-microvolt = <690000>;
  25                 regulator-max-microvolt = <1050000>;
  26
  27                 vin-supply = <&vsys_3v3>;
  28
  29                 pwms = <&pwm_AO_cd 1 1250 0>;
  30                 pwm-dutycycle-range = <100 0>;
  31
  32                 regulator-boot-on;
  33                 regulator-always-on;
  34         };
  35 };
  36
  37 &cpu0 {
  38         cpu-supply = <&vddcpu>;
  39         operating-points-v2 = <&cpu_opp_table>;
  40         clocks = <&clkc CLKID_CPU_CLK>;
  41         clock-latency = <50000>;
  42 };
  43
  44 &cpu1 {
  45         cpu-supply = <&vddcpu>;
  46         operating-points-v2 = <&cpu_opp_table>;
  47         clocks = <&clkc CLKID_CPU1_CLK>;
  48         clock-latency = <50000>;
  49 };
  50
  51 &cpu2 {
  52         cpu-supply = <&vddcpu>;
  53         operating-points-v2 = <&cpu_opp_table>;
  54         clocks = <&clkc CLKID_CPU2_CLK>;
  55         clock-latency = <50000>;
  56 };
  57
  58 &cpu3 {
  59         cpu-supply = <&vddcpu>;
  60         operating-points-v2 = <&cpu_opp_table>;
  61         clocks = <&clkc CLKID_CPU3_CLK>;
  62         clock-latency = <50000>;
  63 };
  64
  65 &pwm_AO_cd {
  66         pinctrl-0 = <&pwm_ao_d_e_pins>;
  67         pinctrl-names = "default";
  68         clocks = <&xtal>;
  69         clock-names = "clkin1";
  70         status = "okay";
  71 };
  72
  73 /*
  74  * The VIM3 on-board  MCU can mux the PCIe/USB3.0 shared differential
  75  * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
  76  * an USB3.0 Type A connector and a M.2 Key M slot.
  77  * The PHY driving these differential lines is shared between
  78  * the USB3.0 controller and the PCIe Controller, thus only
  79  * a single controller can use it.
  80  * If the MCU is configured to mux the PCIe/USB3.0 differential lines
  81  * to the M.2 Key M slot, uncomment the following block to disable
  82  * USB3.0 from the USB Complex and enable the PCIe controller.
  83  * The End User is not expected to uncomment the following except for
  84  * testing purposes, but instead rely on the firmware/bootloader to
  85  * update these nodes accordingly if PCIe mode is selected by the MCU.
  86  */
  87 /*
  88 &pcie {
  89         status = "okay";
  90 };
  91
  92 &usb {
  93         phys = <&usb2_phy0>, <&usb2_phy1>;
  94         phy-names = "usb2-phy0", "usb2-phy1";
  95 };
  96  */
  97
  98 &sd_emmc_a {
  99         sd-uhs-sdr50;
 100 };