1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016 Endless Computers, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
7 #include "meson-gx.dtsi"
8 #include <dt-bindings/clock/gxbb-clkc.h>
9 #include <dt-bindings/clock/gxbb-aoclkc.h>
10 #include <dt-bindings/gpio/meson-gxl-gpio.h>
11 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
14 compatible = "amlogic,meson-gxl";
18 compatible = "amlogic,meson-gxl-usb-ctrl";
19 reg = <0x0 0xd0078080 0x0 0x20>;
20 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
25 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
26 clock-names = "usb_ctrl", "ddr";
27 resets = <&reset RESET_USB_OTG>;
31 phys = <&usb2_phy0>, <&usb2_phy1>;
32 phy-names = "usb2-phy0", "usb2-phy1";
35 compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
36 reg = <0x0 0xc9100000 0x0 0x40000>;
37 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
38 clocks = <&clkc CLKID_USB1>;
41 dr_mode = "peripheral";
42 g-rx-fifo-size = <192>;
43 g-np-tx-fifo-size = <128>;
44 g-tx-fifo-size = <128 128 16 16 16>;
48 compatible = "snps,dwc3";
49 reg = <0x0 0xc9000000 0x0 0x100000>;
50 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
52 maximum-speed = "high-speed";
53 snps,dis_u2_susphy_quirk;
57 acodec: audio-controller@c8832000 {
58 compatible = "amlogic,t9015";
59 reg = <0x0 0xc8832000 0x0 0x14>;
60 #sound-dai-cells = <0>;
61 sound-name-prefix = "ACODEC";
62 clocks = <&clkc CLKID_ACODEC>;
64 resets = <&reset RESET_ACODEC>;
68 crypto: crypto@c883e000 {
69 compatible = "amlogic,gxl-crypto";
70 reg = <0x0 0xc883e000 0x0 0x36>;
71 interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
72 <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
73 clocks = <&clkc CLKID_BLKMV>;
74 clock-names = "blkmv";
81 compatible = "amlogic,aiu-gxl", "amlogic,aiu";
82 clocks = <&clkc CLKID_AIU_GLUE>,
83 <&clkc CLKID_I2S_OUT>,
84 <&clkc CLKID_AOCLK_GATE>,
85 <&clkc CLKID_CTS_AMCLK>,
86 <&clkc CLKID_MIXER_IFACE>,
88 <&clkc CLKID_IEC958_GATE>,
89 <&clkc CLKID_CTS_MCLK_I958>,
90 <&clkc CLKID_CTS_I958>;
100 resets = <&reset RESET_AIU>;
104 usb2_phy0: phy@78000 {
105 compatible = "amlogic,meson-gxl-usb2-phy";
107 reg = <0x0 0x78000 0x0 0x20>;
108 clocks = <&clkc CLKID_USB>;
110 resets = <&reset RESET_USB_OTG>;
115 usb2_phy1: phy@78020 {
116 compatible = "amlogic,meson-gxl-usb2-phy";
118 reg = <0x0 0x78020 0x0 0x20>;
119 clocks = <&clkc CLKID_USB>;
121 resets = <&reset RESET_USB_OTG>;
128 clocks = <&clkc CLKID_EFUSE>;
132 clocks = <&clkc CLKID_ETH>,
133 <&clkc CLKID_FCLK_DIV2>,
135 clock-names = "stmmaceth", "clkin0", "clkin1";
138 #address-cells = <1>;
140 compatible = "snps,dwmac-mdio";
145 pinctrl_aobus: pinctrl@14 {
146 compatible = "amlogic,meson-gxl-aobus-pinctrl";
147 #address-cells = <2>;
152 reg = <0x0 0x00014 0x0 0x8>,
153 <0x0 0x0002c 0x0 0x4>,
154 <0x0 0x00024 0x0 0x8>;
155 reg-names = "mux", "pull", "gpio";
158 gpio-ranges = <&pinctrl_aobus 0 0 14>;
161 uart_ao_a_pins: uart_ao_a {
163 groups = "uart_tx_ao_a", "uart_rx_ao_a";
164 function = "uart_ao";
169 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
171 groups = "uart_cts_ao_a",
173 function = "uart_ao";
178 uart_ao_b_pins: uart_ao_b {
180 groups = "uart_tx_ao_b", "uart_rx_ao_b";
181 function = "uart_ao_b";
186 uart_ao_b_0_1_pins: uart_ao_b_0_1 {
188 groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
189 function = "uart_ao_b";
194 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
196 groups = "uart_cts_ao_b",
198 function = "uart_ao_b";
203 remote_input_ao_pins: remote_input_ao {
205 groups = "remote_input_ao";
206 function = "remote_input_ao";
211 i2c_ao_pins: i2c_ao {
213 groups = "i2c_sck_ao",
220 pwm_ao_a_3_pins: pwm_ao_a_3 {
222 groups = "pwm_ao_a_3";
223 function = "pwm_ao_a";
228 pwm_ao_a_8_pins: pwm_ao_a_8 {
230 groups = "pwm_ao_a_8";
231 function = "pwm_ao_a";
236 pwm_ao_b_pins: pwm_ao_b {
239 function = "pwm_ao_b";
244 pwm_ao_b_6_pins: pwm_ao_b_6 {
246 groups = "pwm_ao_b_6";
247 function = "pwm_ao_b";
252 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
254 groups = "i2s_out_ch23_ao";
255 function = "i2s_out_ao";
260 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
262 groups = "i2s_out_ch45_ao";
263 function = "i2s_out_ao";
268 spdif_out_ao_6_pins: spdif_out_ao_6 {
270 groups = "spdif_out_ao_6";
271 function = "spdif_out_ao";
276 spdif_out_ao_9_pins: spdif_out_ao_9 {
278 groups = "spdif_out_ao_9";
279 function = "spdif_out_ao";
284 ao_cec_pins: ao_cec {
292 ee_cec_pins: ee_cec {
303 clocks = <&clkc_AO CLKID_AO_CEC_32K>;
304 clock-names = "core";
308 compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
309 clocks = <&xtal>, <&clkc CLKID_CLK81>;
310 clock-names = "xtal", "mpeg-clk";
314 compatible = "amlogic,meson-gpio-intc",
315 "amlogic,meson-gxl-gpio-intc";
320 compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
321 resets = <&reset RESET_HDMITX_CAPB3>,
322 <&reset RESET_HDMI_SYSTEM_RESET>,
323 <&reset RESET_HDMI_TX>;
324 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
325 clocks = <&clkc CLKID_HDMI_PCLK>,
327 <&clkc CLKID_GCLK_VENCI_INT0>;
328 clock-names = "isfr", "iahb", "venci";
332 clkc: clock-controller {
333 compatible = "amlogic,gxl-clkc";
336 clock-names = "xtal";
341 clocks = <&clkc CLKID_I2C>;
345 clocks = <&clkc CLKID_AO_I2C>;
349 clocks = <&clkc CLKID_I2C>;
353 clocks = <&clkc CLKID_I2C>;
357 pinctrl_periphs: pinctrl@4b0 {
358 compatible = "amlogic,meson-gxl-periphs-pinctrl";
359 #address-cells = <2>;
364 reg = <0x0 0x004b0 0x0 0x28>,
365 <0x0 0x004e8 0x0 0x14>,
366 <0x0 0x00520 0x0 0x14>,
367 <0x0 0x00430 0x0 0x40>;
368 reg-names = "mux", "pull", "pull-enable", "gpio";
371 gpio-ranges = <&pinctrl_periphs 0 0 100>;
376 groups = "emmc_nand_d07",
389 emmc_ds_pins: emmc-ds {
397 emmc_clk_gate_pins: emmc_clk_gate {
400 function = "gpio_periphs";
426 spi_ss0_pins: spi-ss0 {
434 sdcard_pins: sdcard {
436 groups = "sdcard_d0",
446 groups = "sdcard_clk";
452 sdcard_clk_gate_pins: sdcard_clk_gate {
455 function = "gpio_periphs";
478 sdio_clk_gate_pins: sdio_clk_gate {
481 function = "gpio_periphs";
486 sdio_irq_pins: sdio_irq {
494 uart_a_pins: uart_a {
496 groups = "uart_tx_a",
503 uart_a_cts_rts_pins: uart_a_cts_rts {
505 groups = "uart_cts_a",
512 uart_b_pins: uart_b {
514 groups = "uart_tx_b",
521 uart_b_cts_rts_pins: uart_b_cts_rts {
523 groups = "uart_cts_b",
530 uart_c_pins: uart_c {
532 groups = "uart_tx_c",
539 uart_c_cts_rts_pins: uart_c_cts_rts {
541 groups = "uart_cts_c",
550 groups = "i2c_sck_a",
559 groups = "i2c_sck_b",
568 groups = "i2c_sck_c",
575 i2c_c_dv18_pins: i2c_c_dv18 {
577 groups = "i2c_sck_c_dv19",
605 eth_link_led_pins: eth_link_led {
607 groups = "eth_link_led";
608 function = "eth_led";
613 eth_act_led_pins: eth_act_led {
615 groups = "eth_act_led";
616 function = "eth_led";
660 pwm_f_clk_pins: pwm_f_clk {
662 groups = "pwm_f_clk";
668 pwm_f_x_pins: pwm_f_x {
676 hdmi_hpd_pins: hdmi_hpd {
679 function = "hdmi_hpd";
684 hdmi_i2c_pins: hdmi_i2c {
686 groups = "hdmi_sda", "hdmi_scl";
687 function = "hdmi_i2c";
692 i2s_am_clk_pins: i2s_am_clk {
694 groups = "i2s_am_clk";
695 function = "i2s_out";
700 i2s_out_ao_clk_pins: i2s_out_ao_clk {
702 groups = "i2s_out_ao_clk";
703 function = "i2s_out";
708 i2s_out_lr_clk_pins: i2s_out_lr_clk {
710 groups = "i2s_out_lr_clk";
711 function = "i2s_out";
716 i2s_out_ch01_pins: i2s_out_ch01 {
718 groups = "i2s_out_ch01";
719 function = "i2s_out";
723 i2sout_ch23_z_pins: i2sout_ch23_z {
725 groups = "i2sout_ch23_z";
726 function = "i2s_out";
731 i2sout_ch45_z_pins: i2sout_ch45_z {
733 groups = "i2sout_ch45_z";
734 function = "i2s_out";
739 i2sout_ch67_z_pins: i2sout_ch67_z {
741 groups = "i2sout_ch67_z";
742 function = "i2s_out";
747 spdif_out_h_pins: spdif_out_ao_h {
749 groups = "spdif_out_h";
750 function = "spdif_out";
757 compatible = "mdio-mux-mmioreg", "mdio-mux";
758 #address-cells = <1>;
760 reg = <0x0 0x55c 0x0 0x4>;
761 mux-mask = <0xffffffff>;
762 mdio-parent-bus = <&mdio0>;
764 internal_mdio: mdio@e40908ff {
766 #address-cells = <1>;
769 internal_phy: ethernet-phy@8 {
770 compatible = "ethernet-phy-id0181.4400";
771 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
777 external_mdio: mdio@2009087f {
779 #address-cells = <1>;
786 resets = <&reset RESET_VIU>,
788 <&reset RESET_VCBUS>,
789 <&reset RESET_BT656>,
790 <&reset RESET_DVIN_RESET>,
792 <&reset RESET_VENCI>,
793 <&reset RESET_VENCP>,
796 <&reset RESET_VENCL>,
797 <&reset RESET_VID_LOCK>;
798 clocks = <&clkc CLKID_VPU>,
800 clock-names = "vpu", "vapb";
802 * VPU clocking is provided by two identical clock paths
803 * VPU_0 and VPU_1 muxed to a single clock by a glitch
804 * free mux to safely change frequency while running.
805 * Same for VAPB but with a final gate after the glitch free mux.
807 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
809 <&clkc CLKID_VPU>, /* Glitch free mux */
810 <&clkc CLKID_VAPB_0_SEL>,
811 <&clkc CLKID_VAPB_0>,
812 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
813 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
814 <0>, /* Do Nothing */
816 <&clkc CLKID_FCLK_DIV4>,
817 <0>, /* Do Nothing */
818 <&clkc CLKID_VAPB_0>;
819 assigned-clock-rates = <0>, /* Do Nothing */
821 <0>, /* Do Nothing */
822 <0>, /* Do Nothing */
824 <0>; /* Do Nothing */
828 compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
830 <&clkc CLKID_SAR_ADC>,
831 <&clkc CLKID_SAR_ADC_CLK>,
832 <&clkc CLKID_SAR_ADC_SEL>;
833 clock-names = "clkin", "core", "adc_clk", "adc_sel";
837 clocks = <&clkc CLKID_SD_EMMC_A>,
838 <&clkc CLKID_SD_EMMC_A_CLK0>,
839 <&clkc CLKID_FCLK_DIV2>;
840 clock-names = "core", "clkin0", "clkin1";
841 resets = <&reset RESET_SD_EMMC_A>;
845 clocks = <&clkc CLKID_SD_EMMC_B>,
846 <&clkc CLKID_SD_EMMC_B_CLK0>,
847 <&clkc CLKID_FCLK_DIV2>;
848 clock-names = "core", "clkin0", "clkin1";
849 resets = <&reset RESET_SD_EMMC_B>;
853 clocks = <&clkc CLKID_SD_EMMC_C>,
854 <&clkc CLKID_SD_EMMC_C_CLK0>,
855 <&clkc CLKID_FCLK_DIV2>;
856 clock-names = "core", "clkin0", "clkin1";
857 resets = <&reset RESET_SD_EMMC_C>;
861 clocks = <&clkc CLKID_HDMI_PCLK>,
863 <&clkc CLKID_GCLK_VENCI_INT0>;
867 clocks = <&clkc CLKID_SPICC>;
868 clock-names = "core";
869 resets = <&reset RESET_PERIPHS_SPICC>;
874 clocks = <&clkc CLKID_SPI>;
878 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
879 clock-names = "xtal", "pclk", "baud";
883 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
884 clock-names = "xtal", "pclk", "baud";
888 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
889 clock-names = "xtal", "pclk", "baud";
893 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
894 clock-names = "xtal", "pclk", "baud";
898 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
899 clock-names = "xtal", "pclk", "baud";
903 compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
904 power-domains = <&pwrc_vpu>;
908 compatible = "amlogic,gxl-vdec", "amlogic,gx-vdec";
909 clocks = <&clkc CLKID_DOS_PARSER>,
911 <&clkc CLKID_VDEC_1>,
912 <&clkc CLKID_VDEC_HEVC>;
913 clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
914 resets = <&reset RESET_PARSER>;
915 reset-names = "esparser";