arch/arm64/boot/dts/amlogic/meson-g12a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/clock/g12a-clkc.h>
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10
  11 / {
  12         compatible = "amlogic,g12a";
  13
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         cpus {
  19                 #address-cells = <0x2>;
  20                 #size-cells = <0x0>;
  21
  22                 cpu0: cpu@0 {
  23                         device_type = "cpu";
  24                         compatible = "arm,cortex-a53";
  25                         reg = <0x0 0x0>;
  26                         enable-method = "psci";
  27                         next-level-cache = <&l2>;
  28                 };
  29
  30                 cpu1: cpu@1 {
  31                         device_type = "cpu";
  32                         compatible = "arm,cortex-a53";
  33                         reg = <0x0 0x1>;
  34                         enable-method = "psci";
  35                         next-level-cache = <&l2>;
  36                 };
  37
  38                 cpu2: cpu@2 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a53";
  41                         reg = <0x0 0x2>;
  42                         enable-method = "psci";
  43                         next-level-cache = <&l2>;
  44                 };
  45
  46                 cpu3: cpu@3 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a53";
  49                         reg = <0x0 0x3>;
  50                         enable-method = "psci";
  51                         next-level-cache = <&l2>;
  52                 };
  53
  54                 l2: l2-cache0 {
  55                         compatible = "cache";
  56                 };
  57         };
  58
  59         efuse: efuse {
  60                 compatible = "amlogic,meson-gxbb-efuse";
  61                 clocks = <&clkc CLKID_EFUSE>;
  62                 #address-cells = <1>;
  63                 #size-cells = <1>;
  64                 read-only;
  65         };
  66
  67         psci {
  68                 compatible = "arm,psci-1.0";
  69                 method = "smc";
  70         };
  71
  72         reserved-memory {
  73                 #address-cells = <2>;
  74                 #size-cells = <2>;
  75                 ranges;
  76
  77                 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */
  78                 secmon_reserved: secmon@5000000 {
  79                         reg = <0x0 0x05000000 0x0 0x300000>;
  80                         no-map;
  81                 };
  82         };
  83
  84         sm: secure-monitor {
  85                 compatible = "amlogic,meson-gxbb-sm";
  86         };
  87
  88         soc {
  89                 compatible = "simple-bus";
  90                 #address-cells = <2>;
  91                 #size-cells = <2>;
  92                 ranges;
  93
  94                 apb: bus@ff600000 {
  95                         compatible = "simple-bus";
  96                         reg = <0x0 0xff600000 0x0 0x200000>;
  97                         #address-cells = <2>;
  98                         #size-cells = <2>;
  99                         ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
 100
 101                         periphs: bus@34400 {
 102                                 compatible = "simple-bus";
 103                                 reg = <0x0 0x34400 0x0 0x400>;
 104                                 #address-cells = <2>;
 105                                 #size-cells = <2>;
 106                                 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
 107                         };
 108
 109                         hiu: bus@3c000 {
 110                                 compatible = "simple-bus";
 111                                 reg = <0x0 0x3c000 0x0 0x1400>;
 112                                 #address-cells = <2>;
 113                                 #size-cells = <2>;
 114                                 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
 115
 116                                 hhi: system-controller@0 {
 117                                         compatible = "amlogic,meson-gx-hhi-sysctrl",
 118                                                      "simple-mfd", "syscon";
 119                                         reg = <0 0 0 0x400>;
 120
 121                                         clkc: clock-controller {
 122                                                 compatible = "amlogic,g12a-clkc";
 123                                                 #clock-cells = <1>;
 124                                                 clocks = <&xtal>;
 125                                                 clock-names = "xtal";
 126                                         };
 127                                 };
 128                         };
 129                 };
 130
 131                 aobus: bus@ff800000 {
 132                         compatible = "simple-bus";
 133                         reg = <0x0 0xff800000 0x0 0x100000>;
 134                         #address-cells = <2>;
 135                         #size-cells = <2>;
 136                         ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
 137
 138                         rti: sys-ctrl@0 {
 139                                 compatible = "amlogic,meson-gx-ao-sysctrl",
 140                                              "simple-mfd", "syscon";
 141                                 reg = <0x0 0x0 0x0 0x100>;
 142                                 #address-cells = <2>;
 143                                 #size-cells = <2>;
 144                                 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
 145
 146                                 clkc_AO: clock-controller {
 147                                         compatible = "amlogic,meson-g12a-aoclkc";
 148                                         #clock-cells = <1>;
 149                                         #reset-cells = <1>;
 150                                         clocks = <&xtal>, <&clkc CLKID_CLK81>;
 151                                         clock-names = "xtal", "mpeg-clk";
 152                                 };
 153                         };
 154
 155                         sec_AO: ao-secure@140 {
 156                                 compatible = "amlogic,meson-gx-ao-secure", "syscon";
 157                                 reg = <0x0 0x140 0x0 0x140>;
 158                                 amlogic,has-chip-id;
 159                         };
 160
 161                         uart_AO: serial@3000 {
 162                                 compatible = "amlogic,meson-gx-uart",
 163                                              "amlogic,meson-ao-uart";
 164                                 reg = <0x0 0x3000 0x0 0x18>;
 165                                 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
 166                                 clocks = <&xtal>, <&xtal>, <&xtal>;
 167                                 clock-names = "xtal", "pclk", "baud";
 168                                 status = "disabled";
 169                         };
 170
 171                         uart_AO_B: serial@4000 {
 172                                 compatible = "amlogic,meson-gx-uart",
 173                                              "amlogic,meson-ao-uart";
 174                                 reg = <0x0 0x4000 0x0 0x18>;
 175                                 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
 176                                 clocks = <&xtal>, <&xtal>, <&xtal>;
 177                                 clock-names = "xtal", "pclk", "baud";
 178                                 status = "disabled";
 179                         };
 180                 };
 181
 182                 gic: interrupt-controller@ffc01000 {
 183                         compatible = "arm,gic-400";
 184                         reg = <0x0 0xffc01000 0 0x1000>,
 185                               <0x0 0xffc02000 0 0x2000>,
 186                               <0x0 0xffc04000 0 0x2000>,
 187                               <0x0 0xffc06000 0 0x2000>;
 188                         interrupt-controller;
 189                         interrupts = <GIC_PPI 9
 190                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 191                         #interrupt-cells = <3>;
 192                         #address-cells = <0>;
 193                 };
 194
 195                 cbus: bus@ffd00000 {
 196                         compatible = "simple-bus";
 197                         reg = <0x0 0xffd00000 0x0 0x100000>;
 198                         #address-cells = <2>;
 199                         #size-cells = <2>;
 200                         ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
 201
 202                         clk_msr: clock-measure@18000 {
 203                                 compatible = "amlogic,meson-g12a-clk-measure";
 204                                 reg = <0x0 0x18000 0x0 0x10>;
 205                         };
 206                 };
 207         };
 208
 209         timer {
 210                 compatible = "arm,armv8-timer";
 211                 interrupts = <GIC_PPI 13
 212                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
 213                              <GIC_PPI 14
 214                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
 215                              <GIC_PPI 11
 216                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
 217                              <GIC_PPI 10
 218                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
 219         };
 220
 221         xtal: xtal-clk {
 222                 compatible = "fixed-clock";
 223                 clock-frequency = <24000000>;
 224                 clock-output-names = "xtal";
 225                 #clock-cells = <0>;
 226         };
 227
 228 };