1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/axg-clkc.h>
10 #include <dt-bindings/clock/axg-aoclkc.h>
11 #include <dt-bindings/gpio/meson-axg-gpio.h>
12 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
15 compatible = "amlogic,meson-axg";
17 interrupt-parent = <&gic>;
26 /* 16 MiB reserved for Hardware ROM Firmware */
27 hwrom_reserved: hwrom@0 {
28 reg = <0x0 0x0 0x0 0x1000000>;
32 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
33 secmon_reserved: secmon@5000000 {
34 reg = <0x0 0x05000000 0x0 0x300000>;
40 #address-cells = <0x2>;
45 compatible = "arm,cortex-a53", "arm,armv8";
47 enable-method = "psci";
48 next-level-cache = <&l2>;
53 compatible = "arm,cortex-a53", "arm,armv8";
55 enable-method = "psci";
56 next-level-cache = <&l2>;
61 compatible = "arm,cortex-a53", "arm,armv8";
63 enable-method = "psci";
64 next-level-cache = <&l2>;
69 compatible = "arm,cortex-a53", "arm,armv8";
71 enable-method = "psci";
72 next-level-cache = <&l2>;
81 compatible = "arm,cortex-a53-pmu";
82 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
86 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
90 compatible = "arm,psci-1.0";
95 compatible = "arm,armv8-timer";
96 interrupts = <GIC_PPI 13
97 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
99 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
101 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
103 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
107 compatible = "fixed-clock";
108 clock-frequency = <24000000>;
109 clock-output-names = "xtal";
113 ao_alt_xtal: ao_alt_xtal-clk {
114 compatible = "fixed-clock";
115 clock-frequency = <32000000>;
116 clock-output-names = "ao_alt_xtal";
121 compatible = "simple-bus";
122 #address-cells = <2>;
127 compatible = "simple-bus";
128 reg = <0x0 0xffe00000 0x0 0x200000>;
129 #address-cells = <2>;
131 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
134 compatible = "amlogic,meson-axg-mmc";
135 reg = <0x0 0x5000 0x0 0x2000>;
136 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
138 clocks = <&clkc CLKID_SD_EMMC_B>,
139 <&clkc CLKID_SD_EMMC_B_CLK0>,
140 <&clkc CLKID_FCLK_DIV2>;
141 clock-names = "core", "clkin0", "clkin1";
142 resets = <&reset RESET_SD_EMMC_B>;
145 sd_emmc_c: mmc@7000 {
146 compatible = "amlogic,meson-axg-mmc";
147 reg = <0x0 0x7000 0x0 0x2000>;
148 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
150 clocks = <&clkc CLKID_SD_EMMC_C>,
151 <&clkc CLKID_SD_EMMC_C_CLK0>,
152 <&clkc CLKID_FCLK_DIV2>;
153 clock-names = "core", "clkin0", "clkin1";
154 resets = <&reset RESET_SD_EMMC_C>;
159 compatible = "simple-bus";
160 reg = <0x0 0xffd00000 0x0 0x25000>;
161 #address-cells = <2>;
163 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
165 gpio_intc: interrupt-controller@f080 {
166 compatible = "amlogic,meson-gpio-intc";
167 reg = <0x0 0xf080 0x0 0x10>;
168 interrupt-controller;
169 #interrupt-cells = <2>;
170 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
175 compatible = "amlogic,meson-axg-ee-pwm";
176 reg = <0x0 0x1b000 0x0 0x20>;
182 compatible = "amlogic,meson-axg-ee-pwm";
183 reg = <0x0 0x1a000 0x0 0x20>;
188 reset: reset-controller@1004 {
189 compatible = "amlogic,meson-axg-reset";
190 reg = <0x0 0x01004 0x0 0x9c>;
195 compatible = "amlogic,meson-axg-spicc";
196 reg = <0x0 0x13000 0x0 0x3c>;
197 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
198 clocks = <&clkc CLKID_SPICC0>;
199 clock-names = "core";
200 #address-cells = <1>;
206 compatible = "amlogic,meson-axg-spicc";
207 reg = <0x0 0x15000 0x0 0x3c>;
208 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&clkc CLKID_SPICC1>;
210 clock-names = "core";
211 #address-cells = <1>;
217 compatible = "amlogic,meson-axg-i2c";
218 reg = <0x0 0x1f000 0x0 0x20>;
219 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
220 clocks = <&clkc CLKID_I2C>;
221 #address-cells = <1>;
227 compatible = "amlogic,meson-axg-i2c";
228 reg = <0x0 0x1e000 0x0 0x20>;
229 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
230 clocks = <&clkc CLKID_I2C>;
231 #address-cells = <1>;
237 compatible = "amlogic,meson-axg-i2c";
238 reg = <0x0 0x1d000 0x0 0x20>;
239 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
240 clocks = <&clkc CLKID_I2C>;
241 #address-cells = <1>;
247 compatible = "amlogic,meson-axg-i2c";
248 reg = <0x0 0x1c000 0x0 0x20>;
249 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
250 clocks = <&clkc CLKID_I2C>;
251 #address-cells = <1>;
256 uart_A: serial@24000 {
257 compatible = "amlogic,meson-gx-uart";
258 reg = <0x0 0x24000 0x0 0x18>;
259 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
261 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
262 clock-names = "xtal", "pclk", "baud";
265 uart_B: serial@23000 {
266 compatible = "amlogic,meson-gx-uart";
267 reg = <0x0 0x23000 0x0 0x18>;
268 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
270 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
271 clock-names = "xtal", "pclk", "baud";
275 ethmac: ethernet@ff3f0000 {
276 compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
277 reg = <0x0 0xff3f0000 0x0 0x10000
278 0x0 0xff634540 0x0 0x8>;
279 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
280 interrupt-names = "macirq";
281 clocks = <&clkc CLKID_ETH>,
282 <&clkc CLKID_FCLK_DIV2>,
284 clock-names = "stmmaceth", "clkin0", "clkin1";
288 gic: interrupt-controller@ffc01000 {
289 compatible = "arm,gic-400";
290 reg = <0x0 0xffc01000 0 0x1000>,
291 <0x0 0xffc02000 0 0x2000>,
292 <0x0 0xffc04000 0 0x2000>,
293 <0x0 0xffc06000 0 0x2000>;
294 interrupt-controller;
295 interrupts = <GIC_PPI 9
296 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
297 #interrupt-cells = <3>;
298 #address-cells = <0>;
301 hiubus: bus@ff63c000 {
302 compatible = "simple-bus";
303 reg = <0x0 0xff63c000 0x0 0x1c00>;
304 #address-cells = <2>;
306 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
308 sysctrl: system-controller@0 {
309 compatible = "amlogic,meson-axg-hhi-sysctrl", "syscon", "simple-mfd";
312 clkc: clock-controller {
313 compatible = "amlogic,axg-clkc";
319 mailbox: mailbox@ff63dc00 {
320 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
321 reg = <0 0xff63dc00 0 0x400>;
322 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
323 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
324 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
328 periphs: periphs@ff634000 {
329 compatible = "simple-bus";
330 reg = <0x0 0xff634000 0x0 0x2000>;
331 #address-cells = <2>;
333 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
336 compatible = "amlogic,meson-rng";
337 reg = <0x0 0x18 0x0 0x4>;
338 clocks = <&clkc CLKID_RNG0>;
339 clock-names = "core";
342 pinctrl_periphs: pinctrl@480 {
343 compatible = "amlogic,meson-axg-periphs-pinctrl";
344 #address-cells = <2>;
349 reg = <0x0 0x00480 0x0 0x40>,
350 <0x0 0x004e8 0x0 0x14>,
351 <0x0 0x00520 0x0 0x14>,
352 <0x0 0x00430 0x0 0x3c>;
353 reg-names = "mux", "pull", "pull-enable", "gpio";
356 gpio-ranges = <&pinctrl_periphs 0 0 86>;
361 groups = "emmc_nand_d0",
376 emmc_clk_gate_pins: emmc_clk_gate {
379 function = "gpio_periphs";
399 sdio_clk_gate_pins: sdio_clk_gate {
402 function = "gpio_periphs";
410 eth_rmii_x_pins: eth-x-rmii {
412 groups = "eth_mdio_x",
414 "eth_rgmii_rx_clk_x",
425 eth_rmii_y_pins: eth-y-rmii {
427 groups = "eth_mdio_y",
429 "eth_rgmii_rx_clk_y",
440 eth_rgmii_x_pins: eth-x-rgmii {
442 groups = "eth_mdio_x",
444 "eth_rgmii_rx_clk_x",
460 eth_rgmii_y_pins: eth-y-rgmii {
462 groups = "eth_mdio_y",
464 "eth_rgmii_rx_clk_y",
480 pwm_a_a_pins: pwm_a_a {
487 pwm_a_x18_pins: pwm_a_x18 {
489 groups = "pwm_a_x18";
494 pwm_a_x20_pins: pwm_a_x20 {
496 groups = "pwm_a_x20";
501 pwm_a_z_pins: pwm_a_z {
508 pwm_b_a_pins: pwm_b_a {
515 pwm_b_x_pins: pwm_b_x {
522 pwm_b_z_pins: pwm_b_z {
529 pwm_c_a_pins: pwm_c_a {
536 pwm_c_x10_pins: pwm_c_x10 {
538 groups = "pwm_c_x10";
543 pwm_c_x17_pins: pwm_c_x17 {
545 groups = "pwm_c_x17";
550 pwm_d_x11_pins: pwm_d_x11 {
552 groups = "pwm_d_x11";
557 pwm_d_x16_pins: pwm_d_x16 {
559 groups = "pwm_d_x16";
566 groups = "spi0_miso",
573 spi0_ss0_pins: spi0_ss0 {
580 spi0_ss1_pins: spi0_ss1 {
587 spi0_ss2_pins: spi0_ss2 {
595 spi1_a_pins: spi1_a {
597 groups = "spi1_miso_a",
604 spi1_ss0_a_pins: spi1_ss0_a {
606 groups = "spi1_ss0_a";
611 spi1_ss1_pins: spi1_ss1 {
618 spi1_x_pins: spi1_x {
620 groups = "spi1_miso_x",
627 spi1_ss0_x_pins: spi1_ss0_x {
629 groups = "spi1_ss0_x";
642 i2c1_z_pins: i2c1_z {
644 groups = "i2c1_sck_z",
650 i2c1_x_pins: i2c1_x {
652 groups = "i2c1_sck_x",
658 i2c2_x_pins: i2c2_x {
660 groups = "i2c2_sck_x",
666 i2c2_a_pins: i2c2_a {
668 groups = "i2c2_sck_a",
674 i2c3_a6_pins: i2c3_a6 {
676 groups = "i2c3_sda_a6",
682 i2c3_a12_pins: i2c3_a12 {
684 groups = "i2c3_sda_a12",
690 i2c3_a19_pins: i2c3_a19 {
692 groups = "i2c3_sda_a19",
698 uart_a_pins: uart_a {
700 groups = "uart_tx_a",
706 uart_a_cts_rts_pins: uart_a_cts_rts {
708 groups = "uart_cts_a",
714 uart_b_x_pins: uart_b_x {
716 groups = "uart_tx_b_x",
722 uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
724 groups = "uart_cts_b_x",
730 uart_b_z_pins: uart_b_z {
732 groups = "uart_tx_b_z",
738 uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
740 groups = "uart_cts_b_z",
746 uart_ao_b_z_pins: uart_ao_b_z {
748 groups = "uart_ao_tx_b_z",
750 function = "uart_ao_b_z";
754 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
756 groups = "uart_ao_cts_b_z",
758 function = "uart_ao_b_z";
762 mclk_b_pins: mclk_b {
769 mclk_c_pins: mclk_c {
776 tdma_sclk_pins: tdma_sclk {
778 groups = "tdma_sclk";
783 tdma_sclk_slv_pins: tdma_sclk_slv {
785 groups = "tdma_sclk_slv";
790 tdma_fs_pins: tdma_fs {
797 tdma_fs_slv_pins: tdma_fs_slv {
799 groups = "tdma_fs_slv";
804 tdma_din0_pins: tdma_din0 {
806 groups = "tdma_din0";
811 tdma_dout0_x14_pins: tdma_dout0_x14 {
813 groups = "tdma_dout0_x14";
818 tdma_dout0_x15_pins: tdma_dout0_x15 {
820 groups = "tdma_dout0_x15";
825 tdma_dout1_pins: tdma_dout1 {
827 groups = "tdma_dout1";
832 tdma_din1_pins: tdma_din1 {
834 groups = "tdma_din1";
839 tdmb_sclk_pins: tdmb_sclk {
841 groups = "tdmb_sclk";
846 tdmb_sclk_slv_pins: tdmb_sclk_slv {
848 groups = "tdmb_sclk_slv";
853 tdmb_fs_pins: tdmb_fs {
860 tdmb_fs_slv_pins: tdmb_fs_slv {
862 groups = "tdmb_fs_slv";
867 tdmb_din0_pins: tdmb_din0 {
869 groups = "tdmb_din0";
874 tdmb_dout0_pins: tdmb_dout0 {
876 groups = "tdmb_dout0";
881 tdmb_din1_pins: tdmb_din1 {
883 groups = "tdmb_din1";
888 tdmb_dout1_pins: tdmb_dout1 {
890 groups = "tdmb_dout1";
895 tdmb_din2_pins: tdmb_din2 {
897 groups = "tdmb_din2";
902 tdmb_dout2_pins: tdmb_dout2 {
904 groups = "tdmb_dout2";
909 tdmb_din3_pins: tdmb_din3 {
911 groups = "tdmb_din3";
916 tdmb_dout3_pins: tdmb_dout3 {
918 groups = "tdmb_dout3";
923 tdmc_sclk_pins: tdmc_sclk {
925 groups = "tdmc_sclk";
930 tdmc_sclk_slv_pins: tdmc_sclk_slv {
932 groups = "tdmc_sclk_slv";
937 tdmc_fs_pins: tdmc_fs {
944 tdmc_fs_slv_pins: tdmc_fs_slv {
946 groups = "tdmc_fs_slv";
951 tdmc_din0_pins: tdmc_din0 {
953 groups = "tdmc_din0";
958 tdmc_dout0_pins: tdmc_dout0 {
960 groups = "tdmc_dout0";
965 tdmc_din1_pins: tdmc_din1 {
967 groups = "tdmc_din1";
972 tdmc_dout1_pins: tdmc_dout1 {
974 groups = "tdmc_dout1";
979 tdmc_din2_pins: tdmc_din2 {
981 groups = "tdmc_din2";
986 tdmc_dout2_pins: tdmc_dout2 {
988 groups = "tdmc_dout2";
993 tdmc_din3_pins: tdmc_din3 {
995 groups = "tdmc_din3";
1000 tdmc_dout3_pins: tdmc_dout3 {
1002 groups = "tdmc_dout3";
1009 sram: sram@fffc0000 {
1010 compatible = "amlogic,meson-axg-sram", "mmio-sram";
1011 reg = <0x0 0xfffc0000 0x0 0x20000>;
1012 #address-cells = <1>;
1014 ranges = <0 0x0 0xfffc0000 0x20000>;
1016 cpu_scp_lpri: scp-shmem@0 {
1017 compatible = "amlogic,meson-axg-scp-shmem";
1018 reg = <0x13000 0x400>;
1021 cpu_scp_hpri: scp-shmem@200 {
1022 compatible = "amlogic,meson-axg-scp-shmem";
1023 reg = <0x13400 0x400>;
1027 aobus: bus@ff800000 {
1028 compatible = "simple-bus";
1029 reg = <0x0 0xff800000 0x0 0x100000>;
1030 #address-cells = <2>;
1032 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1034 sysctrl_AO: sys-ctrl@0 {
1035 compatible = "amlogic,meson-axg-ao-sysctrl", "syscon", "simple-mfd";
1036 reg = <0x0 0x0 0x0 0x100>;
1038 clkc_AO: clock-controller {
1039 compatible = "amlogic,meson-axg-aoclkc";
1045 pinctrl_aobus: pinctrl@14 {
1046 compatible = "amlogic,meson-axg-aobus-pinctrl";
1047 #address-cells = <2>;
1052 reg = <0x0 0x00014 0x0 0x8>,
1053 <0x0 0x0002c 0x0 0x4>,
1054 <0x0 0x00024 0x0 0x8>;
1055 reg-names = "mux", "pull", "gpio";
1058 gpio-ranges = <&pinctrl_aobus 0 0 15>;
1061 i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1063 groups = "i2c_ao_sck_4";
1064 function = "i2c_ao";
1068 i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1070 groups = "i2c_ao_sck_8";
1071 function = "i2c_ao";
1075 i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1077 groups = "i2c_ao_sck_10";
1078 function = "i2c_ao";
1082 i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1084 groups = "i2c_ao_sda_5";
1085 function = "i2c_ao";
1089 i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1091 groups = "i2c_ao_sda_9";
1092 function = "i2c_ao";
1096 i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1098 groups = "i2c_ao_sda_11";
1099 function = "i2c_ao";
1103 remote_input_ao_pins: remote_input_ao {
1105 groups = "remote_input_ao";
1106 function = "remote_input_ao";
1110 uart_ao_a_pins: uart_ao_a {
1112 groups = "uart_ao_tx_a",
1114 function = "uart_ao_a";
1118 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1120 groups = "uart_ao_cts_a",
1122 function = "uart_ao_a";
1126 uart_ao_b_pins: uart_ao_b {
1128 groups = "uart_ao_tx_b",
1130 function = "uart_ao_b";
1134 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1136 groups = "uart_ao_cts_b",
1138 function = "uart_ao_b";
1143 sec_AO: ao-secure@140 {
1144 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1145 reg = <0x0 0x140 0x0 0x140>;
1146 amlogic,has-chip-id;
1149 pwm_AO_ab: pwm@7000 {
1150 compatible = "amlogic,meson-axg-ao-pwm";
1151 reg = <0x0 0x07000 0x0 0x20>;
1153 status = "disabled";
1156 pwm_AO_cd: pwm@2000 {
1157 compatible = "amlogic,meson-axg-ao-pwm";
1158 reg = <0x0 0x02000 0x0 0x20>;
1160 status = "disabled";
1164 compatible = "amlogic,meson-axg-i2c";
1165 reg = <0x0 0x05000 0x0 0x20>;
1166 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1167 clocks = <&clkc CLKID_AO_I2C>;
1168 #address-cells = <1>;
1170 status = "disabled";
1173 uart_AO: serial@3000 {
1174 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1175 reg = <0x0 0x3000 0x0 0x18>;
1176 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1177 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1178 clock-names = "xtal", "pclk", "baud";
1179 status = "disabled";
1182 uart_AO_B: serial@4000 {
1183 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1184 reg = <0x0 0x4000 0x0 0x18>;
1185 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1186 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1187 clock-names = "xtal", "pclk", "baud";
1188 status = "disabled";
1192 compatible = "amlogic,meson-gxbb-ir";
1193 reg = <0x0 0x8000 0x0 0x20>;
1194 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1195 status = "disabled";