1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright Altera Corporation (C) 2015. All rights reserved.
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
21 service_reserved: svcbuffer@0 {
22 compatible = "shared-dma-pool";
23 reg = <0x0 0x0 0x0 0x1000000>;
34 compatible = "arm,cortex-a53";
36 enable-method = "psci";
41 compatible = "arm,cortex-a53";
43 enable-method = "psci";
48 compatible = "arm,cortex-a53";
50 enable-method = "psci";
55 compatible = "arm,cortex-a53";
57 enable-method = "psci";
63 compatible = "arm,armv8-pmuv3";
64 interrupts = <0 170 4>,
68 interrupt-affinity = <&cpu0>,
72 interrupt-parent = <&intc>;
76 compatible = "arm,psci-0.2";
82 compatible = "arm,armv8-timer";
83 interrupts = <1 13 0xf08>,
87 interrupt-parent = <&intc>;
90 intc: interrupt-controller@fffc1000 {
91 compatible = "arm,gic-400", "arm,cortex-a15-gic";
92 #interrupt-cells = <3>;
94 reg = <0x0 0xfffc1000 0x0 0x1000>,
95 <0x0 0xfffc2000 0x0 0x2000>,
96 <0x0 0xfffc4000 0x0 0x2000>,
97 <0x0 0xfffc6000 0x0 0x2000>;
101 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
103 compatible = "fixed-clock";
106 cb_intosc_ls_clk: cb-intosc-ls-clk {
108 compatible = "fixed-clock";
111 f2s_free_clk: f2s-free-clk {
113 compatible = "fixed-clock";
118 compatible = "fixed-clock";
123 compatible = "fixed-clock";
124 clock-frequency = <200000000>;
129 #address-cells = <1>;
131 compatible = "simple-bus";
133 interrupt-parent = <&intc>;
134 ranges = <0 0 0 0xffffffff>;
137 #address-cells = <0x2>;
139 compatible = "fpga-region";
140 fpga-mgr = <&fpga_mgr>;
143 clkmgr: clock-controller@ffd10000 {
144 compatible = "intel,stratix10-clkmgr";
145 reg = <0xffd10000 0x1000>;
149 gmac0: ethernet@ff800000 {
150 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
151 reg = <0xff800000 0x2000>;
152 interrupts = <0 90 4>;
153 interrupt-names = "macirq";
154 mac-address = [00 00 00 00 00 00];
155 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
156 reset-names = "stmmaceth", "ahb";
157 clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
158 clock-names = "stmmaceth", "ptp_ref";
159 tx-fifo-depth = <16384>;
160 rx-fifo-depth = <16384>;
161 snps,multicast-filter-bins = <256>;
163 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
167 gmac1: ethernet@ff802000 {
168 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
169 reg = <0xff802000 0x2000>;
170 interrupts = <0 91 4>;
171 interrupt-names = "macirq";
172 mac-address = [00 00 00 00 00 00];
173 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
174 reset-names = "stmmaceth", "ahb";
175 clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
176 clock-names = "stmmaceth", "ptp_ref";
177 tx-fifo-depth = <16384>;
178 rx-fifo-depth = <16384>;
179 snps,multicast-filter-bins = <256>;
181 altr,sysmgr-syscon = <&sysmgr 0x48 8>;
185 gmac2: ethernet@ff804000 {
186 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
187 reg = <0xff804000 0x2000>;
188 interrupts = <0 92 4>;
189 interrupt-names = "macirq";
190 mac-address = [00 00 00 00 00 00];
191 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
192 reset-names = "stmmaceth", "ahb";
193 clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
194 clock-names = "stmmaceth", "ptp_ref";
195 tx-fifo-depth = <16384>;
196 rx-fifo-depth = <16384>;
197 snps,multicast-filter-bins = <256>;
199 altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
203 gpio0: gpio@ffc03200 {
204 #address-cells = <1>;
206 compatible = "snps,dw-apb-gpio";
207 reg = <0xffc03200 0x100>;
208 resets = <&rst GPIO0_RESET>;
211 porta: gpio-controller@0 {
212 compatible = "snps,dw-apb-gpio-port";
217 interrupt-controller;
218 #interrupt-cells = <2>;
219 interrupts = <0 110 4>;
223 gpio1: gpio@ffc03300 {
224 #address-cells = <1>;
226 compatible = "snps,dw-apb-gpio";
227 reg = <0xffc03300 0x100>;
228 resets = <&rst GPIO1_RESET>;
231 portb: gpio-controller@0 {
232 compatible = "snps,dw-apb-gpio-port";
237 interrupt-controller;
238 #interrupt-cells = <2>;
239 interrupts = <0 111 4>;
244 #address-cells = <1>;
246 compatible = "snps,designware-i2c";
247 reg = <0xffc02800 0x100>;
248 interrupts = <0 103 4>;
249 resets = <&rst I2C0_RESET>;
250 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
255 #address-cells = <1>;
257 compatible = "snps,designware-i2c";
258 reg = <0xffc02900 0x100>;
259 interrupts = <0 104 4>;
260 resets = <&rst I2C1_RESET>;
261 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
266 #address-cells = <1>;
268 compatible = "snps,designware-i2c";
269 reg = <0xffc02a00 0x100>;
270 interrupts = <0 105 4>;
271 resets = <&rst I2C2_RESET>;
272 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
277 #address-cells = <1>;
279 compatible = "snps,designware-i2c";
280 reg = <0xffc02b00 0x100>;
281 interrupts = <0 106 4>;
282 resets = <&rst I2C3_RESET>;
283 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
288 #address-cells = <1>;
290 compatible = "snps,designware-i2c";
291 reg = <0xffc02c00 0x100>;
292 interrupts = <0 107 4>;
293 resets = <&rst I2C4_RESET>;
294 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
299 #address-cells = <1>;
301 compatible = "altr,socfpga-dw-mshc";
302 reg = <0xff808000 0x1000>;
303 interrupts = <0 96 4>;
304 fifo-depth = <0x400>;
305 resets = <&rst SDMMC_RESET>;
306 reset-names = "reset";
307 clocks = <&clkmgr STRATIX10_L4_MP_CLK>,
308 <&clkmgr STRATIX10_SDMMC_CLK>;
309 clock-names = "biu", "ciu";
311 altr,sysmgr-syscon = <&sysmgr 0x28 4>;
315 nand: nand-controller@ffb90000 {
316 #address-cells = <1>;
318 compatible = "altr,socfpga-denali-nand";
319 reg = <0xffb90000 0x10000>,
321 reg-names = "nand_data", "denali_reg";
322 interrupts = <0 97 4>;
323 clocks = <&clkmgr STRATIX10_NAND_CLK>,
324 <&clkmgr STRATIX10_NAND_X_CLK>,
325 <&clkmgr STRATIX10_NAND_ECC_CLK>;
326 clock-names = "nand", "nand_x", "ecc";
327 resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
331 ocram: sram@ffe00000 {
332 compatible = "mmio-sram";
333 reg = <0xffe00000 0x100000>;
334 #address-cells = <1>;
336 ranges = <0 0xffe00000 0x100000>;
339 pdma: dma-controller@ffda0000 {
340 compatible = "arm,pl330", "arm,primecell";
341 reg = <0xffda0000 0x1000>;
342 interrupts = <0 81 4>,
352 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
353 clock-names = "apb_pclk";
354 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
355 reset-names = "dma", "dma-ocp";
358 pinctrl0: pinctrl@ffd13000 {
359 compatible = "pinctrl-single";
360 reg = <0xffd13000 0xA0>;
361 #pinctrl-cells = <1>;
362 pinctrl-single,register-width = <32>;
363 pinctrl-single,function-mask = <0x0000000f>;
366 pinctrl1: pinctrl@ffd13100 {
367 compatible = "pinctrl-single";
368 reg = <0xffd13100 0x20>;
369 #pinctrl-cells = <1>;
370 pinctrl-single,register-width = <32>;
371 pinctrl-single,function-mask = <0x0000000f>;
374 rst: rstmgr@ffd11000 {
376 compatible = "altr,stratix10-rst-mgr";
377 reg = <0xffd11000 0x1000>;
380 smmu: iommu@fa000000 {
381 compatible = "arm,mmu-500", "arm,smmu-v2";
382 reg = <0xfa000000 0x40000>;
383 #global-interrupts = <2>;
385 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
386 clock-names = "iommu";
387 interrupt-parent = <&intc>;
388 interrupts = <0 128 4>, /* Global Secure Fault */
389 <0 129 4>, /* Global Non-secure Fault */
390 /* Non-secure Context Interrupts (32) */
391 <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
392 <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
393 <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
394 <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
395 <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
396 <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
397 <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
398 <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
399 stream-match-mask = <0x7ff0>;
404 compatible = "snps,dw-apb-ssi";
405 #address-cells = <1>;
407 reg = <0xffda4000 0x1000>;
408 interrupts = <0 99 4>;
409 resets = <&rst SPIM0_RESET>;
413 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
418 compatible = "snps,dw-apb-ssi";
419 #address-cells = <1>;
421 reg = <0xffda5000 0x1000>;
422 interrupts = <0 100 4>;
423 resets = <&rst SPIM1_RESET>;
427 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
431 sysmgr: sysmgr@ffd12000 {
432 compatible = "altr,sys-mgr-s10","altr,sys-mgr";
433 reg = <0xffd12000 0x228>;
436 timer0: timer0@ffc03000 {
437 compatible = "snps,dw-apb-timer";
438 interrupts = <0 113 4>;
439 reg = <0xffc03000 0x100>;
440 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
441 clock-names = "timer";
444 timer1: timer1@ffc03100 {
445 compatible = "snps,dw-apb-timer";
446 interrupts = <0 114 4>;
447 reg = <0xffc03100 0x100>;
448 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
449 clock-names = "timer";
452 timer2: timer2@ffd00000 {
453 compatible = "snps,dw-apb-timer";
454 interrupts = <0 115 4>;
455 reg = <0xffd00000 0x100>;
456 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
457 clock-names = "timer";
460 timer3: timer3@ffd00100 {
461 compatible = "snps,dw-apb-timer";
462 interrupts = <0 116 4>;
463 reg = <0xffd00100 0x100>;
464 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
465 clock-names = "timer";
468 uart0: serial@ffc02000 {
469 compatible = "snps,dw-apb-uart";
470 reg = <0xffc02000 0x100>;
471 interrupts = <0 108 4>;
474 resets = <&rst UART0_RESET>;
475 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
479 uart1: serial@ffc02100 {
480 compatible = "snps,dw-apb-uart";
481 reg = <0xffc02100 0x100>;
482 interrupts = <0 109 4>;
485 resets = <&rst UART1_RESET>;
486 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
491 compatible = "snps,dwc2";
492 reg = <0xffb00000 0x40000>;
493 interrupts = <0 93 4>;
495 phy-names = "usb2-phy";
496 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
497 reset-names = "dwc2", "dwc2-ecc";
498 clocks = <&clkmgr STRATIX10_USB_CLK>;
505 compatible = "snps,dwc2";
506 reg = <0xffb40000 0x40000>;
507 interrupts = <0 94 4>;
509 phy-names = "usb2-phy";
510 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
511 reset-names = "dwc2", "dwc2-ecc";
512 clocks = <&clkmgr STRATIX10_USB_CLK>;
518 watchdog0: watchdog@ffd00200 {
519 compatible = "snps,dw-wdt";
520 reg = <0xffd00200 0x100>;
521 interrupts = <0 117 4>;
522 resets = <&rst WATCHDOG0_RESET>;
523 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
527 watchdog1: watchdog@ffd00300 {
528 compatible = "snps,dw-wdt";
529 reg = <0xffd00300 0x100>;
530 interrupts = <0 118 4>;
531 resets = <&rst WATCHDOG1_RESET>;
532 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
536 watchdog2: watchdog@ffd00400 {
537 compatible = "snps,dw-wdt";
538 reg = <0xffd00400 0x100>;
539 interrupts = <0 125 4>;
540 resets = <&rst WATCHDOG2_RESET>;
541 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
545 watchdog3: watchdog@ffd00500 {
546 compatible = "snps,dw-wdt";
547 reg = <0xffd00500 0x100>;
548 interrupts = <0 126 4>;
549 resets = <&rst WATCHDOG3_RESET>;
550 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
555 compatible = "altr,sdr-ctl", "syscon";
556 reg = <0xf8011100 0xc0>;
560 compatible = "altr,socfpga-s10-ecc-manager",
561 "altr,socfpga-a10-ecc-manager";
562 altr,sysmgr-syscon = <&sysmgr>;
563 #address-cells = <1>;
565 interrupts = <0 15 4>;
566 interrupt-controller;
567 #interrupt-cells = <2>;
571 compatible = "altr,sdram-edac-s10";
572 altr,sdr-syscon = <&sdr>;
577 compatible = "altr,socfpga-s10-ocram-ecc",
578 "altr,socfpga-a10-ocram-ecc";
579 reg = <0xff8cc000 0x100>;
580 altr,ecc-parent = <&ocram>;
585 compatible = "altr,socfpga-s10-usb-ecc",
586 "altr,socfpga-usb-ecc";
587 reg = <0xff8c4000 0x100>;
588 altr,ecc-parent = <&usb0>;
592 emac0-rx-ecc@ff8c0000 {
593 compatible = "altr,socfpga-s10-eth-mac-ecc",
594 "altr,socfpga-eth-mac-ecc";
595 reg = <0xff8c0000 0x100>;
596 altr,ecc-parent = <&gmac0>;
600 emac0-tx-ecc@ff8c0400 {
601 compatible = "altr,socfpga-s10-eth-mac-ecc",
602 "altr,socfpga-eth-mac-ecc";
603 reg = <0xff8c0400 0x100>;
604 altr,ecc-parent = <&gmac0>;
611 compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
612 #address-cells = <1>;
614 reg = <0xff8d2000 0x100>,
615 <0xff900000 0x100000>;
616 interrupts = <0 3 4>;
617 cdns,fifo-depth = <128>;
618 cdns,fifo-width = <4>;
619 cdns,trigger-address = <0x00000000>;
620 clocks = <&qspi_clk>;
627 compatible = "intel,stratix10-svc";
629 memory-region = <&service_reserved>;
632 compatible = "intel,stratix10-soc-fpga-mgr";
639 compatible = "usb-nop-xceiv";