arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 // Copyright (C) 2016 ARM Ltd.
   3
   4 #include <arm/sunxi-h3-h5.dtsi>
   5
   6 #include <dt-bindings/thermal/thermal.h>
   7
   8 / {
   9         cpus {
  10                 #address-cells = <1>;
  11                 #size-cells = <0>;
  12
  13                 cpu0: cpu@0 {
  14                         compatible = "arm,cortex-a53";
  15                         device_type = "cpu";
  16                         reg = <0>;
  17                         enable-method = "psci";
  18                         clocks = <&ccu CLK_CPUX>;
  19                         clock-latency-ns = <244144>; /* 8 32k periods */
  20                         #cooling-cells = <2>;
  21                 };
  22
  23                 cpu1: cpu@1 {
  24                         compatible = "arm,cortex-a53";
  25                         device_type = "cpu";
  26                         reg = <1>;
  27                         enable-method = "psci";
  28                         clocks = <&ccu CLK_CPUX>;
  29                         clock-latency-ns = <244144>; /* 8 32k periods */
  30                         #cooling-cells = <2>;
  31                 };
  32
  33                 cpu2: cpu@2 {
  34                         compatible = "arm,cortex-a53";
  35                         device_type = "cpu";
  36                         reg = <2>;
  37                         enable-method = "psci";
  38                         clocks = <&ccu CLK_CPUX>;
  39                         clock-latency-ns = <244144>; /* 8 32k periods */
  40                         #cooling-cells = <2>;
  41                 };
  42
  43                 cpu3: cpu@3 {
  44                         compatible = "arm,cortex-a53";
  45                         device_type = "cpu";
  46                         reg = <3>;
  47                         enable-method = "psci";
  48                         clocks = <&ccu CLK_CPUX>;
  49                         clock-latency-ns = <244144>; /* 8 32k periods */
  50                         #cooling-cells = <2>;
  51                 };
  52         };
  53
  54         pmu {
  55                 compatible = "arm,cortex-a53-pmu";
  56                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
  57                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
  58                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
  59                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
  60                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  61         };
  62
  63         psci {
  64                 compatible = "arm,psci-0.2";
  65                 method = "smc";
  66         };
  67
  68         timer {
  69                 compatible = "arm,armv8-timer";
  70                 arm,no-tick-in-suspend;
  71                 interrupts = <GIC_PPI 13
  72                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  73                              <GIC_PPI 14
  74                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  75                              <GIC_PPI 11
  76                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  77                              <GIC_PPI 10
  78                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  79         };
  80
  81         soc {
  82                 syscon: system-control@1c00000 {
  83                         compatible = "allwinner,sun50i-h5-system-control";
  84                         reg = <0x01c00000 0x1000>;
  85                         #address-cells = <1>;
  86                         #size-cells = <1>;
  87                         ranges;
  88
  89                         sram_c1: sram@18000 {
  90                                 compatible = "mmio-sram";
  91                                 reg = <0x00018000 0x1c000>;
  92                                 #address-cells = <1>;
  93                                 #size-cells = <1>;
  94                                 ranges = <0 0x00018000 0x1c000>;
  95
  96                                 ve_sram: sram-section@0 {
  97                                         compatible = "allwinner,sun50i-h5-sram-c1",
  98                                                      "allwinner,sun4i-a10-sram-c1";
  99                                         reg = <0x000000 0x1c000>;
 100                                 };
 101                         };
 102                 };
 103
 104                 video-codec@1c0e000 {
 105                         compatible = "allwinner,sun50i-h5-video-engine";
 106                         reg = <0x01c0e000 0x1000>;
 107                         clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
 108                                  <&ccu CLK_DRAM_VE>;
 109                         clock-names = "ahb", "mod", "ram";
 110                         resets = <&ccu RST_BUS_VE>;
 111                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 112                         allwinner,sram = <&ve_sram 1>;
 113                 };
 114
 115                 crypto: crypto@1c15000 {
 116                         compatible = "allwinner,sun50i-h5-crypto";
 117                         reg = <0x01c15000 0x1000>;
 118                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 119                         clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
 120                         clock-names = "bus", "mod";
 121                         resets = <&ccu RST_BUS_CE>;
 122                 };
 123
 124                 mali: gpu@1e80000 {
 125                         compatible = "allwinner,sun50i-h5-mali", "arm,mali-450";
 126                         reg = <0x01e80000 0x30000>;
 127                         /*
 128                          * While the datasheet lists an interrupt for the
 129                          * PMU, the actual silicon does not have the PMU
 130                          * block. Reads all return zero, and writes are
 131                          * ignored.
 132                          */
 133                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
 134                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 135                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 136                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 137                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 138                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 139                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 140                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 141                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 142                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 143                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 144                         interrupt-names = "gp",
 145                                           "gpmmu",
 146                                           "pp",
 147                                           "pp0",
 148                                           "ppmmu0",
 149                                           "pp1",
 150                                           "ppmmu1",
 151                                           "pp2",
 152                                           "ppmmu2",
 153                                           "pp3",
 154                                           "ppmmu3";
 155                         clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
 156                         clock-names = "bus", "core";
 157                         resets = <&ccu RST_BUS_GPU>;
 158
 159                         assigned-clocks = <&ccu CLK_GPU>;
 160                         assigned-clock-rates = <384000000>;
 161                 };
 162
 163                 ths: thermal-sensor@1c25000 {
 164                         compatible = "allwinner,sun50i-h5-ths";
 165                         reg = <0x01c25000 0x400>;
 166                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 167                         resets = <&ccu RST_BUS_THS>;
 168                         clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
 169                         clock-names = "bus", "mod";
 170                         nvmem-cells = <&ths_calibration>;
 171                         nvmem-cell-names = "calibration";
 172                         #thermal-sensor-cells = <1>;
 173                 };
 174         };
 175
 176         thermal-zones {
 177                 cpu_thermal: cpu-thermal {
 178                         polling-delay-passive = <0>;
 179                         polling-delay = <0>;
 180                         thermal-sensors = <&ths 0>;
 181
 182                         trips {
 183                                 cpu_hot_trip: cpu-hot {
 184                                         temperature = <80000>;
 185                                         hysteresis = <2000>;
 186                                         type = "passive";
 187                                 };
 188
 189                                 cpu_very_hot_trip: cpu-very-hot {
 190                                         temperature = <100000>;
 191                                         hysteresis = <0>;
 192                                         type = "critical";
 193                                 };
 194                         };
 195
 196                         cooling-maps {
 197                                 cpu-hot-limit {
 198                                         trip = <&cpu_hot_trip>;
 199                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 200                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 201                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 202                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 203                                 };
 204                         };
 205                 };
 206
 207                 gpu_thermal {
 208                         polling-delay-passive = <0>;
 209                         polling-delay = <0>;
 210                         thermal-sensors = <&ths 1>;
 211                 };
 212         };
 213 };
 214
 215 &ccu {
 216         compatible = "allwinner,sun50i-h5-ccu";
 217 };
 218
 219 &display_clocks {
 220         compatible = "allwinner,sun50i-h5-de2-clk";
 221 };
 222
 223 &mmc0 {
 224         compatible = "allwinner,sun50i-h5-mmc",
 225                      "allwinner,sun50i-a64-mmc";
 226         clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
 227         clock-names = "ahb", "mmc";
 228 };
 229
 230 &mmc1 {
 231         compatible = "allwinner,sun50i-h5-mmc",
 232                      "allwinner,sun50i-a64-mmc";
 233         clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
 234         clock-names = "ahb", "mmc";
 235 };
 236
 237 &mmc2 {
 238         compatible = "allwinner,sun50i-h5-emmc",
 239                      "allwinner,sun50i-a64-emmc";
 240         clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
 241         clock-names = "ahb", "mmc";
 242 };
 243
 244 &pio {
 245         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 246                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 247                      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 248         compatible = "allwinner,sun50i-h5-pinctrl";
 249 };
 250
 251 &rtc {
 252         compatible = "allwinner,sun50i-h5-rtc";
 253 };
 254
 255 &sid {
 256         compatible = "allwinner,sun50i-h5-sid";
 257 };