1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_WX
13 select ARCH_BINFMT_ELF_STATE
14 select ARCH_HAS_DEBUG_VIRTUAL
15 select ARCH_HAS_DEBUG_VM_PGTABLE
16 select ARCH_HAS_DMA_PREP_COHERENT
17 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
18 select ARCH_HAS_FAST_MULTIPLIER
19 select ARCH_HAS_FORTIFY_SOURCE
20 select ARCH_HAS_GCOV_PROFILE_ALL
21 select ARCH_HAS_GIGANTIC_PAGE
23 select ARCH_HAS_KEEPINITRD
24 select ARCH_HAS_MEMBARRIER_SYNC_CORE
25 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
26 select ARCH_HAS_PTE_DEVMAP
27 select ARCH_HAS_PTE_SPECIAL
28 select ARCH_HAS_SETUP_DMA_OPS
29 select ARCH_HAS_SET_DIRECT_MAP
30 select ARCH_HAS_SET_MEMORY
32 select ARCH_HAS_STRICT_KERNEL_RWX
33 select ARCH_HAS_STRICT_MODULE_RWX
34 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
35 select ARCH_HAS_SYNC_DMA_FOR_CPU
36 select ARCH_HAS_SYSCALL_WRAPPER
37 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
38 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
39 select ARCH_HAVE_ELF_PROT
40 select ARCH_HAVE_NMI_SAFE_CMPXCHG
41 select ARCH_INLINE_READ_LOCK if !PREEMPTION
42 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
43 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
44 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
45 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
46 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
47 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
48 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
49 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
50 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
51 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
52 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
53 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
54 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
55 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
56 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
57 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
58 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
59 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
60 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
61 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
62 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
63 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
64 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
65 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
66 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
67 select ARCH_KEEP_MEMBLOCK
68 select ARCH_USE_CMPXCHG_LOCKREF
69 select ARCH_USE_GNU_PROPERTY
70 select ARCH_USE_QUEUED_RWLOCKS
71 select ARCH_USE_QUEUED_SPINLOCKS
72 select ARCH_USE_SYM_ANNOTATIONS
73 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
74 select ARCH_SUPPORTS_MEMORY_FAILURE
75 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
76 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
77 select ARCH_SUPPORTS_LTO_CLANG_THIN
78 select ARCH_SUPPORTS_ATOMIC_RMW
79 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG)
80 select ARCH_SUPPORTS_NUMA_BALANCING
81 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
82 select ARCH_WANT_DEFAULT_BPF_JIT
83 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
84 select ARCH_WANT_FRAME_POINTERS
85 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
86 select ARCH_WANT_LD_ORPHAN_WARN
87 select ARCH_HAS_UBSAN_SANITIZE_ALL
91 select AUDIT_ARCH_COMPAT_GENERIC
92 select ARM_GIC_V2M if PCI
94 select ARM_GIC_V3_ITS if PCI
96 select BUILDTIME_TABLE_SORT
97 select CLONE_BACKWARDS
99 select CPU_PM if (SUSPEND || CPU_IDLE)
101 select DCACHE_WORD_ACCESS
102 select DMA_DIRECT_REMAP
105 select GENERIC_ALLOCATOR
106 select GENERIC_ARCH_TOPOLOGY
107 select GENERIC_CLOCKEVENTS_BROADCAST
108 select GENERIC_CPU_AUTOPROBE
109 select GENERIC_CPU_VULNERABILITIES
110 select GENERIC_EARLY_IOREMAP
111 select GENERIC_FIND_FIRST_BIT
112 select GENERIC_IDLE_POLL_SETUP
113 select GENERIC_IRQ_IPI
114 select GENERIC_IRQ_PROBE
115 select GENERIC_IRQ_SHOW
116 select GENERIC_IRQ_SHOW_LEVEL
117 select GENERIC_LIB_DEVMEM_IS_ALLOWED
118 select GENERIC_PCI_IOMAP
119 select GENERIC_PTDUMP
120 select GENERIC_SCHED_CLOCK
121 select GENERIC_SMP_IDLE_THREAD
122 select GENERIC_STRNCPY_FROM_USER
123 select GENERIC_STRNLEN_USER
124 select GENERIC_TIME_VSYSCALL
125 select GENERIC_GETTIMEOFDAY
126 select GENERIC_VDSO_TIME_NS
127 select HANDLE_DOMAIN_IRQ
128 select HARDIRQS_SW_RESEND
132 select HAVE_ACPI_APEI if (ACPI && EFI)
133 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
134 select HAVE_ARCH_AUDITSYSCALL
135 select HAVE_ARCH_BITREVERSE
136 select HAVE_ARCH_COMPILER_H
137 select HAVE_ARCH_HUGE_VMAP
138 select HAVE_ARCH_JUMP_LABEL
139 select HAVE_ARCH_JUMP_LABEL_RELATIVE
140 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
141 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
142 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
143 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
144 select HAVE_ARCH_KFENCE
145 select HAVE_ARCH_KGDB
146 select HAVE_ARCH_MMAP_RND_BITS
147 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
148 select HAVE_ARCH_PFN_VALID
149 select HAVE_ARCH_PREL32_RELOCATIONS
150 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
151 select HAVE_ARCH_SECCOMP_FILTER
152 select HAVE_ARCH_STACKLEAK
153 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
154 select HAVE_ARCH_TRACEHOOK
155 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
156 select HAVE_ARCH_VMAP_STACK
157 select HAVE_ARM_SMCCC
158 select HAVE_ASM_MODVERSIONS
160 select HAVE_C_RECORDMCOUNT
161 select HAVE_CMPXCHG_DOUBLE
162 select HAVE_CMPXCHG_LOCAL
163 select HAVE_CONTEXT_TRACKING
164 select HAVE_DEBUG_BUGVERBOSE
165 select HAVE_DEBUG_KMEMLEAK
166 select HAVE_DMA_CONTIGUOUS
167 select HAVE_DYNAMIC_FTRACE
168 select HAVE_DYNAMIC_FTRACE_WITH_REGS \
169 if $(cc-option,-fpatchable-function-entry=2)
170 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
171 if DYNAMIC_FTRACE_WITH_REGS
172 select HAVE_EFFICIENT_UNALIGNED_ACCESS
174 select HAVE_FTRACE_MCOUNT_RECORD
175 select HAVE_FUNCTION_TRACER
176 select HAVE_FUNCTION_ERROR_INJECTION
177 select HAVE_FUNCTION_GRAPH_TRACER
178 select HAVE_GCC_PLUGINS
179 select HAVE_HW_BREAKPOINT if PERF_EVENTS
180 select HAVE_IRQ_TIME_ACCOUNTING
182 select HAVE_PATA_PLATFORM
183 select HAVE_PERF_EVENTS
184 select HAVE_PERF_REGS
185 select HAVE_PERF_USER_STACK_DUMP
186 select HAVE_REGS_AND_STACK_ACCESS_API
187 select HAVE_FUNCTION_ARG_ACCESS_API
188 select HAVE_FUTEX_CMPXCHG if FUTEX
189 select MMU_GATHER_RCU_TABLE_FREE
191 select HAVE_STACKPROTECTOR
192 select HAVE_SYSCALL_TRACEPOINTS
194 select HAVE_KRETPROBES
195 select HAVE_GENERIC_VDSO
196 select IOMMU_DMA if IOMMU_SUPPORT
198 select IRQ_FORCED_THREADING
199 select KASAN_VMALLOC if KASAN_GENERIC
200 select MODULES_USE_ELF_RELA
201 select NEED_DMA_MAP_STATE
202 select NEED_SG_DMA_LENGTH
204 select OF_EARLY_FLATTREE
205 select PCI_DOMAINS_GENERIC if PCI
206 select PCI_ECAM if (ACPI && PCI)
207 select PCI_SYSCALL if PCI
212 select SYSCTL_EXCEPTION_TRACE
213 select THREAD_INFO_IN_TASK
215 ARM 64-bit (AArch64) Linux support.
223 config ARM64_PAGE_SHIFT
225 default 16 if ARM64_64K_PAGES
226 default 14 if ARM64_16K_PAGES
229 config ARM64_CONT_PTE_SHIFT
231 default 5 if ARM64_64K_PAGES
232 default 7 if ARM64_16K_PAGES
235 config ARM64_CONT_PMD_SHIFT
237 default 5 if ARM64_64K_PAGES
238 default 5 if ARM64_16K_PAGES
241 config ARCH_MMAP_RND_BITS_MIN
242 default 14 if ARM64_64K_PAGES
243 default 16 if ARM64_16K_PAGES
246 # max bits determined by the following formula:
247 # VA_BITS - PAGE_SHIFT - 3
248 config ARCH_MMAP_RND_BITS_MAX
249 default 19 if ARM64_VA_BITS=36
250 default 24 if ARM64_VA_BITS=39
251 default 27 if ARM64_VA_BITS=42
252 default 30 if ARM64_VA_BITS=47
253 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
254 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
255 default 33 if ARM64_VA_BITS=48
256 default 14 if ARM64_64K_PAGES
257 default 16 if ARM64_16K_PAGES
260 config ARCH_MMAP_RND_COMPAT_BITS_MIN
261 default 7 if ARM64_64K_PAGES
262 default 9 if ARM64_16K_PAGES
265 config ARCH_MMAP_RND_COMPAT_BITS_MAX
271 config STACKTRACE_SUPPORT
274 config ILLEGAL_POINTER_VALUE
276 default 0xdead000000000000
278 config LOCKDEP_SUPPORT
281 config TRACE_IRQFLAGS_SUPPORT
288 config GENERIC_BUG_RELATIVE_POINTERS
290 depends on GENERIC_BUG
292 config GENERIC_HWEIGHT
298 config GENERIC_CALIBRATE_DELAY
302 bool "Support DMA zone" if EXPERT
306 bool "Support DMA32 zone" if EXPERT
309 config ARCH_ENABLE_MEMORY_HOTPLUG
312 config ARCH_ENABLE_MEMORY_HOTREMOVE
318 config KERNEL_MODE_NEON
321 config FIX_EARLYCON_MEM
324 config PGTABLE_LEVELS
326 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
327 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
328 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
329 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
330 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
331 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
333 config ARCH_SUPPORTS_UPROBES
336 config ARCH_PROC_KCORE_TEXT
339 config BROKEN_GAS_INST
340 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
342 config KASAN_SHADOW_OFFSET
344 depends on KASAN_GENERIC || KASAN_SW_TAGS
345 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
346 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
347 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
348 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
349 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
350 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
351 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
352 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
353 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
354 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
355 default 0xffffffffffffffff
357 source "arch/arm64/Kconfig.platforms"
359 menu "Kernel Features"
361 menu "ARM errata workarounds via the alternatives framework"
363 config ARM64_WORKAROUND_CLEAN_CACHE
366 config ARM64_ERRATUM_826319
367 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
369 select ARM64_WORKAROUND_CLEAN_CACHE
371 This option adds an alternative code sequence to work around ARM
372 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
373 AXI master interface and an L2 cache.
375 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
376 and is unable to accept a certain write via this interface, it will
377 not progress on read data presented on the read data channel and the
380 The workaround promotes data cache clean instructions to
381 data cache clean-and-invalidate.
382 Please note that this does not necessarily enable the workaround,
383 as it depends on the alternative framework, which will only patch
384 the kernel if an affected CPU is detected.
388 config ARM64_ERRATUM_827319
389 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
391 select ARM64_WORKAROUND_CLEAN_CACHE
393 This option adds an alternative code sequence to work around ARM
394 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
395 master interface and an L2 cache.
397 Under certain conditions this erratum can cause a clean line eviction
398 to occur at the same time as another transaction to the same address
399 on the AMBA 5 CHI interface, which can cause data corruption if the
400 interconnect reorders the two transactions.
402 The workaround promotes data cache clean instructions to
403 data cache clean-and-invalidate.
404 Please note that this does not necessarily enable the workaround,
405 as it depends on the alternative framework, which will only patch
406 the kernel if an affected CPU is detected.
410 config ARM64_ERRATUM_824069
411 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
413 select ARM64_WORKAROUND_CLEAN_CACHE
415 This option adds an alternative code sequence to work around ARM
416 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
417 to a coherent interconnect.
419 If a Cortex-A53 processor is executing a store or prefetch for
420 write instruction at the same time as a processor in another
421 cluster is executing a cache maintenance operation to the same
422 address, then this erratum might cause a clean cache line to be
423 incorrectly marked as dirty.
425 The workaround promotes data cache clean instructions to
426 data cache clean-and-invalidate.
427 Please note that this option does not necessarily enable the
428 workaround, as it depends on the alternative framework, which will
429 only patch the kernel if an affected CPU is detected.
433 config ARM64_ERRATUM_819472
434 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
436 select ARM64_WORKAROUND_CLEAN_CACHE
438 This option adds an alternative code sequence to work around ARM
439 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
440 present when it is connected to a coherent interconnect.
442 If the processor is executing a load and store exclusive sequence at
443 the same time as a processor in another cluster is executing a cache
444 maintenance operation to the same address, then this erratum might
445 cause data corruption.
447 The workaround promotes data cache clean instructions to
448 data cache clean-and-invalidate.
449 Please note that this does not necessarily enable the workaround,
450 as it depends on the alternative framework, which will only patch
451 the kernel if an affected CPU is detected.
455 config ARM64_ERRATUM_832075
456 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
459 This option adds an alternative code sequence to work around ARM
460 erratum 832075 on Cortex-A57 parts up to r1p2.
462 Affected Cortex-A57 parts might deadlock when exclusive load/store
463 instructions to Write-Back memory are mixed with Device loads.
465 The workaround is to promote device loads to use Load-Acquire
467 Please note that this does not necessarily enable the workaround,
468 as it depends on the alternative framework, which will only patch
469 the kernel if an affected CPU is detected.
473 config ARM64_ERRATUM_834220
474 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
478 This option adds an alternative code sequence to work around ARM
479 erratum 834220 on Cortex-A57 parts up to r1p2.
481 Affected Cortex-A57 parts might report a Stage 2 translation
482 fault as the result of a Stage 1 fault for load crossing a
483 page boundary when there is a permission or device memory
484 alignment fault at Stage 1 and a translation fault at Stage 2.
486 The workaround is to verify that the Stage 1 translation
487 doesn't generate a fault before handling the Stage 2 fault.
488 Please note that this does not necessarily enable the workaround,
489 as it depends on the alternative framework, which will only patch
490 the kernel if an affected CPU is detected.
494 config ARM64_ERRATUM_845719
495 bool "Cortex-A53: 845719: a load might read incorrect data"
499 This option adds an alternative code sequence to work around ARM
500 erratum 845719 on Cortex-A53 parts up to r0p4.
502 When running a compat (AArch32) userspace on an affected Cortex-A53
503 part, a load at EL0 from a virtual address that matches the bottom 32
504 bits of the virtual address used by a recent load at (AArch64) EL1
505 might return incorrect data.
507 The workaround is to write the contextidr_el1 register on exception
508 return to a 32-bit task.
509 Please note that this does not necessarily enable the workaround,
510 as it depends on the alternative framework, which will only patch
511 the kernel if an affected CPU is detected.
515 config ARM64_ERRATUM_843419
516 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
518 select ARM64_MODULE_PLTS if MODULES
520 This option links the kernel with '--fix-cortex-a53-843419' and
521 enables PLT support to replace certain ADRP instructions, which can
522 cause subsequent memory accesses to use an incorrect address on
523 Cortex-A53 parts up to r0p4.
527 config ARM64_ERRATUM_1024718
528 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
531 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
533 Affected Cortex-A55 cores (all revisions) could cause incorrect
534 update of the hardware dirty bit when the DBM/AP bits are updated
535 without a break-before-make. The workaround is to disable the usage
536 of hardware DBM locally on the affected cores. CPUs not affected by
537 this erratum will continue to use the feature.
541 config ARM64_ERRATUM_1418040
542 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
546 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
547 errata 1188873 and 1418040.
549 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
550 cause register corruption when accessing the timer registers
551 from AArch32 userspace.
555 config ARM64_WORKAROUND_SPECULATIVE_AT
558 config ARM64_ERRATUM_1165522
559 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
561 select ARM64_WORKAROUND_SPECULATIVE_AT
563 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
565 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
566 corrupted TLBs by speculating an AT instruction during a guest
571 config ARM64_ERRATUM_1319367
572 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
574 select ARM64_WORKAROUND_SPECULATIVE_AT
576 This option adds work arounds for ARM Cortex-A57 erratum 1319537
577 and A72 erratum 1319367
579 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
580 speculating an AT instruction during a guest context switch.
584 config ARM64_ERRATUM_1530923
585 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
587 select ARM64_WORKAROUND_SPECULATIVE_AT
589 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
591 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
592 corrupted TLBs by speculating an AT instruction during a guest
597 config ARM64_WORKAROUND_REPEAT_TLBI
600 config ARM64_ERRATUM_1286807
601 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
603 select ARM64_WORKAROUND_REPEAT_TLBI
605 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
607 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
608 address for a cacheable mapping of a location is being
609 accessed by a core while another core is remapping the virtual
610 address to a new physical page using the recommended
611 break-before-make sequence, then under very rare circumstances
612 TLBI+DSB completes before a read using the translation being
613 invalidated has been observed by other observers. The
614 workaround repeats the TLBI+DSB operation.
616 config ARM64_ERRATUM_1463225
617 bool "Cortex-A76: Software Step might prevent interrupt recognition"
620 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
622 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
623 of a system call instruction (SVC) can prevent recognition of
624 subsequent interrupts when software stepping is disabled in the
625 exception handler of the system call and either kernel debugging
626 is enabled or VHE is in use.
628 Work around the erratum by triggering a dummy step exception
629 when handling a system call from a task that is being stepped
630 in a VHE configuration of the kernel.
634 config ARM64_ERRATUM_1542419
635 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
638 This option adds a workaround for ARM Neoverse-N1 erratum
641 Affected Neoverse-N1 cores could execute a stale instruction when
642 modified by another CPU. The workaround depends on a firmware
645 Workaround the issue by hiding the DIC feature from EL0. This
646 forces user-space to perform cache maintenance.
650 config ARM64_ERRATUM_1508412
651 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
654 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
656 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
657 of a store-exclusive or read of PAR_EL1 and a load with device or
658 non-cacheable memory attributes. The workaround depends on a firmware
661 KVM guests must also have the workaround implemented or they can
664 Work around the issue by inserting DMB SY barriers around PAR_EL1
665 register reads and warning KVM users. The DMB barrier is sufficient
666 to prevent a speculative PAR_EL1 read.
670 config CAVIUM_ERRATUM_22375
671 bool "Cavium erratum 22375, 24313"
674 Enable workaround for errata 22375 and 24313.
676 This implements two gicv3-its errata workarounds for ThunderX. Both
677 with a small impact affecting only ITS table allocation.
679 erratum 22375: only alloc 8MB table size
680 erratum 24313: ignore memory access type
682 The fixes are in ITS initialization and basically ignore memory access
683 type and table size provided by the TYPER and BASER registers.
687 config CAVIUM_ERRATUM_23144
688 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
692 ITS SYNC command hang for cross node io and collections/cpu mapping.
696 config CAVIUM_ERRATUM_23154
697 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
700 The gicv3 of ThunderX requires a modified version for
701 reading the IAR status to ensure data synchronization
702 (access to icc_iar1_el1 is not sync'ed before and after).
706 config CAVIUM_ERRATUM_27456
707 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
710 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
711 instructions may cause the icache to become corrupted if it
712 contains data for a non-current ASID. The fix is to
713 invalidate the icache when changing the mm context.
717 config CAVIUM_ERRATUM_30115
718 bool "Cavium erratum 30115: Guest may disable interrupts in host"
721 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
722 1.2, and T83 Pass 1.0, KVM guest execution may disable
723 interrupts in host. Trapping both GICv3 group-0 and group-1
724 accesses sidesteps the issue.
728 config CAVIUM_TX2_ERRATUM_219
729 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
732 On Cavium ThunderX2, a load, store or prefetch instruction between a
733 TTBR update and the corresponding context synchronizing operation can
734 cause a spurious Data Abort to be delivered to any hardware thread in
737 Work around the issue by avoiding the problematic code sequence and
738 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
739 trap handler performs the corresponding register access, skips the
740 instruction and ensures context synchronization by virtue of the
745 config FUJITSU_ERRATUM_010001
746 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
749 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
750 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
751 accesses may cause undefined fault (Data abort, DFSC=0b111111).
752 This fault occurs under a specific hardware condition when a
753 load/store instruction performs an address translation using:
754 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
755 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
756 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
757 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
759 The workaround is to ensure these bits are clear in TCR_ELx.
760 The workaround only affects the Fujitsu-A64FX.
764 config HISILICON_ERRATUM_161600802
765 bool "Hip07 161600802: Erroneous redistributor VLPI base"
768 The HiSilicon Hip07 SoC uses the wrong redistributor base
769 when issued ITS commands such as VMOVP and VMAPP, and requires
770 a 128kB offset to be applied to the target address in this commands.
774 config QCOM_FALKOR_ERRATUM_1003
775 bool "Falkor E1003: Incorrect translation due to ASID change"
778 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
779 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
780 in TTBR1_EL1, this situation only occurs in the entry trampoline and
781 then only for entries in the walk cache, since the leaf translation
782 is unchanged. Work around the erratum by invalidating the walk cache
783 entries for the trampoline before entering the kernel proper.
785 config QCOM_FALKOR_ERRATUM_1009
786 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
788 select ARM64_WORKAROUND_REPEAT_TLBI
790 On Falkor v1, the CPU may prematurely complete a DSB following a
791 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
792 one more time to fix the issue.
796 config QCOM_QDF2400_ERRATUM_0065
797 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
800 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
801 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
802 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
806 config QCOM_FALKOR_ERRATUM_E1041
807 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
810 Falkor CPU may speculatively fetch instructions from an improper
811 memory location when MMU translation is changed from SCTLR_ELn[M]=1
812 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
816 config NVIDIA_CARMEL_CNP_ERRATUM
817 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
820 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
821 invalidate shared TLB entries installed by a different core, as it would
822 on standard ARM cores.
826 config SOCIONEXT_SYNQUACER_PREITS
827 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
830 Socionext Synquacer SoCs implement a separate h/w block to generate
831 MSI doorbell writes with non-zero values for the device ID.
840 default ARM64_4K_PAGES
842 Page size (translation granule) configuration.
844 config ARM64_4K_PAGES
847 This feature enables 4KB pages support.
849 config ARM64_16K_PAGES
852 The system will use 16KB pages support. AArch32 emulation
853 requires applications compiled with 16K (or a multiple of 16K)
856 config ARM64_64K_PAGES
859 This feature enables 64KB pages support (4KB by default)
860 allowing only two levels of page tables and faster TLB
861 look-up. AArch32 emulation requires applications compiled
862 with 64K aligned segments.
867 prompt "Virtual address space size"
868 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
869 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
870 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
872 Allows choosing one of multiple possible virtual address
873 space sizes. The level of translation table is determined by
874 a combination of page size and virtual address space size.
876 config ARM64_VA_BITS_36
877 bool "36-bit" if EXPERT
878 depends on ARM64_16K_PAGES
880 config ARM64_VA_BITS_39
882 depends on ARM64_4K_PAGES
884 config ARM64_VA_BITS_42
886 depends on ARM64_64K_PAGES
888 config ARM64_VA_BITS_47
890 depends on ARM64_16K_PAGES
892 config ARM64_VA_BITS_48
895 config ARM64_VA_BITS_52
897 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
899 Enable 52-bit virtual addressing for userspace when explicitly
900 requested via a hint to mmap(). The kernel will also use 52-bit
901 virtual addresses for its own mappings (provided HW support for
902 this feature is available, otherwise it reverts to 48-bit).
904 NOTE: Enabling 52-bit virtual addressing in conjunction with
905 ARMv8.3 Pointer Authentication will result in the PAC being
906 reduced from 7 bits to 3 bits, which may have a significant
907 impact on its susceptibility to brute-force attacks.
909 If unsure, select 48-bit virtual addressing instead.
913 config ARM64_FORCE_52BIT
914 bool "Force 52-bit virtual addresses for userspace"
915 depends on ARM64_VA_BITS_52 && EXPERT
917 For systems with 52-bit userspace VAs enabled, the kernel will attempt
918 to maintain compatibility with older software by providing 48-bit VAs
919 unless a hint is supplied to mmap.
921 This configuration option disables the 48-bit compatibility logic, and
922 forces all userspace addresses to be 52-bit on HW that supports it. One
923 should only enable this configuration option for stress testing userspace
924 memory management code. If unsure say N here.
928 default 36 if ARM64_VA_BITS_36
929 default 39 if ARM64_VA_BITS_39
930 default 42 if ARM64_VA_BITS_42
931 default 47 if ARM64_VA_BITS_47
932 default 48 if ARM64_VA_BITS_48
933 default 52 if ARM64_VA_BITS_52
936 prompt "Physical address space size"
937 default ARM64_PA_BITS_48
939 Choose the maximum physical address range that the kernel will
942 config ARM64_PA_BITS_48
945 config ARM64_PA_BITS_52
946 bool "52-bit (ARMv8.2)"
947 depends on ARM64_64K_PAGES
948 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
950 Enable support for a 52-bit physical address space, introduced as
951 part of the ARMv8.2-LPA extension.
953 With this enabled, the kernel will also continue to work on CPUs that
954 do not support ARMv8.2-LPA, but with some added memory overhead (and
955 minor performance overhead).
961 default 48 if ARM64_PA_BITS_48
962 default 52 if ARM64_PA_BITS_52
966 default CPU_LITTLE_ENDIAN
968 Select the endianness of data accesses performed by the CPU. Userspace
969 applications will need to be compiled and linked for the endianness
970 that is selected here.
972 config CPU_BIG_ENDIAN
973 bool "Build big-endian kernel"
974 depends on !LD_IS_LLD || LLD_VERSION >= 130000
976 Say Y if you plan on running a kernel with a big-endian userspace.
978 config CPU_LITTLE_ENDIAN
979 bool "Build little-endian kernel"
981 Say Y if you plan on running a kernel with a little-endian userspace.
982 This is usually the case for distributions targeting arm64.
987 bool "Multi-core scheduler support"
989 Multi-core scheduler support improves the CPU scheduler's decision
990 making when dealing with multi-core CPU chips at a cost of slightly
991 increased overhead in some places. If unsure say N here.
994 bool "SMT scheduler support"
996 Improves the CPU scheduler's decision making when dealing with
997 MultiThreading at a cost of slightly increased overhead in some
998 places. If unsure say N here.
1001 int "Maximum number of CPUs (2-4096)"
1006 bool "Support for hot-pluggable CPUs"
1007 select GENERIC_IRQ_MIGRATION
1009 Say Y here to experiment with turning CPUs off and on. CPUs
1010 can be controlled through /sys/devices/system/cpu.
1012 # Common NUMA Features
1014 bool "NUMA Memory Allocation and Scheduler Support"
1015 select GENERIC_ARCH_NUMA
1016 select ACPI_NUMA if ACPI
1019 Enable NUMA (Non-Uniform Memory Access) support.
1021 The kernel will try to allocate memory used by a CPU on the
1022 local memory of the CPU and add some more
1023 NUMA awareness to the kernel.
1026 int "Maximum NUMA Nodes (as a power of 2)"
1029 depends on NEED_MULTIPLE_NODES
1031 Specify the maximum number of NUMA Nodes available on the target
1032 system. Increases memory reserved to accommodate various tables.
1034 config USE_PERCPU_NUMA_NODE_ID
1038 config HAVE_SETUP_PER_CPU_AREA
1042 config NEED_PER_CPU_EMBED_FIRST_CHUNK
1046 config HOLES_IN_ZONE
1049 source "kernel/Kconfig.hz"
1051 config ARCH_SPARSEMEM_ENABLE
1053 select SPARSEMEM_VMEMMAP_ENABLE
1055 config ARCH_SPARSEMEM_DEFAULT
1056 def_bool ARCH_SPARSEMEM_ENABLE
1058 config ARCH_SELECT_MEMORY_MODEL
1059 def_bool ARCH_SPARSEMEM_ENABLE
1061 config ARCH_FLATMEM_ENABLE
1064 config HW_PERF_EVENTS
1068 config SYS_SUPPORTS_HUGETLBFS
1071 config ARCH_HAS_CACHE_LINE_SIZE
1074 config ARCH_HAS_FILTER_PGPROT
1077 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
1078 def_bool y if PGTABLE_LEVELS > 2
1080 # Supported by clang >= 7.0
1081 config CC_HAVE_SHADOW_CALL_STACK
1082 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1085 bool "Enable paravirtualization code"
1087 This changes the kernel so it can modify itself when it is run
1088 under a hypervisor, potentially improving performance significantly
1089 over full virtualization.
1091 config PARAVIRT_TIME_ACCOUNTING
1092 bool "Paravirtual steal time accounting"
1095 Select this option to enable fine granularity task steal time
1096 accounting. Time spent executing other tasks in parallel with
1097 the current vCPU is discounted from the vCPU power. To account for
1098 that, there can be a small performance impact.
1100 If in doubt, say N here.
1103 depends on PM_SLEEP_SMP
1105 bool "kexec system call"
1107 kexec is a system call that implements the ability to shutdown your
1108 current kernel, and to start another kernel. It is like a reboot
1109 but it is independent of the system firmware. And like a reboot
1110 you can start any kernel with it, not just Linux.
1113 bool "kexec file based system call"
1116 This is new version of kexec system call. This system call is
1117 file based and takes file descriptors as system call argument
1118 for kernel and initramfs as opposed to list of segments as
1119 accepted by previous system call.
1122 bool "Verify kernel signature during kexec_file_load() syscall"
1123 depends on KEXEC_FILE
1125 Select this option to verify a signature with loaded kernel
1126 image. If configured, any attempt of loading a image without
1127 valid signature will fail.
1129 In addition to that option, you need to enable signature
1130 verification for the corresponding kernel image type being
1131 loaded in order for this to work.
1133 config KEXEC_IMAGE_VERIFY_SIG
1134 bool "Enable Image signature verification support"
1136 depends on KEXEC_SIG
1137 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1139 Enable Image signature verification support.
1141 comment "Support for PE file signature verification disabled"
1142 depends on KEXEC_SIG
1143 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1146 bool "Build kdump crash kernel"
1148 Generate crash dump after being started by kexec. This should
1149 be normally only set in special crash dump kernels which are
1150 loaded in the main kernel with kexec-tools into a specially
1151 reserved region and then later executed after a crash by
1154 For more details see Documentation/admin-guide/kdump/kdump.rst
1158 depends on HIBERNATION
1165 bool "Xen guest support on ARM64"
1166 depends on ARM64 && OF
1170 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1172 config FORCE_MAX_ZONEORDER
1174 default "14" if ARM64_64K_PAGES
1175 default "12" if ARM64_16K_PAGES
1178 The kernel memory allocator divides physically contiguous memory
1179 blocks into "zones", where each zone is a power of two number of
1180 pages. This option selects the largest power of two that the kernel
1181 keeps in the memory allocator. If you need to allocate very large
1182 blocks of physically contiguous memory, then you may need to
1183 increase this value.
1185 This config option is actually maximum order plus one. For example,
1186 a value of 11 means that the largest free memory block is 2^10 pages.
1188 We make sure that we can allocate upto a HugePage size for each configuration.
1190 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1192 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1193 4M allocations matching the default size used by generic code.
1195 config UNMAP_KERNEL_AT_EL0
1196 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1199 Speculation attacks against some high-performance processors can
1200 be used to bypass MMU permission checks and leak kernel data to
1201 userspace. This can be defended against by unmapping the kernel
1202 when running in userspace, mapping it back in on exception entry
1203 via a trampoline page in the vector table.
1207 config RODATA_FULL_DEFAULT_ENABLED
1208 bool "Apply r/o permissions of VM areas also to their linear aliases"
1211 Apply read-only attributes of VM areas to the linear alias of
1212 the backing pages as well. This prevents code or read-only data
1213 from being modified (inadvertently or intentionally) via another
1214 mapping of the same memory page. This additional enhancement can
1215 be turned off at runtime by passing rodata=[off|on] (and turned on
1216 with rodata=full if this option is set to 'n')
1218 This requires the linear region to be mapped down to pages,
1219 which may adversely affect performance in some cases.
1221 config ARM64_SW_TTBR0_PAN
1222 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1224 Enabling this option prevents the kernel from accessing
1225 user-space memory directly by pointing TTBR0_EL1 to a reserved
1226 zeroed area and reserved ASID. The user access routines
1227 restore the valid TTBR0_EL1 temporarily.
1229 config ARM64_TAGGED_ADDR_ABI
1230 bool "Enable the tagged user addresses syscall ABI"
1233 When this option is enabled, user applications can opt in to a
1234 relaxed ABI via prctl() allowing tagged addresses to be passed
1235 to system calls as pointer arguments. For details, see
1236 Documentation/arm64/tagged-address-abi.rst.
1239 bool "Kernel support for 32-bit EL0"
1240 depends on ARM64_4K_PAGES || EXPERT
1242 select OLD_SIGSUSPEND3
1243 select COMPAT_OLD_SIGACTION
1245 This option enables support for a 32-bit EL0 running under a 64-bit
1246 kernel at EL1. AArch32-specific components such as system calls,
1247 the user helper functions, VFP support and the ptrace interface are
1248 handled appropriately by the kernel.
1250 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1251 that you will only be able to execute AArch32 binaries that were compiled
1252 with page size aligned segments.
1254 If you want to execute 32-bit userspace applications, say Y.
1258 config KUSER_HELPERS
1259 bool "Enable kuser helpers page for 32-bit applications"
1262 Warning: disabling this option may break 32-bit user programs.
1264 Provide kuser helpers to compat tasks. The kernel provides
1265 helper code to userspace in read only form at a fixed location
1266 to allow userspace to be independent of the CPU type fitted to
1267 the system. This permits binaries to be run on ARMv4 through
1268 to ARMv8 without modification.
1270 See Documentation/arm/kernel_user_helpers.rst for details.
1272 However, the fixed address nature of these helpers can be used
1273 by ROP (return orientated programming) authors when creating
1276 If all of the binaries and libraries which run on your platform
1277 are built specifically for your platform, and make no use of
1278 these helpers, then you can turn this option off to hinder
1279 such exploits. However, in that case, if a binary or library
1280 relying on those helpers is run, it will not function correctly.
1282 Say N here only if you are absolutely certain that you do not
1283 need these helpers; otherwise, the safe option is to say Y.
1286 bool "Enable vDSO for 32-bit applications"
1287 depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1288 select GENERIC_COMPAT_VDSO
1291 Place in the process address space of 32-bit applications an
1292 ELF shared object providing fast implementations of gettimeofday
1295 You must have a 32-bit build of glibc 2.22 or later for programs
1296 to seamlessly take advantage of this.
1298 config THUMB2_COMPAT_VDSO
1299 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1300 depends on COMPAT_VDSO
1303 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1304 otherwise with '-marm'.
1306 menuconfig ARMV8_DEPRECATED
1307 bool "Emulate deprecated/obsolete ARMv8 instructions"
1310 Legacy software support may require certain instructions
1311 that have been deprecated or obsoleted in the architecture.
1313 Enable this config to enable selective emulation of these
1320 config SWP_EMULATION
1321 bool "Emulate SWP/SWPB instructions"
1323 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1324 they are always undefined. Say Y here to enable software
1325 emulation of these instructions for userspace using LDXR/STXR.
1326 This feature can be controlled at runtime with the abi.swp
1327 sysctl which is disabled by default.
1329 In some older versions of glibc [<=2.8] SWP is used during futex
1330 trylock() operations with the assumption that the code will not
1331 be preempted. This invalid assumption may be more likely to fail
1332 with SWP emulation enabled, leading to deadlock of the user
1335 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1336 on an external transaction monitoring block called a global
1337 monitor to maintain update atomicity. If your system does not
1338 implement a global monitor, this option can cause programs that
1339 perform SWP operations to uncached memory to deadlock.
1343 config CP15_BARRIER_EMULATION
1344 bool "Emulate CP15 Barrier instructions"
1346 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1347 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1348 strongly recommended to use the ISB, DSB, and DMB
1349 instructions instead.
1351 Say Y here to enable software emulation of these
1352 instructions for AArch32 userspace code. When this option is
1353 enabled, CP15 barrier usage is traced which can help
1354 identify software that needs updating. This feature can be
1355 controlled at runtime with the abi.cp15_barrier sysctl.
1359 config SETEND_EMULATION
1360 bool "Emulate SETEND instruction"
1362 The SETEND instruction alters the data-endianness of the
1363 AArch32 EL0, and is deprecated in ARMv8.
1365 Say Y here to enable software emulation of the instruction
1366 for AArch32 userspace code. This feature can be controlled
1367 at runtime with the abi.setend sysctl.
1369 Note: All the cpus on the system must have mixed endian support at EL0
1370 for this feature to be enabled. If a new CPU - which doesn't support mixed
1371 endian - is hotplugged in after this feature has been enabled, there could
1372 be unexpected results in the applications.
1379 menu "ARMv8.1 architectural features"
1381 config ARM64_HW_AFDBM
1382 bool "Support for hardware updates of the Access and Dirty page flags"
1385 The ARMv8.1 architecture extensions introduce support for
1386 hardware updates of the access and dirty information in page
1387 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1388 capable processors, accesses to pages with PTE_AF cleared will
1389 set this bit instead of raising an access flag fault.
1390 Similarly, writes to read-only pages with the DBM bit set will
1391 clear the read-only bit (AP[2]) instead of raising a
1394 Kernels built with this configuration option enabled continue
1395 to work on pre-ARMv8.1 hardware and the performance impact is
1396 minimal. If unsure, say Y.
1399 bool "Enable support for Privileged Access Never (PAN)"
1402 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1403 prevents the kernel or hypervisor from accessing user-space (EL0)
1406 Choosing this option will cause any unprotected (not using
1407 copy_to_user et al) memory access to fail with a permission fault.
1409 The feature is detected at runtime, and will remain as a 'nop'
1410 instruction if the cpu does not implement the feature.
1413 def_bool $(as-instr,.arch_extension rcpc)
1415 config AS_HAS_LSE_ATOMICS
1416 def_bool $(as-instr,.arch_extension lse)
1418 config ARM64_LSE_ATOMICS
1420 default ARM64_USE_LSE_ATOMICS
1421 depends on AS_HAS_LSE_ATOMICS
1423 config ARM64_USE_LSE_ATOMICS
1424 bool "Atomic instructions"
1425 depends on JUMP_LABEL
1428 As part of the Large System Extensions, ARMv8.1 introduces new
1429 atomic instructions that are designed specifically to scale in
1432 Say Y here to make use of these instructions for the in-kernel
1433 atomic routines. This incurs a small overhead on CPUs that do
1434 not support these instructions and requires the kernel to be
1435 built with binutils >= 2.25 in order for the new instructions
1440 menu "ARMv8.2 architectural features"
1443 bool "Enable support for persistent memory"
1444 select ARCH_HAS_PMEM_API
1445 select ARCH_HAS_UACCESS_FLUSHCACHE
1447 Say Y to enable support for the persistent memory API based on the
1448 ARMv8.2 DCPoP feature.
1450 The feature is detected at runtime, and the kernel will use DC CVAC
1451 operations if DC CVAP is not supported (following the behaviour of
1452 DC CVAP itself if the system does not define a point of persistence).
1454 config ARM64_RAS_EXTN
1455 bool "Enable support for RAS CPU Extensions"
1458 CPUs that support the Reliability, Availability and Serviceability
1459 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1460 errors, classify them and report them to software.
1462 On CPUs with these extensions system software can use additional
1463 barriers to determine if faults are pending and read the
1464 classification from a new set of registers.
1466 Selecting this feature will allow the kernel to use these barriers
1467 and access the new registers if the system supports the extension.
1468 Platform RAS features may additionally depend on firmware support.
1471 bool "Enable support for Common Not Private (CNP) translations"
1473 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1475 Common Not Private (CNP) allows translation table entries to
1476 be shared between different PEs in the same inner shareable
1477 domain, so the hardware can use this fact to optimise the
1478 caching of such entries in the TLB.
1480 Selecting this option allows the CNP feature to be detected
1481 at runtime, and does not affect PEs that do not implement
1486 menu "ARMv8.3 architectural features"
1488 config ARM64_PTR_AUTH
1489 bool "Enable support for pointer authentication"
1491 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1492 # Modern compilers insert a .note.gnu.property section note for PAC
1493 # which is only understood by binutils starting with version 2.33.1.
1494 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1495 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1496 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1498 Pointer authentication (part of the ARMv8.3 Extensions) provides
1499 instructions for signing and authenticating pointers against secret
1500 keys, which can be used to mitigate Return Oriented Programming (ROP)
1503 This option enables these instructions at EL0 (i.e. for userspace).
1504 Choosing this option will cause the kernel to initialise secret keys
1505 for each process at exec() time, with these keys being
1506 context-switched along with the process.
1508 If the compiler supports the -mbranch-protection or
1509 -msign-return-address flag (e.g. GCC 7 or later), then this option
1510 will also cause the kernel itself to be compiled with return address
1511 protection. In this case, and if the target hardware is known to
1512 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1513 disabled with minimal loss of protection.
1515 The feature is detected at runtime. If the feature is not present in
1516 hardware it will not be advertised to userspace/KVM guest nor will it
1519 If the feature is present on the boot CPU but not on a late CPU, then
1520 the late CPU will be parked. Also, if the boot CPU does not have
1521 address auth and the late CPU has then the late CPU will still boot
1522 but with the feature disabled. On such a system, this option should
1525 This feature works with FUNCTION_GRAPH_TRACER option only if
1526 DYNAMIC_FTRACE_WITH_REGS is enabled.
1528 config CC_HAS_BRANCH_PROT_PAC_RET
1529 # GCC 9 or later, clang 8 or later
1530 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1532 config CC_HAS_SIGN_RETURN_ADDRESS
1534 def_bool $(cc-option,-msign-return-address=all)
1537 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1539 config AS_HAS_CFI_NEGATE_RA_STATE
1540 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1544 menu "ARMv8.4 architectural features"
1546 config ARM64_AMU_EXTN
1547 bool "Enable support for the Activity Monitors Unit CPU extension"
1550 The activity monitors extension is an optional extension introduced
1551 by the ARMv8.4 CPU architecture. This enables support for version 1
1552 of the activity monitors architecture, AMUv1.
1554 To enable the use of this extension on CPUs that implement it, say Y.
1556 Note that for architectural reasons, firmware _must_ implement AMU
1557 support when running on CPUs that present the activity monitors
1558 extension. The required support is present in:
1559 * Version 1.5 and later of the ARM Trusted Firmware
1561 For kernels that have this configuration enabled but boot with broken
1562 firmware, you may need to say N here until the firmware is fixed.
1563 Otherwise you may experience firmware panics or lockups when
1564 accessing the counter registers. Even if you are not observing these
1565 symptoms, the values returned by the register reads might not
1566 correctly reflect reality. Most commonly, the value read will be 0,
1567 indicating that the counter is not enabled.
1569 config AS_HAS_ARMV8_4
1570 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1572 config ARM64_TLB_RANGE
1573 bool "Enable support for tlbi range feature"
1575 depends on AS_HAS_ARMV8_4
1577 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1578 range of input addresses.
1580 The feature introduces new assembly instructions, and they were
1581 support when binutils >= 2.30.
1585 menu "ARMv8.5 architectural features"
1587 config AS_HAS_ARMV8_5
1588 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1591 bool "Branch Target Identification support"
1594 Branch Target Identification (part of the ARMv8.5 Extensions)
1595 provides a mechanism to limit the set of locations to which computed
1596 branch instructions such as BR or BLR can jump.
1598 To make use of BTI on CPUs that support it, say Y.
1600 BTI is intended to provide complementary protection to other control
1601 flow integrity protection mechanisms, such as the Pointer
1602 authentication mechanism provided as part of the ARMv8.3 Extensions.
1603 For this reason, it does not make sense to enable this option without
1604 also enabling support for pointer authentication. Thus, when
1605 enabling this option you should also select ARM64_PTR_AUTH=y.
1607 Userspace binaries must also be specifically compiled to make use of
1608 this mechanism. If you say N here or the hardware does not support
1609 BTI, such binaries can still run, but you get no additional
1610 enforcement of branch destinations.
1612 config ARM64_BTI_KERNEL
1613 bool "Use Branch Target Identification for kernel"
1615 depends on ARM64_BTI
1616 depends on ARM64_PTR_AUTH
1617 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1618 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1619 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1620 depends on !(CC_IS_CLANG && GCOV_KERNEL)
1621 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1623 Build the kernel with Branch Target Identification annotations
1624 and enable enforcement of this for kernel code. When this option
1625 is enabled and the system supports BTI all kernel code including
1626 modular code must have BTI enabled.
1628 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1629 # GCC 9 or later, clang 8 or later
1630 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1633 bool "Enable support for E0PD"
1636 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1637 that EL0 accesses made via TTBR1 always fault in constant time,
1638 providing similar benefits to KASLR as those provided by KPTI, but
1639 with lower overhead and without disrupting legitimate access to
1640 kernel memory such as SPE.
1642 This option enables E0PD for TTBR1 where available.
1645 bool "Enable support for random number generation"
1648 Random number generation (part of the ARMv8.5 Extensions)
1649 provides a high bandwidth, cryptographically secure
1650 hardware random number generator.
1652 config ARM64_AS_HAS_MTE
1653 # Initial support for MTE went in binutils 2.32.0, checked with
1654 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1655 # as a late addition to the final architecture spec (LDGM/STGM)
1656 # is only supported in the newer 2.32.x and 2.33 binutils
1657 # versions, hence the extra "stgm" instruction check below.
1658 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1661 bool "Memory Tagging Extension support"
1663 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1664 depends on AS_HAS_ARMV8_5
1665 depends on AS_HAS_LSE_ATOMICS
1666 # Required for tag checking in the uaccess routines
1667 depends on ARM64_PAN
1668 select ARCH_USES_HIGH_VMA_FLAGS
1670 Memory Tagging (part of the ARMv8.5 Extensions) provides
1671 architectural support for run-time, always-on detection of
1672 various classes of memory error to aid with software debugging
1673 to eliminate vulnerabilities arising from memory-unsafe
1676 This option enables the support for the Memory Tagging
1677 Extension at EL0 (i.e. for userspace).
1679 Selecting this option allows the feature to be detected at
1680 runtime. Any secondary CPU not implementing this feature will
1681 not be allowed a late bring-up.
1683 Userspace binaries that want to use this feature must
1684 explicitly opt in. The mechanism for the userspace is
1687 Documentation/arm64/memory-tagging-extension.rst.
1691 menu "ARMv8.7 architectural features"
1694 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
1696 depends on ARM64_PAN
1698 Enhanced Privileged Access Never (EPAN) allows Privileged
1699 Access Never to be used with Execute-only mappings.
1701 The feature is detected at runtime, and will remain disabled
1702 if the cpu does not implement the feature.
1706 bool "ARM Scalable Vector Extension support"
1709 The Scalable Vector Extension (SVE) is an extension to the AArch64
1710 execution state which complements and extends the SIMD functionality
1711 of the base architecture to support much larger vectors and to enable
1712 additional vectorisation opportunities.
1714 To enable use of this extension on CPUs that implement it, say Y.
1716 On CPUs that support the SVE2 extensions, this option will enable
1719 Note that for architectural reasons, firmware _must_ implement SVE
1720 support when running on SVE capable hardware. The required support
1723 * version 1.5 and later of the ARM Trusted Firmware
1724 * the AArch64 boot wrapper since commit 5e1261e08abf
1725 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1727 For other firmware implementations, consult the firmware documentation
1730 If you need the kernel to boot on SVE-capable hardware with broken
1731 firmware, you may need to say N here until you get your firmware
1732 fixed. Otherwise, you may experience firmware panics or lockups when
1733 booting the kernel. If unsure and you are not observing these
1734 symptoms, you should assume that it is safe to say Y.
1736 config ARM64_MODULE_PLTS
1737 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1739 select HAVE_MOD_ARCH_SPECIFIC
1741 Allocate PLTs when loading modules so that jumps and calls whose
1742 targets are too far away for their relative offsets to be encoded
1743 in the instructions themselves can be bounced via veneers in the
1744 module's PLT. This allows modules to be allocated in the generic
1745 vmalloc area after the dedicated module memory area has been
1748 When running with address space randomization (KASLR), the module
1749 region itself may be too far away for ordinary relative jumps and
1750 calls, and so in that case, module PLTs are required and cannot be
1753 Specific errata workaround(s) might also force module PLTs to be
1754 enabled (ARM64_ERRATUM_843419).
1756 config ARM64_PSEUDO_NMI
1757 bool "Support for NMI-like interrupts"
1760 Adds support for mimicking Non-Maskable Interrupts through the use of
1761 GIC interrupt priority. This support requires version 3 or later of
1764 This high priority configuration for interrupts needs to be
1765 explicitly enabled by setting the kernel parameter
1766 "irqchip.gicv3_pseudo_nmi" to 1.
1771 config ARM64_DEBUG_PRIORITY_MASKING
1772 bool "Debug interrupt priority masking"
1774 This adds runtime checks to functions enabling/disabling
1775 interrupts when using priority masking. The additional checks verify
1776 the validity of ICC_PMR_EL1 when calling concerned functions.
1782 bool "Build a relocatable kernel image" if EXPERT
1783 select ARCH_HAS_RELR
1786 This builds the kernel as a Position Independent Executable (PIE),
1787 which retains all relocation metadata required to relocate the
1788 kernel binary at runtime to a different virtual address than the
1789 address it was linked at.
1790 Since AArch64 uses the RELA relocation format, this requires a
1791 relocation pass at runtime even if the kernel is loaded at the
1792 same address it was linked at.
1794 config RANDOMIZE_BASE
1795 bool "Randomize the address of the kernel image"
1796 select ARM64_MODULE_PLTS if MODULES
1799 Randomizes the virtual address at which the kernel image is
1800 loaded, as a security feature that deters exploit attempts
1801 relying on knowledge of the location of kernel internals.
1803 It is the bootloader's job to provide entropy, by passing a
1804 random u64 value in /chosen/kaslr-seed at kernel entry.
1806 When booting via the UEFI stub, it will invoke the firmware's
1807 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1808 to the kernel proper. In addition, it will randomise the physical
1809 location of the kernel Image as well.
1813 config RANDOMIZE_MODULE_REGION_FULL
1814 bool "Randomize the module region over a 4 GB range"
1815 depends on RANDOMIZE_BASE
1818 Randomizes the location of the module region inside a 4 GB window
1819 covering the core kernel. This way, it is less likely for modules
1820 to leak information about the location of core kernel data structures
1821 but it does imply that function calls between modules and the core
1822 kernel will need to be resolved via veneers in the module PLT.
1824 When this option is not set, the module region will be randomized over
1825 a limited range that contains the [_stext, _etext] interval of the
1826 core kernel, so branch relocations are always in range.
1828 config CC_HAVE_STACKPROTECTOR_SYSREG
1829 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1831 config STACKPROTECTOR_PER_TASK
1833 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1839 config ARM64_ACPI_PARKING_PROTOCOL
1840 bool "Enable support for the ARM64 ACPI parking protocol"
1843 Enable support for the ARM64 ACPI parking protocol. If disabled
1844 the kernel will not allow booting through the ARM64 ACPI parking
1845 protocol even if the corresponding data is present in the ACPI
1849 string "Default kernel command string"
1852 Provide a set of default command-line options at build time by
1853 entering them here. As a minimum, you should specify the the
1854 root device (e.g. root=/dev/nfs).
1857 prompt "Kernel command line type" if CMDLINE != ""
1858 default CMDLINE_FROM_BOOTLOADER
1860 Choose how the kernel will handle the provided default kernel
1861 command line string.
1863 config CMDLINE_FROM_BOOTLOADER
1864 bool "Use bootloader kernel arguments if available"
1866 Uses the command-line options passed by the boot loader. If
1867 the boot loader doesn't provide any, the default kernel command
1868 string provided in CMDLINE will be used.
1870 config CMDLINE_FORCE
1871 bool "Always use the default kernel command string"
1873 Always use the default kernel command string, even if the boot
1874 loader passes other arguments to the kernel.
1875 This is useful if you cannot or don't want to change the
1876 command-line options your boot loader passes to the kernel.
1884 bool "UEFI runtime support"
1885 depends on OF && !CPU_BIG_ENDIAN
1886 depends on KERNEL_MODE_NEON
1887 select ARCH_SUPPORTS_ACPI
1890 select EFI_PARAMS_FROM_FDT
1891 select EFI_RUNTIME_WRAPPERS
1893 select EFI_GENERIC_STUB
1894 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
1897 This option provides support for runtime services provided
1898 by UEFI firmware (such as non-volatile variables, realtime
1899 clock, and platform reset). A UEFI stub is also provided to
1900 allow the kernel to be booted as an EFI application. This
1901 is only useful on systems that have UEFI firmware.
1904 bool "Enable support for SMBIOS (DMI) tables"
1908 This enables SMBIOS/DMI feature for systems.
1910 This option is only useful on systems that have UEFI firmware.
1911 However, even with this option, the resultant kernel should
1912 continue to boot on existing non-UEFI platforms.
1916 config SYSVIPC_COMPAT
1918 depends on COMPAT && SYSVIPC
1920 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1922 depends on HUGETLB_PAGE && MIGRATION
1924 config ARCH_ENABLE_THP_MIGRATION
1926 depends on TRANSPARENT_HUGEPAGE
1928 menu "Power management options"
1930 source "kernel/power/Kconfig"
1932 config ARCH_HIBERNATION_POSSIBLE
1936 config ARCH_HIBERNATION_HEADER
1938 depends on HIBERNATION
1940 config ARCH_SUSPEND_POSSIBLE
1945 menu "CPU Power Management"
1947 source "drivers/cpuidle/Kconfig"
1949 source "drivers/cpufreq/Kconfig"
1953 source "drivers/firmware/Kconfig"
1955 source "drivers/acpi/Kconfig"
1957 source "arch/arm64/kvm/Kconfig"
1960 source "arch/arm64/crypto/Kconfig"