1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_WX
13 select ARCH_BINFMT_ELF_STATE
14 select ARCH_HAS_DEBUG_VIRTUAL
15 select ARCH_HAS_DEBUG_VM_PGTABLE
16 select ARCH_HAS_DMA_PREP_COHERENT
17 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
18 select ARCH_HAS_FAST_MULTIPLIER
19 select ARCH_HAS_FORTIFY_SOURCE
20 select ARCH_HAS_GCOV_PROFILE_ALL
21 select ARCH_HAS_GIGANTIC_PAGE
23 select ARCH_HAS_KEEPINITRD
24 select ARCH_HAS_MEMBARRIER_SYNC_CORE
25 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
26 select ARCH_HAS_PTE_DEVMAP
27 select ARCH_HAS_PTE_SPECIAL
28 select ARCH_HAS_SETUP_DMA_OPS
29 select ARCH_HAS_SET_DIRECT_MAP
30 select ARCH_HAS_SET_MEMORY
32 select ARCH_HAS_STRICT_KERNEL_RWX
33 select ARCH_HAS_STRICT_MODULE_RWX
34 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
35 select ARCH_HAS_SYNC_DMA_FOR_CPU
36 select ARCH_HAS_SYSCALL_WRAPPER
37 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
38 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
39 select ARCH_HAVE_ELF_PROT
40 select ARCH_HAVE_NMI_SAFE_CMPXCHG
41 select ARCH_INLINE_READ_LOCK if !PREEMPTION
42 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
43 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
44 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
45 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
46 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
47 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
48 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
49 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
50 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
51 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
52 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
53 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
54 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
55 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
56 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
57 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
58 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
59 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
60 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
61 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
62 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
63 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
64 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
65 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
66 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
67 select ARCH_KEEP_MEMBLOCK
68 select ARCH_USE_CMPXCHG_LOCKREF
69 select ARCH_USE_GNU_PROPERTY
70 select ARCH_USE_QUEUED_RWLOCKS
71 select ARCH_USE_QUEUED_SPINLOCKS
72 select ARCH_USE_SYM_ANNOTATIONS
73 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
74 select ARCH_SUPPORTS_MEMORY_FAILURE
75 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
76 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
77 select ARCH_SUPPORTS_LTO_CLANG_THIN
78 select ARCH_SUPPORTS_CFI_CLANG
79 select ARCH_SUPPORTS_ATOMIC_RMW
80 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG)
81 select ARCH_SUPPORTS_NUMA_BALANCING
82 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
83 select ARCH_WANT_DEFAULT_BPF_JIT
84 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
85 select ARCH_WANT_FRAME_POINTERS
86 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
87 select ARCH_WANT_LD_ORPHAN_WARN
88 select ARCH_HAS_UBSAN_SANITIZE_ALL
92 select AUDIT_ARCH_COMPAT_GENERIC
93 select ARM_GIC_V2M if PCI
95 select ARM_GIC_V3_ITS if PCI
97 select BUILDTIME_TABLE_SORT
98 select CLONE_BACKWARDS
100 select CPU_PM if (SUSPEND || CPU_IDLE)
102 select DCACHE_WORD_ACCESS
103 select DMA_DIRECT_REMAP
106 select GENERIC_ALLOCATOR
107 select GENERIC_ARCH_TOPOLOGY
108 select GENERIC_CLOCKEVENTS_BROADCAST
109 select GENERIC_CPU_AUTOPROBE
110 select GENERIC_CPU_VULNERABILITIES
111 select GENERIC_EARLY_IOREMAP
112 select GENERIC_FIND_FIRST_BIT
113 select GENERIC_IDLE_POLL_SETUP
114 select GENERIC_IRQ_IPI
115 select GENERIC_IRQ_PROBE
116 select GENERIC_IRQ_SHOW
117 select GENERIC_IRQ_SHOW_LEVEL
118 select GENERIC_LIB_DEVMEM_IS_ALLOWED
119 select GENERIC_PCI_IOMAP
120 select GENERIC_PTDUMP
121 select GENERIC_SCHED_CLOCK
122 select GENERIC_SMP_IDLE_THREAD
123 select GENERIC_STRNCPY_FROM_USER
124 select GENERIC_STRNLEN_USER
125 select GENERIC_TIME_VSYSCALL
126 select GENERIC_GETTIMEOFDAY
127 select GENERIC_VDSO_TIME_NS
128 select HANDLE_DOMAIN_IRQ
129 select HARDIRQS_SW_RESEND
133 select HAVE_ACPI_APEI if (ACPI && EFI)
134 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
135 select HAVE_ARCH_AUDITSYSCALL
136 select HAVE_ARCH_BITREVERSE
137 select HAVE_ARCH_COMPILER_H
138 select HAVE_ARCH_HUGE_VMAP
139 select HAVE_ARCH_JUMP_LABEL
140 select HAVE_ARCH_JUMP_LABEL_RELATIVE
141 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
142 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
143 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
144 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
145 select HAVE_ARCH_KFENCE
146 select HAVE_ARCH_KGDB
147 select HAVE_ARCH_MMAP_RND_BITS
148 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
149 select HAVE_ARCH_PFN_VALID
150 select HAVE_ARCH_PREL32_RELOCATIONS
151 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
152 select HAVE_ARCH_SECCOMP_FILTER
153 select HAVE_ARCH_STACKLEAK
154 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
155 select HAVE_ARCH_TRACEHOOK
156 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
157 select HAVE_ARCH_VMAP_STACK
158 select HAVE_ARM_SMCCC
159 select HAVE_ASM_MODVERSIONS
161 select HAVE_C_RECORDMCOUNT
162 select HAVE_CMPXCHG_DOUBLE
163 select HAVE_CMPXCHG_LOCAL
164 select HAVE_CONTEXT_TRACKING
165 select HAVE_DEBUG_BUGVERBOSE
166 select HAVE_DEBUG_KMEMLEAK
167 select HAVE_DMA_CONTIGUOUS
168 select HAVE_DYNAMIC_FTRACE
169 select HAVE_DYNAMIC_FTRACE_WITH_REGS \
170 if $(cc-option,-fpatchable-function-entry=2)
171 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
172 if DYNAMIC_FTRACE_WITH_REGS
173 select HAVE_EFFICIENT_UNALIGNED_ACCESS
175 select HAVE_FTRACE_MCOUNT_RECORD
176 select HAVE_FUNCTION_TRACER
177 select HAVE_FUNCTION_ERROR_INJECTION
178 select HAVE_FUNCTION_GRAPH_TRACER
179 select HAVE_GCC_PLUGINS
180 select HAVE_HW_BREAKPOINT if PERF_EVENTS
181 select HAVE_IRQ_TIME_ACCOUNTING
183 select HAVE_PATA_PLATFORM
184 select HAVE_PERF_EVENTS
185 select HAVE_PERF_REGS
186 select HAVE_PERF_USER_STACK_DUMP
187 select HAVE_REGS_AND_STACK_ACCESS_API
188 select HAVE_FUNCTION_ARG_ACCESS_API
189 select HAVE_FUTEX_CMPXCHG if FUTEX
190 select MMU_GATHER_RCU_TABLE_FREE
192 select HAVE_STACKPROTECTOR
193 select HAVE_SYSCALL_TRACEPOINTS
195 select HAVE_KRETPROBES
196 select HAVE_GENERIC_VDSO
197 select IOMMU_DMA if IOMMU_SUPPORT
199 select IRQ_FORCED_THREADING
200 select KASAN_VMALLOC if KASAN_GENERIC
201 select MODULES_USE_ELF_RELA
202 select NEED_DMA_MAP_STATE
203 select NEED_SG_DMA_LENGTH
205 select OF_EARLY_FLATTREE
206 select PCI_DOMAINS_GENERIC if PCI
207 select PCI_ECAM if (ACPI && PCI)
208 select PCI_SYSCALL if PCI
213 select SYSCTL_EXCEPTION_TRACE
214 select THREAD_INFO_IN_TASK
216 ARM 64-bit (AArch64) Linux support.
224 config ARM64_PAGE_SHIFT
226 default 16 if ARM64_64K_PAGES
227 default 14 if ARM64_16K_PAGES
230 config ARM64_CONT_PTE_SHIFT
232 default 5 if ARM64_64K_PAGES
233 default 7 if ARM64_16K_PAGES
236 config ARM64_CONT_PMD_SHIFT
238 default 5 if ARM64_64K_PAGES
239 default 5 if ARM64_16K_PAGES
242 config ARCH_MMAP_RND_BITS_MIN
243 default 14 if ARM64_64K_PAGES
244 default 16 if ARM64_16K_PAGES
247 # max bits determined by the following formula:
248 # VA_BITS - PAGE_SHIFT - 3
249 config ARCH_MMAP_RND_BITS_MAX
250 default 19 if ARM64_VA_BITS=36
251 default 24 if ARM64_VA_BITS=39
252 default 27 if ARM64_VA_BITS=42
253 default 30 if ARM64_VA_BITS=47
254 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
255 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
256 default 33 if ARM64_VA_BITS=48
257 default 14 if ARM64_64K_PAGES
258 default 16 if ARM64_16K_PAGES
261 config ARCH_MMAP_RND_COMPAT_BITS_MIN
262 default 7 if ARM64_64K_PAGES
263 default 9 if ARM64_16K_PAGES
266 config ARCH_MMAP_RND_COMPAT_BITS_MAX
272 config STACKTRACE_SUPPORT
275 config ILLEGAL_POINTER_VALUE
277 default 0xdead000000000000
279 config LOCKDEP_SUPPORT
282 config TRACE_IRQFLAGS_SUPPORT
289 config GENERIC_BUG_RELATIVE_POINTERS
291 depends on GENERIC_BUG
293 config GENERIC_HWEIGHT
299 config GENERIC_CALIBRATE_DELAY
303 bool "Support DMA zone" if EXPERT
307 bool "Support DMA32 zone" if EXPERT
310 config ARCH_ENABLE_MEMORY_HOTPLUG
313 config ARCH_ENABLE_MEMORY_HOTREMOVE
319 config KERNEL_MODE_NEON
322 config FIX_EARLYCON_MEM
325 config PGTABLE_LEVELS
327 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
328 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
329 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
330 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
331 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
332 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
334 config ARCH_SUPPORTS_UPROBES
337 config ARCH_PROC_KCORE_TEXT
340 config BROKEN_GAS_INST
341 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
343 config KASAN_SHADOW_OFFSET
345 depends on KASAN_GENERIC || KASAN_SW_TAGS
346 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
347 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
348 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
349 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
350 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
351 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
352 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
353 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
354 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
355 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
356 default 0xffffffffffffffff
358 source "arch/arm64/Kconfig.platforms"
360 menu "Kernel Features"
362 menu "ARM errata workarounds via the alternatives framework"
364 config ARM64_WORKAROUND_CLEAN_CACHE
367 config ARM64_ERRATUM_826319
368 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
370 select ARM64_WORKAROUND_CLEAN_CACHE
372 This option adds an alternative code sequence to work around ARM
373 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
374 AXI master interface and an L2 cache.
376 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
377 and is unable to accept a certain write via this interface, it will
378 not progress on read data presented on the read data channel and the
381 The workaround promotes data cache clean instructions to
382 data cache clean-and-invalidate.
383 Please note that this does not necessarily enable the workaround,
384 as it depends on the alternative framework, which will only patch
385 the kernel if an affected CPU is detected.
389 config ARM64_ERRATUM_827319
390 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
392 select ARM64_WORKAROUND_CLEAN_CACHE
394 This option adds an alternative code sequence to work around ARM
395 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
396 master interface and an L2 cache.
398 Under certain conditions this erratum can cause a clean line eviction
399 to occur at the same time as another transaction to the same address
400 on the AMBA 5 CHI interface, which can cause data corruption if the
401 interconnect reorders the two transactions.
403 The workaround promotes data cache clean instructions to
404 data cache clean-and-invalidate.
405 Please note that this does not necessarily enable the workaround,
406 as it depends on the alternative framework, which will only patch
407 the kernel if an affected CPU is detected.
411 config ARM64_ERRATUM_824069
412 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
414 select ARM64_WORKAROUND_CLEAN_CACHE
416 This option adds an alternative code sequence to work around ARM
417 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
418 to a coherent interconnect.
420 If a Cortex-A53 processor is executing a store or prefetch for
421 write instruction at the same time as a processor in another
422 cluster is executing a cache maintenance operation to the same
423 address, then this erratum might cause a clean cache line to be
424 incorrectly marked as dirty.
426 The workaround promotes data cache clean instructions to
427 data cache clean-and-invalidate.
428 Please note that this option does not necessarily enable the
429 workaround, as it depends on the alternative framework, which will
430 only patch the kernel if an affected CPU is detected.
434 config ARM64_ERRATUM_819472
435 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
437 select ARM64_WORKAROUND_CLEAN_CACHE
439 This option adds an alternative code sequence to work around ARM
440 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
441 present when it is connected to a coherent interconnect.
443 If the processor is executing a load and store exclusive sequence at
444 the same time as a processor in another cluster is executing a cache
445 maintenance operation to the same address, then this erratum might
446 cause data corruption.
448 The workaround promotes data cache clean instructions to
449 data cache clean-and-invalidate.
450 Please note that this does not necessarily enable the workaround,
451 as it depends on the alternative framework, which will only patch
452 the kernel if an affected CPU is detected.
456 config ARM64_ERRATUM_832075
457 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
460 This option adds an alternative code sequence to work around ARM
461 erratum 832075 on Cortex-A57 parts up to r1p2.
463 Affected Cortex-A57 parts might deadlock when exclusive load/store
464 instructions to Write-Back memory are mixed with Device loads.
466 The workaround is to promote device loads to use Load-Acquire
468 Please note that this does not necessarily enable the workaround,
469 as it depends on the alternative framework, which will only patch
470 the kernel if an affected CPU is detected.
474 config ARM64_ERRATUM_834220
475 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
479 This option adds an alternative code sequence to work around ARM
480 erratum 834220 on Cortex-A57 parts up to r1p2.
482 Affected Cortex-A57 parts might report a Stage 2 translation
483 fault as the result of a Stage 1 fault for load crossing a
484 page boundary when there is a permission or device memory
485 alignment fault at Stage 1 and a translation fault at Stage 2.
487 The workaround is to verify that the Stage 1 translation
488 doesn't generate a fault before handling the Stage 2 fault.
489 Please note that this does not necessarily enable the workaround,
490 as it depends on the alternative framework, which will only patch
491 the kernel if an affected CPU is detected.
495 config ARM64_ERRATUM_845719
496 bool "Cortex-A53: 845719: a load might read incorrect data"
500 This option adds an alternative code sequence to work around ARM
501 erratum 845719 on Cortex-A53 parts up to r0p4.
503 When running a compat (AArch32) userspace on an affected Cortex-A53
504 part, a load at EL0 from a virtual address that matches the bottom 32
505 bits of the virtual address used by a recent load at (AArch64) EL1
506 might return incorrect data.
508 The workaround is to write the contextidr_el1 register on exception
509 return to a 32-bit task.
510 Please note that this does not necessarily enable the workaround,
511 as it depends on the alternative framework, which will only patch
512 the kernel if an affected CPU is detected.
516 config ARM64_ERRATUM_843419
517 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
519 select ARM64_MODULE_PLTS if MODULES
521 This option links the kernel with '--fix-cortex-a53-843419' and
522 enables PLT support to replace certain ADRP instructions, which can
523 cause subsequent memory accesses to use an incorrect address on
524 Cortex-A53 parts up to r0p4.
528 config ARM64_ERRATUM_1024718
529 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
532 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
534 Affected Cortex-A55 cores (all revisions) could cause incorrect
535 update of the hardware dirty bit when the DBM/AP bits are updated
536 without a break-before-make. The workaround is to disable the usage
537 of hardware DBM locally on the affected cores. CPUs not affected by
538 this erratum will continue to use the feature.
542 config ARM64_ERRATUM_1418040
543 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
547 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
548 errata 1188873 and 1418040.
550 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
551 cause register corruption when accessing the timer registers
552 from AArch32 userspace.
556 config ARM64_WORKAROUND_SPECULATIVE_AT
559 config ARM64_ERRATUM_1165522
560 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
562 select ARM64_WORKAROUND_SPECULATIVE_AT
564 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
566 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
567 corrupted TLBs by speculating an AT instruction during a guest
572 config ARM64_ERRATUM_1319367
573 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
575 select ARM64_WORKAROUND_SPECULATIVE_AT
577 This option adds work arounds for ARM Cortex-A57 erratum 1319537
578 and A72 erratum 1319367
580 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
581 speculating an AT instruction during a guest context switch.
585 config ARM64_ERRATUM_1530923
586 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
588 select ARM64_WORKAROUND_SPECULATIVE_AT
590 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
592 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
593 corrupted TLBs by speculating an AT instruction during a guest
598 config ARM64_WORKAROUND_REPEAT_TLBI
601 config ARM64_ERRATUM_1286807
602 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
604 select ARM64_WORKAROUND_REPEAT_TLBI
606 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
608 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
609 address for a cacheable mapping of a location is being
610 accessed by a core while another core is remapping the virtual
611 address to a new physical page using the recommended
612 break-before-make sequence, then under very rare circumstances
613 TLBI+DSB completes before a read using the translation being
614 invalidated has been observed by other observers. The
615 workaround repeats the TLBI+DSB operation.
617 config ARM64_ERRATUM_1463225
618 bool "Cortex-A76: Software Step might prevent interrupt recognition"
621 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
623 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
624 of a system call instruction (SVC) can prevent recognition of
625 subsequent interrupts when software stepping is disabled in the
626 exception handler of the system call and either kernel debugging
627 is enabled or VHE is in use.
629 Work around the erratum by triggering a dummy step exception
630 when handling a system call from a task that is being stepped
631 in a VHE configuration of the kernel.
635 config ARM64_ERRATUM_1542419
636 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
639 This option adds a workaround for ARM Neoverse-N1 erratum
642 Affected Neoverse-N1 cores could execute a stale instruction when
643 modified by another CPU. The workaround depends on a firmware
646 Workaround the issue by hiding the DIC feature from EL0. This
647 forces user-space to perform cache maintenance.
651 config ARM64_ERRATUM_1508412
652 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
655 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
657 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
658 of a store-exclusive or read of PAR_EL1 and a load with device or
659 non-cacheable memory attributes. The workaround depends on a firmware
662 KVM guests must also have the workaround implemented or they can
665 Work around the issue by inserting DMB SY barriers around PAR_EL1
666 register reads and warning KVM users. The DMB barrier is sufficient
667 to prevent a speculative PAR_EL1 read.
671 config CAVIUM_ERRATUM_22375
672 bool "Cavium erratum 22375, 24313"
675 Enable workaround for errata 22375 and 24313.
677 This implements two gicv3-its errata workarounds for ThunderX. Both
678 with a small impact affecting only ITS table allocation.
680 erratum 22375: only alloc 8MB table size
681 erratum 24313: ignore memory access type
683 The fixes are in ITS initialization and basically ignore memory access
684 type and table size provided by the TYPER and BASER registers.
688 config CAVIUM_ERRATUM_23144
689 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
693 ITS SYNC command hang for cross node io and collections/cpu mapping.
697 config CAVIUM_ERRATUM_23154
698 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
701 The gicv3 of ThunderX requires a modified version for
702 reading the IAR status to ensure data synchronization
703 (access to icc_iar1_el1 is not sync'ed before and after).
707 config CAVIUM_ERRATUM_27456
708 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
711 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
712 instructions may cause the icache to become corrupted if it
713 contains data for a non-current ASID. The fix is to
714 invalidate the icache when changing the mm context.
718 config CAVIUM_ERRATUM_30115
719 bool "Cavium erratum 30115: Guest may disable interrupts in host"
722 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
723 1.2, and T83 Pass 1.0, KVM guest execution may disable
724 interrupts in host. Trapping both GICv3 group-0 and group-1
725 accesses sidesteps the issue.
729 config CAVIUM_TX2_ERRATUM_219
730 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
733 On Cavium ThunderX2, a load, store or prefetch instruction between a
734 TTBR update and the corresponding context synchronizing operation can
735 cause a spurious Data Abort to be delivered to any hardware thread in
738 Work around the issue by avoiding the problematic code sequence and
739 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
740 trap handler performs the corresponding register access, skips the
741 instruction and ensures context synchronization by virtue of the
746 config FUJITSU_ERRATUM_010001
747 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
750 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
751 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
752 accesses may cause undefined fault (Data abort, DFSC=0b111111).
753 This fault occurs under a specific hardware condition when a
754 load/store instruction performs an address translation using:
755 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
756 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
757 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
758 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
760 The workaround is to ensure these bits are clear in TCR_ELx.
761 The workaround only affects the Fujitsu-A64FX.
765 config HISILICON_ERRATUM_161600802
766 bool "Hip07 161600802: Erroneous redistributor VLPI base"
769 The HiSilicon Hip07 SoC uses the wrong redistributor base
770 when issued ITS commands such as VMOVP and VMAPP, and requires
771 a 128kB offset to be applied to the target address in this commands.
775 config QCOM_FALKOR_ERRATUM_1003
776 bool "Falkor E1003: Incorrect translation due to ASID change"
779 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
780 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
781 in TTBR1_EL1, this situation only occurs in the entry trampoline and
782 then only for entries in the walk cache, since the leaf translation
783 is unchanged. Work around the erratum by invalidating the walk cache
784 entries for the trampoline before entering the kernel proper.
786 config QCOM_FALKOR_ERRATUM_1009
787 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
789 select ARM64_WORKAROUND_REPEAT_TLBI
791 On Falkor v1, the CPU may prematurely complete a DSB following a
792 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
793 one more time to fix the issue.
797 config QCOM_QDF2400_ERRATUM_0065
798 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
801 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
802 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
803 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
807 config QCOM_FALKOR_ERRATUM_E1041
808 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
811 Falkor CPU may speculatively fetch instructions from an improper
812 memory location when MMU translation is changed from SCTLR_ELn[M]=1
813 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
817 config NVIDIA_CARMEL_CNP_ERRATUM
818 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
821 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
822 invalidate shared TLB entries installed by a different core, as it would
823 on standard ARM cores.
827 config SOCIONEXT_SYNQUACER_PREITS
828 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
831 Socionext Synquacer SoCs implement a separate h/w block to generate
832 MSI doorbell writes with non-zero values for the device ID.
841 default ARM64_4K_PAGES
843 Page size (translation granule) configuration.
845 config ARM64_4K_PAGES
848 This feature enables 4KB pages support.
850 config ARM64_16K_PAGES
853 The system will use 16KB pages support. AArch32 emulation
854 requires applications compiled with 16K (or a multiple of 16K)
857 config ARM64_64K_PAGES
860 This feature enables 64KB pages support (4KB by default)
861 allowing only two levels of page tables and faster TLB
862 look-up. AArch32 emulation requires applications compiled
863 with 64K aligned segments.
868 prompt "Virtual address space size"
869 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
870 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
871 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
873 Allows choosing one of multiple possible virtual address
874 space sizes. The level of translation table is determined by
875 a combination of page size and virtual address space size.
877 config ARM64_VA_BITS_36
878 bool "36-bit" if EXPERT
879 depends on ARM64_16K_PAGES
881 config ARM64_VA_BITS_39
883 depends on ARM64_4K_PAGES
885 config ARM64_VA_BITS_42
887 depends on ARM64_64K_PAGES
889 config ARM64_VA_BITS_47
891 depends on ARM64_16K_PAGES
893 config ARM64_VA_BITS_48
896 config ARM64_VA_BITS_52
898 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
900 Enable 52-bit virtual addressing for userspace when explicitly
901 requested via a hint to mmap(). The kernel will also use 52-bit
902 virtual addresses for its own mappings (provided HW support for
903 this feature is available, otherwise it reverts to 48-bit).
905 NOTE: Enabling 52-bit virtual addressing in conjunction with
906 ARMv8.3 Pointer Authentication will result in the PAC being
907 reduced from 7 bits to 3 bits, which may have a significant
908 impact on its susceptibility to brute-force attacks.
910 If unsure, select 48-bit virtual addressing instead.
914 config ARM64_FORCE_52BIT
915 bool "Force 52-bit virtual addresses for userspace"
916 depends on ARM64_VA_BITS_52 && EXPERT
918 For systems with 52-bit userspace VAs enabled, the kernel will attempt
919 to maintain compatibility with older software by providing 48-bit VAs
920 unless a hint is supplied to mmap.
922 This configuration option disables the 48-bit compatibility logic, and
923 forces all userspace addresses to be 52-bit on HW that supports it. One
924 should only enable this configuration option for stress testing userspace
925 memory management code. If unsure say N here.
929 default 36 if ARM64_VA_BITS_36
930 default 39 if ARM64_VA_BITS_39
931 default 42 if ARM64_VA_BITS_42
932 default 47 if ARM64_VA_BITS_47
933 default 48 if ARM64_VA_BITS_48
934 default 52 if ARM64_VA_BITS_52
937 prompt "Physical address space size"
938 default ARM64_PA_BITS_48
940 Choose the maximum physical address range that the kernel will
943 config ARM64_PA_BITS_48
946 config ARM64_PA_BITS_52
947 bool "52-bit (ARMv8.2)"
948 depends on ARM64_64K_PAGES
949 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
951 Enable support for a 52-bit physical address space, introduced as
952 part of the ARMv8.2-LPA extension.
954 With this enabled, the kernel will also continue to work on CPUs that
955 do not support ARMv8.2-LPA, but with some added memory overhead (and
956 minor performance overhead).
962 default 48 if ARM64_PA_BITS_48
963 default 52 if ARM64_PA_BITS_52
967 default CPU_LITTLE_ENDIAN
969 Select the endianness of data accesses performed by the CPU. Userspace
970 applications will need to be compiled and linked for the endianness
971 that is selected here.
973 config CPU_BIG_ENDIAN
974 bool "Build big-endian kernel"
975 depends on !LD_IS_LLD || LLD_VERSION >= 130000
977 Say Y if you plan on running a kernel with a big-endian userspace.
979 config CPU_LITTLE_ENDIAN
980 bool "Build little-endian kernel"
982 Say Y if you plan on running a kernel with a little-endian userspace.
983 This is usually the case for distributions targeting arm64.
988 bool "Multi-core scheduler support"
990 Multi-core scheduler support improves the CPU scheduler's decision
991 making when dealing with multi-core CPU chips at a cost of slightly
992 increased overhead in some places. If unsure say N here.
995 bool "SMT scheduler support"
997 Improves the CPU scheduler's decision making when dealing with
998 MultiThreading at a cost of slightly increased overhead in some
999 places. If unsure say N here.
1002 int "Maximum number of CPUs (2-4096)"
1007 bool "Support for hot-pluggable CPUs"
1008 select GENERIC_IRQ_MIGRATION
1010 Say Y here to experiment with turning CPUs off and on. CPUs
1011 can be controlled through /sys/devices/system/cpu.
1013 # Common NUMA Features
1015 bool "NUMA Memory Allocation and Scheduler Support"
1016 select GENERIC_ARCH_NUMA
1017 select ACPI_NUMA if ACPI
1020 Enable NUMA (Non-Uniform Memory Access) support.
1022 The kernel will try to allocate memory used by a CPU on the
1023 local memory of the CPU and add some more
1024 NUMA awareness to the kernel.
1027 int "Maximum NUMA Nodes (as a power of 2)"
1030 depends on NEED_MULTIPLE_NODES
1032 Specify the maximum number of NUMA Nodes available on the target
1033 system. Increases memory reserved to accommodate various tables.
1035 config USE_PERCPU_NUMA_NODE_ID
1039 config HAVE_SETUP_PER_CPU_AREA
1043 config NEED_PER_CPU_EMBED_FIRST_CHUNK
1047 config HOLES_IN_ZONE
1050 source "kernel/Kconfig.hz"
1052 config ARCH_SPARSEMEM_ENABLE
1054 select SPARSEMEM_VMEMMAP_ENABLE
1056 config ARCH_SPARSEMEM_DEFAULT
1057 def_bool ARCH_SPARSEMEM_ENABLE
1059 config ARCH_SELECT_MEMORY_MODEL
1060 def_bool ARCH_SPARSEMEM_ENABLE
1062 config ARCH_FLATMEM_ENABLE
1065 config HW_PERF_EVENTS
1069 config SYS_SUPPORTS_HUGETLBFS
1072 config ARCH_HAS_CACHE_LINE_SIZE
1075 config ARCH_HAS_FILTER_PGPROT
1078 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
1079 def_bool y if PGTABLE_LEVELS > 2
1081 # Supported by clang >= 7.0
1082 config CC_HAVE_SHADOW_CALL_STACK
1083 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1086 bool "Enable paravirtualization code"
1088 This changes the kernel so it can modify itself when it is run
1089 under a hypervisor, potentially improving performance significantly
1090 over full virtualization.
1092 config PARAVIRT_TIME_ACCOUNTING
1093 bool "Paravirtual steal time accounting"
1096 Select this option to enable fine granularity task steal time
1097 accounting. Time spent executing other tasks in parallel with
1098 the current vCPU is discounted from the vCPU power. To account for
1099 that, there can be a small performance impact.
1101 If in doubt, say N here.
1104 depends on PM_SLEEP_SMP
1106 bool "kexec system call"
1108 kexec is a system call that implements the ability to shutdown your
1109 current kernel, and to start another kernel. It is like a reboot
1110 but it is independent of the system firmware. And like a reboot
1111 you can start any kernel with it, not just Linux.
1114 bool "kexec file based system call"
1117 This is new version of kexec system call. This system call is
1118 file based and takes file descriptors as system call argument
1119 for kernel and initramfs as opposed to list of segments as
1120 accepted by previous system call.
1123 bool "Verify kernel signature during kexec_file_load() syscall"
1124 depends on KEXEC_FILE
1126 Select this option to verify a signature with loaded kernel
1127 image. If configured, any attempt of loading a image without
1128 valid signature will fail.
1130 In addition to that option, you need to enable signature
1131 verification for the corresponding kernel image type being
1132 loaded in order for this to work.
1134 config KEXEC_IMAGE_VERIFY_SIG
1135 bool "Enable Image signature verification support"
1137 depends on KEXEC_SIG
1138 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1140 Enable Image signature verification support.
1142 comment "Support for PE file signature verification disabled"
1143 depends on KEXEC_SIG
1144 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1147 bool "Build kdump crash kernel"
1149 Generate crash dump after being started by kexec. This should
1150 be normally only set in special crash dump kernels which are
1151 loaded in the main kernel with kexec-tools into a specially
1152 reserved region and then later executed after a crash by
1155 For more details see Documentation/admin-guide/kdump/kdump.rst
1159 depends on HIBERNATION
1166 bool "Xen guest support on ARM64"
1167 depends on ARM64 && OF
1171 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1173 config FORCE_MAX_ZONEORDER
1175 default "14" if ARM64_64K_PAGES
1176 default "12" if ARM64_16K_PAGES
1179 The kernel memory allocator divides physically contiguous memory
1180 blocks into "zones", where each zone is a power of two number of
1181 pages. This option selects the largest power of two that the kernel
1182 keeps in the memory allocator. If you need to allocate very large
1183 blocks of physically contiguous memory, then you may need to
1184 increase this value.
1186 This config option is actually maximum order plus one. For example,
1187 a value of 11 means that the largest free memory block is 2^10 pages.
1189 We make sure that we can allocate upto a HugePage size for each configuration.
1191 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1193 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1194 4M allocations matching the default size used by generic code.
1196 config UNMAP_KERNEL_AT_EL0
1197 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1200 Speculation attacks against some high-performance processors can
1201 be used to bypass MMU permission checks and leak kernel data to
1202 userspace. This can be defended against by unmapping the kernel
1203 when running in userspace, mapping it back in on exception entry
1204 via a trampoline page in the vector table.
1208 config RODATA_FULL_DEFAULT_ENABLED
1209 bool "Apply r/o permissions of VM areas also to their linear aliases"
1212 Apply read-only attributes of VM areas to the linear alias of
1213 the backing pages as well. This prevents code or read-only data
1214 from being modified (inadvertently or intentionally) via another
1215 mapping of the same memory page. This additional enhancement can
1216 be turned off at runtime by passing rodata=[off|on] (and turned on
1217 with rodata=full if this option is set to 'n')
1219 This requires the linear region to be mapped down to pages,
1220 which may adversely affect performance in some cases.
1222 config ARM64_SW_TTBR0_PAN
1223 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1225 Enabling this option prevents the kernel from accessing
1226 user-space memory directly by pointing TTBR0_EL1 to a reserved
1227 zeroed area and reserved ASID. The user access routines
1228 restore the valid TTBR0_EL1 temporarily.
1230 config ARM64_TAGGED_ADDR_ABI
1231 bool "Enable the tagged user addresses syscall ABI"
1234 When this option is enabled, user applications can opt in to a
1235 relaxed ABI via prctl() allowing tagged addresses to be passed
1236 to system calls as pointer arguments. For details, see
1237 Documentation/arm64/tagged-address-abi.rst.
1240 bool "Kernel support for 32-bit EL0"
1241 depends on ARM64_4K_PAGES || EXPERT
1243 select OLD_SIGSUSPEND3
1244 select COMPAT_OLD_SIGACTION
1246 This option enables support for a 32-bit EL0 running under a 64-bit
1247 kernel at EL1. AArch32-specific components such as system calls,
1248 the user helper functions, VFP support and the ptrace interface are
1249 handled appropriately by the kernel.
1251 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1252 that you will only be able to execute AArch32 binaries that were compiled
1253 with page size aligned segments.
1255 If you want to execute 32-bit userspace applications, say Y.
1259 config KUSER_HELPERS
1260 bool "Enable kuser helpers page for 32-bit applications"
1263 Warning: disabling this option may break 32-bit user programs.
1265 Provide kuser helpers to compat tasks. The kernel provides
1266 helper code to userspace in read only form at a fixed location
1267 to allow userspace to be independent of the CPU type fitted to
1268 the system. This permits binaries to be run on ARMv4 through
1269 to ARMv8 without modification.
1271 See Documentation/arm/kernel_user_helpers.rst for details.
1273 However, the fixed address nature of these helpers can be used
1274 by ROP (return orientated programming) authors when creating
1277 If all of the binaries and libraries which run on your platform
1278 are built specifically for your platform, and make no use of
1279 these helpers, then you can turn this option off to hinder
1280 such exploits. However, in that case, if a binary or library
1281 relying on those helpers is run, it will not function correctly.
1283 Say N here only if you are absolutely certain that you do not
1284 need these helpers; otherwise, the safe option is to say Y.
1287 bool "Enable vDSO for 32-bit applications"
1288 depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1289 select GENERIC_COMPAT_VDSO
1292 Place in the process address space of 32-bit applications an
1293 ELF shared object providing fast implementations of gettimeofday
1296 You must have a 32-bit build of glibc 2.22 or later for programs
1297 to seamlessly take advantage of this.
1299 config THUMB2_COMPAT_VDSO
1300 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1301 depends on COMPAT_VDSO
1304 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1305 otherwise with '-marm'.
1307 menuconfig ARMV8_DEPRECATED
1308 bool "Emulate deprecated/obsolete ARMv8 instructions"
1311 Legacy software support may require certain instructions
1312 that have been deprecated or obsoleted in the architecture.
1314 Enable this config to enable selective emulation of these
1321 config SWP_EMULATION
1322 bool "Emulate SWP/SWPB instructions"
1324 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1325 they are always undefined. Say Y here to enable software
1326 emulation of these instructions for userspace using LDXR/STXR.
1327 This feature can be controlled at runtime with the abi.swp
1328 sysctl which is disabled by default.
1330 In some older versions of glibc [<=2.8] SWP is used during futex
1331 trylock() operations with the assumption that the code will not
1332 be preempted. This invalid assumption may be more likely to fail
1333 with SWP emulation enabled, leading to deadlock of the user
1336 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1337 on an external transaction monitoring block called a global
1338 monitor to maintain update atomicity. If your system does not
1339 implement a global monitor, this option can cause programs that
1340 perform SWP operations to uncached memory to deadlock.
1344 config CP15_BARRIER_EMULATION
1345 bool "Emulate CP15 Barrier instructions"
1347 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1348 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1349 strongly recommended to use the ISB, DSB, and DMB
1350 instructions instead.
1352 Say Y here to enable software emulation of these
1353 instructions for AArch32 userspace code. When this option is
1354 enabled, CP15 barrier usage is traced which can help
1355 identify software that needs updating. This feature can be
1356 controlled at runtime with the abi.cp15_barrier sysctl.
1360 config SETEND_EMULATION
1361 bool "Emulate SETEND instruction"
1363 The SETEND instruction alters the data-endianness of the
1364 AArch32 EL0, and is deprecated in ARMv8.
1366 Say Y here to enable software emulation of the instruction
1367 for AArch32 userspace code. This feature can be controlled
1368 at runtime with the abi.setend sysctl.
1370 Note: All the cpus on the system must have mixed endian support at EL0
1371 for this feature to be enabled. If a new CPU - which doesn't support mixed
1372 endian - is hotplugged in after this feature has been enabled, there could
1373 be unexpected results in the applications.
1380 menu "ARMv8.1 architectural features"
1382 config ARM64_HW_AFDBM
1383 bool "Support for hardware updates of the Access and Dirty page flags"
1386 The ARMv8.1 architecture extensions introduce support for
1387 hardware updates of the access and dirty information in page
1388 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1389 capable processors, accesses to pages with PTE_AF cleared will
1390 set this bit instead of raising an access flag fault.
1391 Similarly, writes to read-only pages with the DBM bit set will
1392 clear the read-only bit (AP[2]) instead of raising a
1395 Kernels built with this configuration option enabled continue
1396 to work on pre-ARMv8.1 hardware and the performance impact is
1397 minimal. If unsure, say Y.
1400 bool "Enable support for Privileged Access Never (PAN)"
1403 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1404 prevents the kernel or hypervisor from accessing user-space (EL0)
1407 Choosing this option will cause any unprotected (not using
1408 copy_to_user et al) memory access to fail with a permission fault.
1410 The feature is detected at runtime, and will remain as a 'nop'
1411 instruction if the cpu does not implement the feature.
1414 def_bool $(as-instr,.arch_extension rcpc)
1416 config AS_HAS_LSE_ATOMICS
1417 def_bool $(as-instr,.arch_extension lse)
1419 config ARM64_LSE_ATOMICS
1421 default ARM64_USE_LSE_ATOMICS
1422 depends on AS_HAS_LSE_ATOMICS
1424 config ARM64_USE_LSE_ATOMICS
1425 bool "Atomic instructions"
1426 depends on JUMP_LABEL
1429 As part of the Large System Extensions, ARMv8.1 introduces new
1430 atomic instructions that are designed specifically to scale in
1433 Say Y here to make use of these instructions for the in-kernel
1434 atomic routines. This incurs a small overhead on CPUs that do
1435 not support these instructions and requires the kernel to be
1436 built with binutils >= 2.25 in order for the new instructions
1441 menu "ARMv8.2 architectural features"
1444 bool "Enable support for persistent memory"
1445 select ARCH_HAS_PMEM_API
1446 select ARCH_HAS_UACCESS_FLUSHCACHE
1448 Say Y to enable support for the persistent memory API based on the
1449 ARMv8.2 DCPoP feature.
1451 The feature is detected at runtime, and the kernel will use DC CVAC
1452 operations if DC CVAP is not supported (following the behaviour of
1453 DC CVAP itself if the system does not define a point of persistence).
1455 config ARM64_RAS_EXTN
1456 bool "Enable support for RAS CPU Extensions"
1459 CPUs that support the Reliability, Availability and Serviceability
1460 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1461 errors, classify them and report them to software.
1463 On CPUs with these extensions system software can use additional
1464 barriers to determine if faults are pending and read the
1465 classification from a new set of registers.
1467 Selecting this feature will allow the kernel to use these barriers
1468 and access the new registers if the system supports the extension.
1469 Platform RAS features may additionally depend on firmware support.
1472 bool "Enable support for Common Not Private (CNP) translations"
1474 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1476 Common Not Private (CNP) allows translation table entries to
1477 be shared between different PEs in the same inner shareable
1478 domain, so the hardware can use this fact to optimise the
1479 caching of such entries in the TLB.
1481 Selecting this option allows the CNP feature to be detected
1482 at runtime, and does not affect PEs that do not implement
1487 menu "ARMv8.3 architectural features"
1489 config ARM64_PTR_AUTH
1490 bool "Enable support for pointer authentication"
1492 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1493 # Modern compilers insert a .note.gnu.property section note for PAC
1494 # which is only understood by binutils starting with version 2.33.1.
1495 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1496 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1497 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1499 Pointer authentication (part of the ARMv8.3 Extensions) provides
1500 instructions for signing and authenticating pointers against secret
1501 keys, which can be used to mitigate Return Oriented Programming (ROP)
1504 This option enables these instructions at EL0 (i.e. for userspace).
1505 Choosing this option will cause the kernel to initialise secret keys
1506 for each process at exec() time, with these keys being
1507 context-switched along with the process.
1509 If the compiler supports the -mbranch-protection or
1510 -msign-return-address flag (e.g. GCC 7 or later), then this option
1511 will also cause the kernel itself to be compiled with return address
1512 protection. In this case, and if the target hardware is known to
1513 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1514 disabled with minimal loss of protection.
1516 The feature is detected at runtime. If the feature is not present in
1517 hardware it will not be advertised to userspace/KVM guest nor will it
1520 If the feature is present on the boot CPU but not on a late CPU, then
1521 the late CPU will be parked. Also, if the boot CPU does not have
1522 address auth and the late CPU has then the late CPU will still boot
1523 but with the feature disabled. On such a system, this option should
1526 This feature works with FUNCTION_GRAPH_TRACER option only if
1527 DYNAMIC_FTRACE_WITH_REGS is enabled.
1529 config CC_HAS_BRANCH_PROT_PAC_RET
1530 # GCC 9 or later, clang 8 or later
1531 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1533 config CC_HAS_SIGN_RETURN_ADDRESS
1535 def_bool $(cc-option,-msign-return-address=all)
1538 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1540 config AS_HAS_CFI_NEGATE_RA_STATE
1541 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1545 menu "ARMv8.4 architectural features"
1547 config ARM64_AMU_EXTN
1548 bool "Enable support for the Activity Monitors Unit CPU extension"
1551 The activity monitors extension is an optional extension introduced
1552 by the ARMv8.4 CPU architecture. This enables support for version 1
1553 of the activity monitors architecture, AMUv1.
1555 To enable the use of this extension on CPUs that implement it, say Y.
1557 Note that for architectural reasons, firmware _must_ implement AMU
1558 support when running on CPUs that present the activity monitors
1559 extension. The required support is present in:
1560 * Version 1.5 and later of the ARM Trusted Firmware
1562 For kernels that have this configuration enabled but boot with broken
1563 firmware, you may need to say N here until the firmware is fixed.
1564 Otherwise you may experience firmware panics or lockups when
1565 accessing the counter registers. Even if you are not observing these
1566 symptoms, the values returned by the register reads might not
1567 correctly reflect reality. Most commonly, the value read will be 0,
1568 indicating that the counter is not enabled.
1570 config AS_HAS_ARMV8_4
1571 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1573 config ARM64_TLB_RANGE
1574 bool "Enable support for tlbi range feature"
1576 depends on AS_HAS_ARMV8_4
1578 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1579 range of input addresses.
1581 The feature introduces new assembly instructions, and they were
1582 support when binutils >= 2.30.
1586 menu "ARMv8.5 architectural features"
1588 config AS_HAS_ARMV8_5
1589 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1592 bool "Branch Target Identification support"
1595 Branch Target Identification (part of the ARMv8.5 Extensions)
1596 provides a mechanism to limit the set of locations to which computed
1597 branch instructions such as BR or BLR can jump.
1599 To make use of BTI on CPUs that support it, say Y.
1601 BTI is intended to provide complementary protection to other control
1602 flow integrity protection mechanisms, such as the Pointer
1603 authentication mechanism provided as part of the ARMv8.3 Extensions.
1604 For this reason, it does not make sense to enable this option without
1605 also enabling support for pointer authentication. Thus, when
1606 enabling this option you should also select ARM64_PTR_AUTH=y.
1608 Userspace binaries must also be specifically compiled to make use of
1609 this mechanism. If you say N here or the hardware does not support
1610 BTI, such binaries can still run, but you get no additional
1611 enforcement of branch destinations.
1613 config ARM64_BTI_KERNEL
1614 bool "Use Branch Target Identification for kernel"
1616 depends on ARM64_BTI
1617 depends on ARM64_PTR_AUTH
1618 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1619 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1620 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1621 depends on !(CC_IS_CLANG && GCOV_KERNEL)
1622 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1624 Build the kernel with Branch Target Identification annotations
1625 and enable enforcement of this for kernel code. When this option
1626 is enabled and the system supports BTI all kernel code including
1627 modular code must have BTI enabled.
1629 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1630 # GCC 9 or later, clang 8 or later
1631 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1634 bool "Enable support for E0PD"
1637 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1638 that EL0 accesses made via TTBR1 always fault in constant time,
1639 providing similar benefits to KASLR as those provided by KPTI, but
1640 with lower overhead and without disrupting legitimate access to
1641 kernel memory such as SPE.
1643 This option enables E0PD for TTBR1 where available.
1646 bool "Enable support for random number generation"
1649 Random number generation (part of the ARMv8.5 Extensions)
1650 provides a high bandwidth, cryptographically secure
1651 hardware random number generator.
1653 config ARM64_AS_HAS_MTE
1654 # Initial support for MTE went in binutils 2.32.0, checked with
1655 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1656 # as a late addition to the final architecture spec (LDGM/STGM)
1657 # is only supported in the newer 2.32.x and 2.33 binutils
1658 # versions, hence the extra "stgm" instruction check below.
1659 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1662 bool "Memory Tagging Extension support"
1664 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1665 depends on AS_HAS_ARMV8_5
1666 depends on AS_HAS_LSE_ATOMICS
1667 # Required for tag checking in the uaccess routines
1668 depends on ARM64_PAN
1669 select ARCH_USES_HIGH_VMA_FLAGS
1671 Memory Tagging (part of the ARMv8.5 Extensions) provides
1672 architectural support for run-time, always-on detection of
1673 various classes of memory error to aid with software debugging
1674 to eliminate vulnerabilities arising from memory-unsafe
1677 This option enables the support for the Memory Tagging
1678 Extension at EL0 (i.e. for userspace).
1680 Selecting this option allows the feature to be detected at
1681 runtime. Any secondary CPU not implementing this feature will
1682 not be allowed a late bring-up.
1684 Userspace binaries that want to use this feature must
1685 explicitly opt in. The mechanism for the userspace is
1688 Documentation/arm64/memory-tagging-extension.rst.
1692 menu "ARMv8.7 architectural features"
1695 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
1697 depends on ARM64_PAN
1699 Enhanced Privileged Access Never (EPAN) allows Privileged
1700 Access Never to be used with Execute-only mappings.
1702 The feature is detected at runtime, and will remain disabled
1703 if the cpu does not implement the feature.
1707 bool "ARM Scalable Vector Extension support"
1710 The Scalable Vector Extension (SVE) is an extension to the AArch64
1711 execution state which complements and extends the SIMD functionality
1712 of the base architecture to support much larger vectors and to enable
1713 additional vectorisation opportunities.
1715 To enable use of this extension on CPUs that implement it, say Y.
1717 On CPUs that support the SVE2 extensions, this option will enable
1720 Note that for architectural reasons, firmware _must_ implement SVE
1721 support when running on SVE capable hardware. The required support
1724 * version 1.5 and later of the ARM Trusted Firmware
1725 * the AArch64 boot wrapper since commit 5e1261e08abf
1726 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1728 For other firmware implementations, consult the firmware documentation
1731 If you need the kernel to boot on SVE-capable hardware with broken
1732 firmware, you may need to say N here until you get your firmware
1733 fixed. Otherwise, you may experience firmware panics or lockups when
1734 booting the kernel. If unsure and you are not observing these
1735 symptoms, you should assume that it is safe to say Y.
1737 config ARM64_MODULE_PLTS
1738 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1740 select HAVE_MOD_ARCH_SPECIFIC
1742 Allocate PLTs when loading modules so that jumps and calls whose
1743 targets are too far away for their relative offsets to be encoded
1744 in the instructions themselves can be bounced via veneers in the
1745 module's PLT. This allows modules to be allocated in the generic
1746 vmalloc area after the dedicated module memory area has been
1749 When running with address space randomization (KASLR), the module
1750 region itself may be too far away for ordinary relative jumps and
1751 calls, and so in that case, module PLTs are required and cannot be
1754 Specific errata workaround(s) might also force module PLTs to be
1755 enabled (ARM64_ERRATUM_843419).
1757 config ARM64_PSEUDO_NMI
1758 bool "Support for NMI-like interrupts"
1761 Adds support for mimicking Non-Maskable Interrupts through the use of
1762 GIC interrupt priority. This support requires version 3 or later of
1765 This high priority configuration for interrupts needs to be
1766 explicitly enabled by setting the kernel parameter
1767 "irqchip.gicv3_pseudo_nmi" to 1.
1772 config ARM64_DEBUG_PRIORITY_MASKING
1773 bool "Debug interrupt priority masking"
1775 This adds runtime checks to functions enabling/disabling
1776 interrupts when using priority masking. The additional checks verify
1777 the validity of ICC_PMR_EL1 when calling concerned functions.
1783 bool "Build a relocatable kernel image" if EXPERT
1784 select ARCH_HAS_RELR
1787 This builds the kernel as a Position Independent Executable (PIE),
1788 which retains all relocation metadata required to relocate the
1789 kernel binary at runtime to a different virtual address than the
1790 address it was linked at.
1791 Since AArch64 uses the RELA relocation format, this requires a
1792 relocation pass at runtime even if the kernel is loaded at the
1793 same address it was linked at.
1795 config RANDOMIZE_BASE
1796 bool "Randomize the address of the kernel image"
1797 select ARM64_MODULE_PLTS if MODULES
1800 Randomizes the virtual address at which the kernel image is
1801 loaded, as a security feature that deters exploit attempts
1802 relying on knowledge of the location of kernel internals.
1804 It is the bootloader's job to provide entropy, by passing a
1805 random u64 value in /chosen/kaslr-seed at kernel entry.
1807 When booting via the UEFI stub, it will invoke the firmware's
1808 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1809 to the kernel proper. In addition, it will randomise the physical
1810 location of the kernel Image as well.
1814 config RANDOMIZE_MODULE_REGION_FULL
1815 bool "Randomize the module region over a 4 GB range"
1816 depends on RANDOMIZE_BASE
1819 Randomizes the location of the module region inside a 4 GB window
1820 covering the core kernel. This way, it is less likely for modules
1821 to leak information about the location of core kernel data structures
1822 but it does imply that function calls between modules and the core
1823 kernel will need to be resolved via veneers in the module PLT.
1825 When this option is not set, the module region will be randomized over
1826 a limited range that contains the [_stext, _etext] interval of the
1827 core kernel, so branch relocations are always in range.
1829 config CC_HAVE_STACKPROTECTOR_SYSREG
1830 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1832 config STACKPROTECTOR_PER_TASK
1834 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1840 config ARM64_ACPI_PARKING_PROTOCOL
1841 bool "Enable support for the ARM64 ACPI parking protocol"
1844 Enable support for the ARM64 ACPI parking protocol. If disabled
1845 the kernel will not allow booting through the ARM64 ACPI parking
1846 protocol even if the corresponding data is present in the ACPI
1850 string "Default kernel command string"
1853 Provide a set of default command-line options at build time by
1854 entering them here. As a minimum, you should specify the the
1855 root device (e.g. root=/dev/nfs).
1858 prompt "Kernel command line type" if CMDLINE != ""
1859 default CMDLINE_FROM_BOOTLOADER
1861 Choose how the kernel will handle the provided default kernel
1862 command line string.
1864 config CMDLINE_FROM_BOOTLOADER
1865 bool "Use bootloader kernel arguments if available"
1867 Uses the command-line options passed by the boot loader. If
1868 the boot loader doesn't provide any, the default kernel command
1869 string provided in CMDLINE will be used.
1871 config CMDLINE_FORCE
1872 bool "Always use the default kernel command string"
1874 Always use the default kernel command string, even if the boot
1875 loader passes other arguments to the kernel.
1876 This is useful if you cannot or don't want to change the
1877 command-line options your boot loader passes to the kernel.
1885 bool "UEFI runtime support"
1886 depends on OF && !CPU_BIG_ENDIAN
1887 depends on KERNEL_MODE_NEON
1888 select ARCH_SUPPORTS_ACPI
1891 select EFI_PARAMS_FROM_FDT
1892 select EFI_RUNTIME_WRAPPERS
1894 select EFI_GENERIC_STUB
1895 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
1898 This option provides support for runtime services provided
1899 by UEFI firmware (such as non-volatile variables, realtime
1900 clock, and platform reset). A UEFI stub is also provided to
1901 allow the kernel to be booted as an EFI application. This
1902 is only useful on systems that have UEFI firmware.
1905 bool "Enable support for SMBIOS (DMI) tables"
1909 This enables SMBIOS/DMI feature for systems.
1911 This option is only useful on systems that have UEFI firmware.
1912 However, even with this option, the resultant kernel should
1913 continue to boot on existing non-UEFI platforms.
1917 config SYSVIPC_COMPAT
1919 depends on COMPAT && SYSVIPC
1921 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1923 depends on HUGETLB_PAGE && MIGRATION
1925 config ARCH_ENABLE_THP_MIGRATION
1927 depends on TRANSPARENT_HUGEPAGE
1929 menu "Power management options"
1931 source "kernel/power/Kconfig"
1933 config ARCH_HIBERNATION_POSSIBLE
1937 config ARCH_HIBERNATION_HEADER
1939 depends on HIBERNATION
1941 config ARCH_SUSPEND_POSSIBLE
1946 menu "CPU Power Management"
1948 source "drivers/cpuidle/Kconfig"
1950 source "drivers/cpufreq/Kconfig"
1954 source "drivers/firmware/Kconfig"
1956 source "drivers/acpi/Kconfig"
1958 source "arch/arm64/kvm/Kconfig"
1961 source "arch/arm64/crypto/Kconfig"