3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if (ACPI && PCI)
9 select ACPI_SPCR_TABLE if ACPI
10 select ACPI_PPTT if ACPI
11 select ARCH_CLOCKSOURCE_DATA
12 select ARCH_HAS_DEBUG_VIRTUAL
13 select ARCH_HAS_DEVMEM_IS_ALLOWED
14 select ARCH_HAS_DMA_COHERENT_TO_PFN
15 select ARCH_HAS_DMA_MMAP_PGPROT
16 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
17 select ARCH_HAS_ELF_RANDOMIZE
18 select ARCH_HAS_FAST_MULTIPLIER
19 select ARCH_HAS_FORTIFY_SOURCE
20 select ARCH_HAS_GCOV_PROFILE_ALL
21 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
23 select ARCH_HAS_MEMBARRIER_SYNC_CORE
24 select ARCH_HAS_PTE_SPECIAL
25 select ARCH_HAS_SETUP_DMA_OPS
26 select ARCH_HAS_SET_MEMORY
27 select ARCH_HAS_STRICT_KERNEL_RWX
28 select ARCH_HAS_STRICT_MODULE_RWX
29 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
30 select ARCH_HAS_SYNC_DMA_FOR_CPU
31 select ARCH_HAS_SYSCALL_WRAPPER
32 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
33 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
34 select ARCH_HAVE_NMI_SAFE_CMPXCHG
35 select ARCH_INLINE_READ_LOCK if !PREEMPT
36 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
37 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
38 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
39 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
40 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
41 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
42 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
43 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
44 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
45 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
46 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
47 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
48 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
49 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
50 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
51 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
52 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
53 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
54 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
55 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
56 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
57 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
58 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
59 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
60 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
61 select ARCH_USE_CMPXCHG_LOCKREF
62 select ARCH_USE_QUEUED_RWLOCKS
63 select ARCH_USE_QUEUED_SPINLOCKS
64 select ARCH_SUPPORTS_MEMORY_FAILURE
65 select ARCH_SUPPORTS_ATOMIC_RMW
66 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
67 select ARCH_SUPPORTS_NUMA_BALANCING
68 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
69 select ARCH_WANT_FRAME_POINTERS
70 select ARCH_HAS_UBSAN_SANITIZE_ALL
74 select AUDIT_ARCH_COMPAT_GENERIC
75 select ARM_GIC_V2M if PCI
77 select ARM_GIC_V3_ITS if PCI
79 select BUILDTIME_EXTABLE_SORT
80 select CLONE_BACKWARDS
82 select CPU_PM if (SUSPEND || CPU_IDLE)
84 select DCACHE_WORD_ACCESS
85 select DMA_DIRECT_REMAP
88 select GENERIC_ALLOCATOR
89 select GENERIC_ARCH_TOPOLOGY
90 select GENERIC_CLOCKEVENTS
91 select GENERIC_CLOCKEVENTS_BROADCAST
92 select GENERIC_CPU_AUTOPROBE
93 select GENERIC_EARLY_IOREMAP
94 select GENERIC_IDLE_POLL_SETUP
95 select GENERIC_IRQ_MULTI_HANDLER
96 select GENERIC_IRQ_PROBE
97 select GENERIC_IRQ_SHOW
98 select GENERIC_IRQ_SHOW_LEVEL
99 select GENERIC_PCI_IOMAP
100 select GENERIC_SCHED_CLOCK
101 select GENERIC_SMP_IDLE_THREAD
102 select GENERIC_STRNCPY_FROM_USER
103 select GENERIC_STRNLEN_USER
104 select GENERIC_TIME_VSYSCALL
105 select HANDLE_DOMAIN_IRQ
106 select HARDIRQS_SW_RESEND
108 select HAVE_ACPI_APEI if (ACPI && EFI)
109 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
110 select HAVE_ARCH_AUDITSYSCALL
111 select HAVE_ARCH_BITREVERSE
112 select HAVE_ARCH_HUGE_VMAP
113 select HAVE_ARCH_JUMP_LABEL
114 select HAVE_ARCH_JUMP_LABEL_RELATIVE
115 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
116 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
117 select HAVE_ARCH_KGDB
118 select HAVE_ARCH_MMAP_RND_BITS
119 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
120 select HAVE_ARCH_PREL32_RELOCATIONS
121 select HAVE_ARCH_SECCOMP_FILTER
122 select HAVE_ARCH_STACKLEAK
123 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
124 select HAVE_ARCH_TRACEHOOK
125 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
126 select HAVE_ARCH_VMAP_STACK
127 select HAVE_ARM_SMCCC
129 select HAVE_C_RECORDMCOUNT
130 select HAVE_CMPXCHG_DOUBLE
131 select HAVE_CMPXCHG_LOCAL
132 select HAVE_CONTEXT_TRACKING
133 select HAVE_DEBUG_BUGVERBOSE
134 select HAVE_DEBUG_KMEMLEAK
135 select HAVE_DMA_CONTIGUOUS
136 select HAVE_DYNAMIC_FTRACE
137 select HAVE_EFFICIENT_UNALIGNED_ACCESS
138 select HAVE_FTRACE_MCOUNT_RECORD
139 select HAVE_FUNCTION_TRACER
140 select HAVE_FUNCTION_GRAPH_TRACER
141 select HAVE_GCC_PLUGINS
142 select HAVE_HW_BREAKPOINT if PERF_EVENTS
143 select HAVE_IRQ_TIME_ACCOUNTING
144 select HAVE_MEMBLOCK_NODE_MAP if NUMA
146 select HAVE_PATA_PLATFORM
147 select HAVE_PERF_EVENTS
148 select HAVE_PERF_REGS
149 select HAVE_PERF_USER_STACK_DUMP
150 select HAVE_REGS_AND_STACK_ACCESS_API
151 select HAVE_RCU_TABLE_FREE
152 select HAVE_RCU_TABLE_INVALIDATE
154 select HAVE_STACKPROTECTOR
155 select HAVE_SYSCALL_TRACEPOINTS
157 select HAVE_KRETPROBES
158 select IOMMU_DMA if IOMMU_SUPPORT
160 select IRQ_FORCED_THREADING
161 select MODULES_USE_ELF_RELA
162 select MULTI_IRQ_HANDLER
163 select NEED_DMA_MAP_STATE
164 select NEED_SG_DMA_LENGTH
166 select OF_EARLY_FLATTREE
167 select PCI_DOMAINS_GENERIC if PCI
168 select PCI_ECAM if (ACPI && PCI)
169 select PCI_SYSCALL if PCI
175 select SYSCTL_EXCEPTION_TRACE
176 select THREAD_INFO_IN_TASK
178 ARM 64-bit (AArch64) Linux support.
186 config ARM64_PAGE_SHIFT
188 default 16 if ARM64_64K_PAGES
189 default 14 if ARM64_16K_PAGES
192 config ARM64_CONT_SHIFT
194 default 5 if ARM64_64K_PAGES
195 default 7 if ARM64_16K_PAGES
198 config ARCH_MMAP_RND_BITS_MIN
199 default 14 if ARM64_64K_PAGES
200 default 16 if ARM64_16K_PAGES
203 # max bits determined by the following formula:
204 # VA_BITS - PAGE_SHIFT - 3
205 config ARCH_MMAP_RND_BITS_MAX
206 default 19 if ARM64_VA_BITS=36
207 default 24 if ARM64_VA_BITS=39
208 default 27 if ARM64_VA_BITS=42
209 default 30 if ARM64_VA_BITS=47
210 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
211 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
212 default 33 if ARM64_VA_BITS=48
213 default 14 if ARM64_64K_PAGES
214 default 16 if ARM64_16K_PAGES
217 config ARCH_MMAP_RND_COMPAT_BITS_MIN
218 default 7 if ARM64_64K_PAGES
219 default 9 if ARM64_16K_PAGES
222 config ARCH_MMAP_RND_COMPAT_BITS_MAX
228 config STACKTRACE_SUPPORT
231 config ILLEGAL_POINTER_VALUE
233 default 0xdead000000000000
235 config LOCKDEP_SUPPORT
238 config TRACE_IRQFLAGS_SUPPORT
241 config RWSEM_XCHGADD_ALGORITHM
248 config GENERIC_BUG_RELATIVE_POINTERS
250 depends on GENERIC_BUG
252 config GENERIC_HWEIGHT
258 config GENERIC_CALIBRATE_DELAY
264 config HAVE_GENERIC_GUP
267 config ARCH_ENABLE_MEMORY_HOTPLUG
273 config KERNEL_MODE_NEON
276 config FIX_EARLYCON_MEM
279 config PGTABLE_LEVELS
281 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
282 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
283 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_USER_VA_BITS_52)
284 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
285 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
286 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
288 config ARCH_SUPPORTS_UPROBES
291 config ARCH_PROC_KCORE_TEXT
294 source "arch/arm64/Kconfig.platforms"
296 menu "Kernel Features"
298 menu "ARM errata workarounds via the alternatives framework"
300 config ARM64_WORKAROUND_CLEAN_CACHE
303 config ARM64_ERRATUM_826319
304 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
306 select ARM64_WORKAROUND_CLEAN_CACHE
308 This option adds an alternative code sequence to work around ARM
309 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
310 AXI master interface and an L2 cache.
312 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
313 and is unable to accept a certain write via this interface, it will
314 not progress on read data presented on the read data channel and the
317 The workaround promotes data cache clean instructions to
318 data cache clean-and-invalidate.
319 Please note that this does not necessarily enable the workaround,
320 as it depends on the alternative framework, which will only patch
321 the kernel if an affected CPU is detected.
325 config ARM64_ERRATUM_827319
326 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
328 select ARM64_WORKAROUND_CLEAN_CACHE
330 This option adds an alternative code sequence to work around ARM
331 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
332 master interface and an L2 cache.
334 Under certain conditions this erratum can cause a clean line eviction
335 to occur at the same time as another transaction to the same address
336 on the AMBA 5 CHI interface, which can cause data corruption if the
337 interconnect reorders the two transactions.
339 The workaround promotes data cache clean instructions to
340 data cache clean-and-invalidate.
341 Please note that this does not necessarily enable the workaround,
342 as it depends on the alternative framework, which will only patch
343 the kernel if an affected CPU is detected.
347 config ARM64_ERRATUM_824069
348 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
350 select ARM64_WORKAROUND_CLEAN_CACHE
352 This option adds an alternative code sequence to work around ARM
353 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
354 to a coherent interconnect.
356 If a Cortex-A53 processor is executing a store or prefetch for
357 write instruction at the same time as a processor in another
358 cluster is executing a cache maintenance operation to the same
359 address, then this erratum might cause a clean cache line to be
360 incorrectly marked as dirty.
362 The workaround promotes data cache clean instructions to
363 data cache clean-and-invalidate.
364 Please note that this option does not necessarily enable the
365 workaround, as it depends on the alternative framework, which will
366 only patch the kernel if an affected CPU is detected.
370 config ARM64_ERRATUM_819472
371 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
373 select ARM64_WORKAROUND_CLEAN_CACHE
375 This option adds an alternative code sequence to work around ARM
376 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
377 present when it is connected to a coherent interconnect.
379 If the processor is executing a load and store exclusive sequence at
380 the same time as a processor in another cluster is executing a cache
381 maintenance operation to the same address, then this erratum might
382 cause data corruption.
384 The workaround promotes data cache clean instructions to
385 data cache clean-and-invalidate.
386 Please note that this does not necessarily enable the workaround,
387 as it depends on the alternative framework, which will only patch
388 the kernel if an affected CPU is detected.
392 config ARM64_ERRATUM_832075
393 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
396 This option adds an alternative code sequence to work around ARM
397 erratum 832075 on Cortex-A57 parts up to r1p2.
399 Affected Cortex-A57 parts might deadlock when exclusive load/store
400 instructions to Write-Back memory are mixed with Device loads.
402 The workaround is to promote device loads to use Load-Acquire
404 Please note that this does not necessarily enable the workaround,
405 as it depends on the alternative framework, which will only patch
406 the kernel if an affected CPU is detected.
410 config ARM64_ERRATUM_834220
411 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
415 This option adds an alternative code sequence to work around ARM
416 erratum 834220 on Cortex-A57 parts up to r1p2.
418 Affected Cortex-A57 parts might report a Stage 2 translation
419 fault as the result of a Stage 1 fault for load crossing a
420 page boundary when there is a permission or device memory
421 alignment fault at Stage 1 and a translation fault at Stage 2.
423 The workaround is to verify that the Stage 1 translation
424 doesn't generate a fault before handling the Stage 2 fault.
425 Please note that this does not necessarily enable the workaround,
426 as it depends on the alternative framework, which will only patch
427 the kernel if an affected CPU is detected.
431 config ARM64_ERRATUM_845719
432 bool "Cortex-A53: 845719: a load might read incorrect data"
436 This option adds an alternative code sequence to work around ARM
437 erratum 845719 on Cortex-A53 parts up to r0p4.
439 When running a compat (AArch32) userspace on an affected Cortex-A53
440 part, a load at EL0 from a virtual address that matches the bottom 32
441 bits of the virtual address used by a recent load at (AArch64) EL1
442 might return incorrect data.
444 The workaround is to write the contextidr_el1 register on exception
445 return to a 32-bit task.
446 Please note that this does not necessarily enable the workaround,
447 as it depends on the alternative framework, which will only patch
448 the kernel if an affected CPU is detected.
452 config ARM64_ERRATUM_843419
453 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
455 select ARM64_MODULE_PLTS if MODULES
457 This option links the kernel with '--fix-cortex-a53-843419' and
458 enables PLT support to replace certain ADRP instructions, which can
459 cause subsequent memory accesses to use an incorrect address on
460 Cortex-A53 parts up to r0p4.
464 config ARM64_ERRATUM_1024718
465 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
468 This option adds work around for Arm Cortex-A55 Erratum 1024718.
470 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
471 update of the hardware dirty bit when the DBM/AP bits are updated
472 without a break-before-make. The work around is to disable the usage
473 of hardware DBM locally on the affected cores. CPUs not affected by
474 erratum will continue to use the feature.
478 config ARM64_ERRATUM_1188873
479 bool "Cortex-A76: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
481 select ARM_ARCH_TIMER_OOL_WORKAROUND
483 This option adds work arounds for ARM Cortex-A76 erratum 1188873
485 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could cause
486 register corruption when accessing the timer registers from
491 config ARM64_ERRATUM_1165522
492 bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
495 This option adds work arounds for ARM Cortex-A76 erratum 1165522
497 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
498 corrupted TLBs by speculating an AT instruction during a guest
503 config ARM64_ERRATUM_1286807
504 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
506 select ARM64_WORKAROUND_REPEAT_TLBI
508 This option adds workaround for ARM Cortex-A76 erratum 1286807
510 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
511 address for a cacheable mapping of a location is being
512 accessed by a core while another core is remapping the virtual
513 address to a new physical page using the recommended
514 break-before-make sequence, then under very rare circumstances
515 TLBI+DSB completes before a read using the translation being
516 invalidated has been observed by other observers. The
517 workaround repeats the TLBI+DSB operation.
521 config CAVIUM_ERRATUM_22375
522 bool "Cavium erratum 22375, 24313"
525 Enable workaround for erratum 22375, 24313.
527 This implements two gicv3-its errata workarounds for ThunderX. Both
528 with small impact affecting only ITS table allocation.
530 erratum 22375: only alloc 8MB table size
531 erratum 24313: ignore memory access type
533 The fixes are in ITS initialization and basically ignore memory access
534 type and table size provided by the TYPER and BASER registers.
538 config CAVIUM_ERRATUM_23144
539 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
543 ITS SYNC command hang for cross node io and collections/cpu mapping.
547 config CAVIUM_ERRATUM_23154
548 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
551 The gicv3 of ThunderX requires a modified version for
552 reading the IAR status to ensure data synchronization
553 (access to icc_iar1_el1 is not sync'ed before and after).
557 config CAVIUM_ERRATUM_27456
558 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
561 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
562 instructions may cause the icache to become corrupted if it
563 contains data for a non-current ASID. The fix is to
564 invalidate the icache when changing the mm context.
568 config CAVIUM_ERRATUM_30115
569 bool "Cavium erratum 30115: Guest may disable interrupts in host"
572 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
573 1.2, and T83 Pass 1.0, KVM guest execution may disable
574 interrupts in host. Trapping both GICv3 group-0 and group-1
575 accesses sidesteps the issue.
579 config QCOM_FALKOR_ERRATUM_1003
580 bool "Falkor E1003: Incorrect translation due to ASID change"
583 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
584 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
585 in TTBR1_EL1, this situation only occurs in the entry trampoline and
586 then only for entries in the walk cache, since the leaf translation
587 is unchanged. Work around the erratum by invalidating the walk cache
588 entries for the trampoline before entering the kernel proper.
590 config ARM64_WORKAROUND_REPEAT_TLBI
593 Enable the repeat TLBI workaround for Falkor erratum 1009 and
594 Cortex-A76 erratum 1286807.
596 config QCOM_FALKOR_ERRATUM_1009
597 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
599 select ARM64_WORKAROUND_REPEAT_TLBI
601 On Falkor v1, the CPU may prematurely complete a DSB following a
602 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
603 one more time to fix the issue.
607 config QCOM_QDF2400_ERRATUM_0065
608 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
611 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
612 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
613 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
617 config SOCIONEXT_SYNQUACER_PREITS
618 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
621 Socionext Synquacer SoCs implement a separate h/w block to generate
622 MSI doorbell writes with non-zero values for the device ID.
626 config HISILICON_ERRATUM_161600802
627 bool "Hip07 161600802: Erroneous redistributor VLPI base"
630 The HiSilicon Hip07 SoC usees the wrong redistributor base
631 when issued ITS commands such as VMOVP and VMAPP, and requires
632 a 128kB offset to be applied to the target address in this commands.
636 config QCOM_FALKOR_ERRATUM_E1041
637 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
640 Falkor CPU may speculatively fetch instructions from an improper
641 memory location when MMU translation is changed from SCTLR_ELn[M]=1
642 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
646 config FUJITSU_ERRATUM_010001
647 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
650 This option adds workaround for Fujitsu-A64FX erratum E#010001.
651 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
652 accesses may cause undefined fault (Data abort, DFSC=0b111111).
653 This fault occurs under a specific hardware condition when a
654 load/store instruction performs an address translation using:
655 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
656 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
657 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
658 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
660 The workaround is to ensure these bits are clear in TCR_ELx.
661 The workaround only affect the Fujitsu-A64FX.
670 default ARM64_4K_PAGES
672 Page size (translation granule) configuration.
674 config ARM64_4K_PAGES
677 This feature enables 4KB pages support.
679 config ARM64_16K_PAGES
682 The system will use 16KB pages support. AArch32 emulation
683 requires applications compiled with 16K (or a multiple of 16K)
686 config ARM64_64K_PAGES
689 This feature enables 64KB pages support (4KB by default)
690 allowing only two levels of page tables and faster TLB
691 look-up. AArch32 emulation requires applications compiled
692 with 64K aligned segments.
697 prompt "Virtual address space size"
698 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
699 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
700 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
702 Allows choosing one of multiple possible virtual address
703 space sizes. The level of translation table is determined by
704 a combination of page size and virtual address space size.
706 config ARM64_VA_BITS_36
707 bool "36-bit" if EXPERT
708 depends on ARM64_16K_PAGES
710 config ARM64_VA_BITS_39
712 depends on ARM64_4K_PAGES
714 config ARM64_VA_BITS_42
716 depends on ARM64_64K_PAGES
718 config ARM64_VA_BITS_47
720 depends on ARM64_16K_PAGES
722 config ARM64_VA_BITS_48
725 config ARM64_USER_VA_BITS_52
727 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
729 Enable 52-bit virtual addressing for userspace when explicitly
730 requested via a hint to mmap(). The kernel will continue to
731 use 48-bit virtual addresses for its own mappings.
733 NOTE: Enabling 52-bit virtual addressing in conjunction with
734 ARMv8.3 Pointer Authentication will result in the PAC being
735 reduced from 7 bits to 3 bits, which may have a significant
736 impact on its susceptibility to brute-force attacks.
738 If unsure, select 48-bit virtual addressing instead.
742 config ARM64_FORCE_52BIT
743 bool "Force 52-bit virtual addresses for userspace"
744 depends on ARM64_USER_VA_BITS_52 && EXPERT
746 For systems with 52-bit userspace VAs enabled, the kernel will attempt
747 to maintain compatibility with older software by providing 48-bit VAs
748 unless a hint is supplied to mmap.
750 This configuration option disables the 48-bit compatibility logic, and
751 forces all userspace addresses to be 52-bit on HW that supports it. One
752 should only enable this configuration option for stress testing userspace
753 memory management code. If unsure say N here.
757 default 36 if ARM64_VA_BITS_36
758 default 39 if ARM64_VA_BITS_39
759 default 42 if ARM64_VA_BITS_42
760 default 47 if ARM64_VA_BITS_47
761 default 48 if ARM64_VA_BITS_48 || ARM64_USER_VA_BITS_52
764 prompt "Physical address space size"
765 default ARM64_PA_BITS_48
767 Choose the maximum physical address range that the kernel will
770 config ARM64_PA_BITS_48
773 config ARM64_PA_BITS_52
774 bool "52-bit (ARMv8.2)"
775 depends on ARM64_64K_PAGES
776 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
778 Enable support for a 52-bit physical address space, introduced as
779 part of the ARMv8.2-LPA extension.
781 With this enabled, the kernel will also continue to work on CPUs that
782 do not support ARMv8.2-LPA, but with some added memory overhead (and
783 minor performance overhead).
789 default 48 if ARM64_PA_BITS_48
790 default 52 if ARM64_PA_BITS_52
792 config CPU_BIG_ENDIAN
793 bool "Build big-endian kernel"
795 Say Y if you plan on running a kernel in big-endian mode.
798 bool "Multi-core scheduler support"
800 Multi-core scheduler support improves the CPU scheduler's decision
801 making when dealing with multi-core CPU chips at a cost of slightly
802 increased overhead in some places. If unsure say N here.
805 bool "SMT scheduler support"
807 Improves the CPU scheduler's decision making when dealing with
808 MultiThreading at a cost of slightly increased overhead in some
809 places. If unsure say N here.
812 int "Maximum number of CPUs (2-4096)"
817 bool "Support for hot-pluggable CPUs"
818 select GENERIC_IRQ_MIGRATION
820 Say Y here to experiment with turning CPUs off and on. CPUs
821 can be controlled through /sys/devices/system/cpu.
823 # Common NUMA Features
825 bool "Numa Memory Allocation and Scheduler Support"
826 select ACPI_NUMA if ACPI
829 Enable NUMA (Non Uniform Memory Access) support.
831 The kernel will try to allocate memory used by a CPU on the
832 local memory of the CPU and add some more
833 NUMA awareness to the kernel.
836 int "Maximum NUMA Nodes (as a power of 2)"
839 depends on NEED_MULTIPLE_NODES
841 Specify the maximum number of NUMA Nodes available on the target
842 system. Increases memory reserved to accommodate various tables.
844 config USE_PERCPU_NUMA_NODE_ID
848 config HAVE_SETUP_PER_CPU_AREA
852 config NEED_PER_CPU_EMBED_FIRST_CHUNK
859 source "kernel/Kconfig.hz"
861 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
864 config ARCH_SPARSEMEM_ENABLE
866 select SPARSEMEM_VMEMMAP_ENABLE
868 config ARCH_SPARSEMEM_DEFAULT
869 def_bool ARCH_SPARSEMEM_ENABLE
871 config ARCH_SELECT_MEMORY_MODEL
872 def_bool ARCH_SPARSEMEM_ENABLE
874 config ARCH_FLATMEM_ENABLE
877 config HAVE_ARCH_PFN_VALID
880 config HW_PERF_EVENTS
884 config SYS_SUPPORTS_HUGETLBFS
887 config ARCH_WANT_HUGE_PMD_SHARE
888 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
890 config ARCH_HAS_CACHE_LINE_SIZE
894 bool "Enable seccomp to safely compute untrusted bytecode"
896 This kernel feature is useful for number crunching applications
897 that may need to compute untrusted bytecode during their
898 execution. By using pipes or other transports made available to
899 the process as file descriptors supporting the read/write
900 syscalls, it's possible to isolate those applications in
901 their own address space using seccomp. Once seccomp is
902 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
903 and the task is only allowed to execute a few safe syscalls
904 defined by each seccomp mode.
907 bool "Enable paravirtualization code"
909 This changes the kernel so it can modify itself when it is run
910 under a hypervisor, potentially improving performance significantly
911 over full virtualization.
913 config PARAVIRT_TIME_ACCOUNTING
914 bool "Paravirtual steal time accounting"
918 Select this option to enable fine granularity task steal time
919 accounting. Time spent executing other tasks in parallel with
920 the current vCPU is discounted from the vCPU power. To account for
921 that, there can be a small performance impact.
923 If in doubt, say N here.
926 depends on PM_SLEEP_SMP
928 bool "kexec system call"
930 kexec is a system call that implements the ability to shutdown your
931 current kernel, and to start another kernel. It is like a reboot
932 but it is independent of the system firmware. And like a reboot
933 you can start any kernel with it, not just Linux.
936 bool "kexec file based system call"
939 This is new version of kexec system call. This system call is
940 file based and takes file descriptors as system call argument
941 for kernel and initramfs as opposed to list of segments as
942 accepted by previous system call.
944 config KEXEC_VERIFY_SIG
945 bool "Verify kernel signature during kexec_file_load() syscall"
946 depends on KEXEC_FILE
948 Select this option to verify a signature with loaded kernel
949 image. If configured, any attempt of loading a image without
950 valid signature will fail.
952 In addition to that option, you need to enable signature
953 verification for the corresponding kernel image type being
954 loaded in order for this to work.
956 config KEXEC_IMAGE_VERIFY_SIG
957 bool "Enable Image signature verification support"
959 depends on KEXEC_VERIFY_SIG
960 depends on EFI && SIGNED_PE_FILE_VERIFICATION
962 Enable Image signature verification support.
964 comment "Support for PE file signature verification disabled"
965 depends on KEXEC_VERIFY_SIG
966 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
969 bool "Build kdump crash kernel"
971 Generate crash dump after being started by kexec. This should
972 be normally only set in special crash dump kernels which are
973 loaded in the main kernel with kexec-tools into a specially
974 reserved region and then later executed after a crash by
977 For more details see Documentation/kdump/kdump.txt
984 bool "Xen guest support on ARM64"
985 depends on ARM64 && OF
989 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
991 config FORCE_MAX_ZONEORDER
993 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
994 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
997 The kernel memory allocator divides physically contiguous memory
998 blocks into "zones", where each zone is a power of two number of
999 pages. This option selects the largest power of two that the kernel
1000 keeps in the memory allocator. If you need to allocate very large
1001 blocks of physically contiguous memory, then you may need to
1002 increase this value.
1004 This config option is actually maximum order plus one. For example,
1005 a value of 11 means that the largest free memory block is 2^10 pages.
1007 We make sure that we can allocate upto a HugePage size for each configuration.
1009 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1011 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1012 4M allocations matching the default size used by generic code.
1014 config UNMAP_KERNEL_AT_EL0
1015 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1018 Speculation attacks against some high-performance processors can
1019 be used to bypass MMU permission checks and leak kernel data to
1020 userspace. This can be defended against by unmapping the kernel
1021 when running in userspace, mapping it back in on exception entry
1022 via a trampoline page in the vector table.
1026 config HARDEN_BRANCH_PREDICTOR
1027 bool "Harden the branch predictor against aliasing attacks" if EXPERT
1030 Speculation attacks against some high-performance processors rely on
1031 being able to manipulate the branch predictor for a victim context by
1032 executing aliasing branches in the attacker context. Such attacks
1033 can be partially mitigated against by clearing internal branch
1034 predictor state and limiting the prediction logic in some situations.
1036 This config option will take CPU-specific actions to harden the
1037 branch predictor against aliasing attacks and may rely on specific
1038 instruction sequences or control bits being set by the system
1043 config HARDEN_EL2_VECTORS
1044 bool "Harden EL2 vector mapping against system register leak" if EXPERT
1047 Speculation attacks against some high-performance processors can
1048 be used to leak privileged information such as the vector base
1049 register, resulting in a potential defeat of the EL2 layout
1052 This config option will map the vectors to a fixed location,
1053 independent of the EL2 code mapping, so that revealing VBAR_EL2
1054 to an attacker does not give away any extra information. This
1055 only gets enabled on affected CPUs.
1060 bool "Speculative Store Bypass Disable" if EXPERT
1063 This enables mitigation of the bypassing of previous stores
1064 by speculative loads.
1068 config RODATA_FULL_DEFAULT_ENABLED
1069 bool "Apply r/o permissions of VM areas also to their linear aliases"
1072 Apply read-only attributes of VM areas to the linear alias of
1073 the backing pages as well. This prevents code or read-only data
1074 from being modified (inadvertently or intentionally) via another
1075 mapping of the same memory page. This additional enhancement can
1076 be turned off at runtime by passing rodata=[off|on] (and turned on
1077 with rodata=full if this option is set to 'n')
1079 This requires the linear region to be mapped down to pages,
1080 which may adversely affect performance in some cases.
1082 menuconfig ARMV8_DEPRECATED
1083 bool "Emulate deprecated/obsolete ARMv8 instructions"
1087 Legacy software support may require certain instructions
1088 that have been deprecated or obsoleted in the architecture.
1090 Enable this config to enable selective emulation of these
1097 config SWP_EMULATION
1098 bool "Emulate SWP/SWPB instructions"
1100 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1101 they are always undefined. Say Y here to enable software
1102 emulation of these instructions for userspace using LDXR/STXR.
1104 In some older versions of glibc [<=2.8] SWP is used during futex
1105 trylock() operations with the assumption that the code will not
1106 be preempted. This invalid assumption may be more likely to fail
1107 with SWP emulation enabled, leading to deadlock of the user
1110 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1111 on an external transaction monitoring block called a global
1112 monitor to maintain update atomicity. If your system does not
1113 implement a global monitor, this option can cause programs that
1114 perform SWP operations to uncached memory to deadlock.
1118 config CP15_BARRIER_EMULATION
1119 bool "Emulate CP15 Barrier instructions"
1121 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1122 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1123 strongly recommended to use the ISB, DSB, and DMB
1124 instructions instead.
1126 Say Y here to enable software emulation of these
1127 instructions for AArch32 userspace code. When this option is
1128 enabled, CP15 barrier usage is traced which can help
1129 identify software that needs updating.
1133 config SETEND_EMULATION
1134 bool "Emulate SETEND instruction"
1136 The SETEND instruction alters the data-endianness of the
1137 AArch32 EL0, and is deprecated in ARMv8.
1139 Say Y here to enable software emulation of the instruction
1140 for AArch32 userspace code.
1142 Note: All the cpus on the system must have mixed endian support at EL0
1143 for this feature to be enabled. If a new CPU - which doesn't support mixed
1144 endian - is hotplugged in after this feature has been enabled, there could
1145 be unexpected results in the applications.
1150 config ARM64_SW_TTBR0_PAN
1151 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1153 Enabling this option prevents the kernel from accessing
1154 user-space memory directly by pointing TTBR0_EL1 to a reserved
1155 zeroed area and reserved ASID. The user access routines
1156 restore the valid TTBR0_EL1 temporarily.
1158 menu "ARMv8.1 architectural features"
1160 config ARM64_HW_AFDBM
1161 bool "Support for hardware updates of the Access and Dirty page flags"
1164 The ARMv8.1 architecture extensions introduce support for
1165 hardware updates of the access and dirty information in page
1166 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1167 capable processors, accesses to pages with PTE_AF cleared will
1168 set this bit instead of raising an access flag fault.
1169 Similarly, writes to read-only pages with the DBM bit set will
1170 clear the read-only bit (AP[2]) instead of raising a
1173 Kernels built with this configuration option enabled continue
1174 to work on pre-ARMv8.1 hardware and the performance impact is
1175 minimal. If unsure, say Y.
1178 bool "Enable support for Privileged Access Never (PAN)"
1181 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1182 prevents the kernel or hypervisor from accessing user-space (EL0)
1185 Choosing this option will cause any unprotected (not using
1186 copy_to_user et al) memory access to fail with a permission fault.
1188 The feature is detected at runtime, and will remain as a 'nop'
1189 instruction if the cpu does not implement the feature.
1191 config ARM64_LSE_ATOMICS
1192 bool "Atomic instructions"
1195 As part of the Large System Extensions, ARMv8.1 introduces new
1196 atomic instructions that are designed specifically to scale in
1199 Say Y here to make use of these instructions for the in-kernel
1200 atomic routines. This incurs a small overhead on CPUs that do
1201 not support these instructions and requires the kernel to be
1202 built with binutils >= 2.25 in order for the new instructions
1206 bool "Enable support for Virtualization Host Extensions (VHE)"
1209 Virtualization Host Extensions (VHE) allow the kernel to run
1210 directly at EL2 (instead of EL1) on processors that support
1211 it. This leads to better performance for KVM, as they reduce
1212 the cost of the world switch.
1214 Selecting this option allows the VHE feature to be detected
1215 at runtime, and does not affect processors that do not
1216 implement this feature.
1220 menu "ARMv8.2 architectural features"
1223 bool "Enable support for User Access Override (UAO)"
1226 User Access Override (UAO; part of the ARMv8.2 Extensions)
1227 causes the 'unprivileged' variant of the load/store instructions to
1228 be overridden to be privileged.
1230 This option changes get_user() and friends to use the 'unprivileged'
1231 variant of the load/store instructions. This ensures that user-space
1232 really did have access to the supplied memory. When addr_limit is
1233 set to kernel memory the UAO bit will be set, allowing privileged
1234 access to kernel memory.
1236 Choosing this option will cause copy_to_user() et al to use user-space
1239 The feature is detected at runtime, the kernel will use the
1240 regular load/store instructions if the cpu does not implement the
1244 bool "Enable support for persistent memory"
1245 select ARCH_HAS_PMEM_API
1246 select ARCH_HAS_UACCESS_FLUSHCACHE
1248 Say Y to enable support for the persistent memory API based on the
1249 ARMv8.2 DCPoP feature.
1251 The feature is detected at runtime, and the kernel will use DC CVAC
1252 operations if DC CVAP is not supported (following the behaviour of
1253 DC CVAP itself if the system does not define a point of persistence).
1255 config ARM64_RAS_EXTN
1256 bool "Enable support for RAS CPU Extensions"
1259 CPUs that support the Reliability, Availability and Serviceability
1260 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1261 errors, classify them and report them to software.
1263 On CPUs with these extensions system software can use additional
1264 barriers to determine if faults are pending and read the
1265 classification from a new set of registers.
1267 Selecting this feature will allow the kernel to use these barriers
1268 and access the new registers if the system supports the extension.
1269 Platform RAS features may additionally depend on firmware support.
1272 bool "Enable support for Common Not Private (CNP) translations"
1274 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1276 Common Not Private (CNP) allows translation table entries to
1277 be shared between different PEs in the same inner shareable
1278 domain, so the hardware can use this fact to optimise the
1279 caching of such entries in the TLB.
1281 Selecting this option allows the CNP feature to be detected
1282 at runtime, and does not affect PEs that do not implement
1287 menu "ARMv8.3 architectural features"
1289 config ARM64_PTR_AUTH
1290 bool "Enable support for pointer authentication"
1293 Pointer authentication (part of the ARMv8.3 Extensions) provides
1294 instructions for signing and authenticating pointers against secret
1295 keys, which can be used to mitigate Return Oriented Programming (ROP)
1298 This option enables these instructions at EL0 (i.e. for userspace).
1300 Choosing this option will cause the kernel to initialise secret keys
1301 for each process at exec() time, with these keys being
1302 context-switched along with the process.
1304 The feature is detected at runtime. If the feature is not present in
1305 hardware it will not be advertised to userspace nor will it be
1311 bool "ARM Scalable Vector Extension support"
1313 depends on !KVM || ARM64_VHE
1315 The Scalable Vector Extension (SVE) is an extension to the AArch64
1316 execution state which complements and extends the SIMD functionality
1317 of the base architecture to support much larger vectors and to enable
1318 additional vectorisation opportunities.
1320 To enable use of this extension on CPUs that implement it, say Y.
1322 Note that for architectural reasons, firmware _must_ implement SVE
1323 support when running on SVE capable hardware. The required support
1326 * version 1.5 and later of the ARM Trusted Firmware
1327 * the AArch64 boot wrapper since commit 5e1261e08abf
1328 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1330 For other firmware implementations, consult the firmware documentation
1333 If you need the kernel to boot on SVE-capable hardware with broken
1334 firmware, you may need to say N here until you get your firmware
1335 fixed. Otherwise, you may experience firmware panics or lockups when
1336 booting the kernel. If unsure and you are not observing these
1337 symptoms, you should assume that it is safe to say Y.
1339 CPUs that support SVE are architecturally required to support the
1340 Virtualization Host Extensions (VHE), so the kernel makes no
1341 provision for supporting SVE alongside KVM without VHE enabled.
1342 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1343 KVM in the same kernel image.
1345 config ARM64_MODULE_PLTS
1347 select HAVE_MOD_ARCH_SPECIFIC
1349 config ARM64_PSEUDO_NMI
1350 bool "Support for NMI-like interrupts"
1351 select CONFIG_ARM_GIC_V3
1353 Adds support for mimicking Non-Maskable Interrupts through the use of
1354 GIC interrupt priority. This support requires version 3 or later of
1357 This high priority configuration for interrupts needs to be
1358 explicitly enabled by setting the kernel parameter
1359 "irqchip.gicv3_pseudo_nmi" to 1.
1366 This builds the kernel as a Position Independent Executable (PIE),
1367 which retains all relocation metadata required to relocate the
1368 kernel binary at runtime to a different virtual address than the
1369 address it was linked at.
1370 Since AArch64 uses the RELA relocation format, this requires a
1371 relocation pass at runtime even if the kernel is loaded at the
1372 same address it was linked at.
1374 config RANDOMIZE_BASE
1375 bool "Randomize the address of the kernel image"
1376 select ARM64_MODULE_PLTS if MODULES
1379 Randomizes the virtual address at which the kernel image is
1380 loaded, as a security feature that deters exploit attempts
1381 relying on knowledge of the location of kernel internals.
1383 It is the bootloader's job to provide entropy, by passing a
1384 random u64 value in /chosen/kaslr-seed at kernel entry.
1386 When booting via the UEFI stub, it will invoke the firmware's
1387 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1388 to the kernel proper. In addition, it will randomise the physical
1389 location of the kernel Image as well.
1393 config RANDOMIZE_MODULE_REGION_FULL
1394 bool "Randomize the module region over a 4 GB range"
1395 depends on RANDOMIZE_BASE
1398 Randomizes the location of the module region inside a 4 GB window
1399 covering the core kernel. This way, it is less likely for modules
1400 to leak information about the location of core kernel data structures
1401 but it does imply that function calls between modules and the core
1402 kernel will need to be resolved via veneers in the module PLT.
1404 When this option is not set, the module region will be randomized over
1405 a limited range that contains the [_stext, _etext] interval of the
1406 core kernel, so branch relocations are always in range.
1408 config CC_HAVE_STACKPROTECTOR_SYSREG
1409 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1411 config STACKPROTECTOR_PER_TASK
1413 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1419 config ARM64_ACPI_PARKING_PROTOCOL
1420 bool "Enable support for the ARM64 ACPI parking protocol"
1423 Enable support for the ARM64 ACPI parking protocol. If disabled
1424 the kernel will not allow booting through the ARM64 ACPI parking
1425 protocol even if the corresponding data is present in the ACPI
1429 string "Default kernel command string"
1432 Provide a set of default command-line options at build time by
1433 entering them here. As a minimum, you should specify the the
1434 root device (e.g. root=/dev/nfs).
1436 config CMDLINE_FORCE
1437 bool "Always use the default kernel command string"
1439 Always use the default kernel command string, even if the boot
1440 loader passes other arguments to the kernel.
1441 This is useful if you cannot or don't want to change the
1442 command-line options your boot loader passes to the kernel.
1448 bool "UEFI runtime support"
1449 depends on OF && !CPU_BIG_ENDIAN
1450 depends on KERNEL_MODE_NEON
1451 select ARCH_SUPPORTS_ACPI
1454 select EFI_PARAMS_FROM_FDT
1455 select EFI_RUNTIME_WRAPPERS
1460 This option provides support for runtime services provided
1461 by UEFI firmware (such as non-volatile variables, realtime
1462 clock, and platform reset). A UEFI stub is also provided to
1463 allow the kernel to be booted as an EFI application. This
1464 is only useful on systems that have UEFI firmware.
1467 bool "Enable support for SMBIOS (DMI) tables"
1471 This enables SMBIOS/DMI feature for systems.
1473 This option is only useful on systems that have UEFI firmware.
1474 However, even with this option, the resultant kernel should
1475 continue to boot on existing non-UEFI platforms.
1480 bool "Kernel support for 32-bit EL0"
1481 depends on ARM64_4K_PAGES || EXPERT
1482 select COMPAT_BINFMT_ELF if BINFMT_ELF
1484 select OLD_SIGSUSPEND3
1485 select COMPAT_OLD_SIGACTION
1487 This option enables support for a 32-bit EL0 running under a 64-bit
1488 kernel at EL1. AArch32-specific components such as system calls,
1489 the user helper functions, VFP support and the ptrace interface are
1490 handled appropriately by the kernel.
1492 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1493 that you will only be able to execute AArch32 binaries that were compiled
1494 with page size aligned segments.
1496 If you want to execute 32-bit userspace applications, say Y.
1498 config SYSVIPC_COMPAT
1500 depends on COMPAT && SYSVIPC
1502 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1504 depends on HUGETLB_PAGE && MIGRATION
1506 menu "Power management options"
1508 source "kernel/power/Kconfig"
1510 config ARCH_HIBERNATION_POSSIBLE
1514 config ARCH_HIBERNATION_HEADER
1516 depends on HIBERNATION
1518 config ARCH_SUSPEND_POSSIBLE
1523 menu "CPU Power Management"
1525 source "drivers/cpuidle/Kconfig"
1527 source "drivers/cpufreq/Kconfig"
1531 source "drivers/firmware/Kconfig"
1533 source "drivers/acpi/Kconfig"
1535 source "arch/arm64/kvm/Kconfig"
1538 source "arch/arm64/crypto/Kconfig"