1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_WX
13 select ARCH_BINFMT_ELF_STATE
14 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
15 select ARCH_ENABLE_MEMORY_HOTPLUG
16 select ARCH_ENABLE_MEMORY_HOTREMOVE
17 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
18 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
19 select ARCH_HAS_CACHE_LINE_SIZE
20 select ARCH_HAS_DEBUG_VIRTUAL
21 select ARCH_HAS_DEBUG_VM_PGTABLE
22 select ARCH_HAS_DMA_PREP_COHERENT
23 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
24 select ARCH_HAS_FAST_MULTIPLIER
25 select ARCH_HAS_FORTIFY_SOURCE
26 select ARCH_HAS_GCOV_PROFILE_ALL
27 select ARCH_HAS_GIGANTIC_PAGE
29 select ARCH_HAS_KEEPINITRD
30 select ARCH_HAS_MEMBARRIER_SYNC_CORE
31 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
32 select ARCH_HAS_PTE_DEVMAP
33 select ARCH_HAS_PTE_SPECIAL
34 select ARCH_HAS_SETUP_DMA_OPS
35 select ARCH_HAS_SET_DIRECT_MAP
36 select ARCH_HAS_SET_MEMORY
38 select ARCH_HAS_STRICT_KERNEL_RWX
39 select ARCH_HAS_STRICT_MODULE_RWX
40 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
41 select ARCH_HAS_SYNC_DMA_FOR_CPU
42 select ARCH_HAS_SYSCALL_WRAPPER
43 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
44 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
45 select ARCH_HAS_ZONE_DMA_SET if EXPERT
46 select ARCH_HAVE_ELF_PROT
47 select ARCH_HAVE_NMI_SAFE_CMPXCHG
48 select ARCH_INLINE_READ_LOCK if !PREEMPTION
49 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
50 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
51 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
52 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
53 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
54 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
55 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
56 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
57 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
58 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
59 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
60 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
61 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
62 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
63 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
64 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
65 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
66 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
67 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
68 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
69 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
70 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
71 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
72 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
73 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
74 select ARCH_KEEP_MEMBLOCK
75 select ARCH_USE_CMPXCHG_LOCKREF
76 select ARCH_USE_GNU_PROPERTY
77 select ARCH_USE_MEMTEST
78 select ARCH_USE_QUEUED_RWLOCKS
79 select ARCH_USE_QUEUED_SPINLOCKS
80 select ARCH_USE_SYM_ANNOTATIONS
81 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
82 select ARCH_SUPPORTS_HUGETLBFS
83 select ARCH_SUPPORTS_MEMORY_FAILURE
84 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
85 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
86 select ARCH_SUPPORTS_LTO_CLANG_THIN
87 select ARCH_SUPPORTS_CFI_CLANG
88 select ARCH_SUPPORTS_ATOMIC_RMW
89 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG)
90 select ARCH_SUPPORTS_NUMA_BALANCING
91 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
92 select ARCH_WANT_DEFAULT_BPF_JIT
93 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
94 select ARCH_WANT_FRAME_POINTERS
95 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
96 select ARCH_WANT_LD_ORPHAN_WARN
97 select ARCH_WANTS_NO_INSTR
98 select ARCH_HAS_UBSAN_SANITIZE_ALL
100 select ARM_ARCH_TIMER
102 select AUDIT_ARCH_COMPAT_GENERIC
103 select ARM_GIC_V2M if PCI
105 select ARM_GIC_V3_ITS if PCI
107 select BUILDTIME_TABLE_SORT
108 select CLONE_BACKWARDS
110 select CPU_PM if (SUSPEND || CPU_IDLE)
112 select DCACHE_WORD_ACCESS
113 select DMA_DIRECT_REMAP
116 select GENERIC_ALLOCATOR
117 select GENERIC_ARCH_TOPOLOGY
118 select GENERIC_CLOCKEVENTS_BROADCAST
119 select GENERIC_CPU_AUTOPROBE
120 select GENERIC_CPU_VULNERABILITIES
121 select GENERIC_EARLY_IOREMAP
122 select GENERIC_FIND_FIRST_BIT
123 select GENERIC_IDLE_POLL_SETUP
124 select GENERIC_IRQ_IPI
125 select GENERIC_IRQ_PROBE
126 select GENERIC_IRQ_SHOW
127 select GENERIC_IRQ_SHOW_LEVEL
128 select GENERIC_LIB_DEVMEM_IS_ALLOWED
129 select GENERIC_PCI_IOMAP
130 select GENERIC_PTDUMP
131 select GENERIC_SCHED_CLOCK
132 select GENERIC_SMP_IDLE_THREAD
133 select GENERIC_STRNCPY_FROM_USER
134 select GENERIC_STRNLEN_USER
135 select GENERIC_TIME_VSYSCALL
136 select GENERIC_GETTIMEOFDAY
137 select GENERIC_VDSO_TIME_NS
138 select HANDLE_DOMAIN_IRQ
139 select HARDIRQS_SW_RESEND
143 select HAVE_ACPI_APEI if (ACPI && EFI)
144 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
145 select HAVE_ARCH_AUDITSYSCALL
146 select HAVE_ARCH_BITREVERSE
147 select HAVE_ARCH_COMPILER_H
148 select HAVE_ARCH_HUGE_VMAP
149 select HAVE_ARCH_JUMP_LABEL
150 select HAVE_ARCH_JUMP_LABEL_RELATIVE
151 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
152 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
153 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
154 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
155 select HAVE_ARCH_KFENCE
156 select HAVE_ARCH_KGDB
157 select HAVE_ARCH_MMAP_RND_BITS
158 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
159 select HAVE_ARCH_PREL32_RELOCATIONS
160 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
161 select HAVE_ARCH_SECCOMP_FILTER
162 select HAVE_ARCH_STACKLEAK
163 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
164 select HAVE_ARCH_TRACEHOOK
165 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
166 select HAVE_ARCH_VMAP_STACK
167 select HAVE_ARM_SMCCC
168 select HAVE_ASM_MODVERSIONS
170 select HAVE_C_RECORDMCOUNT
171 select HAVE_CMPXCHG_DOUBLE
172 select HAVE_CMPXCHG_LOCAL
173 select HAVE_CONTEXT_TRACKING
174 select HAVE_DEBUG_KMEMLEAK
175 select HAVE_DMA_CONTIGUOUS
176 select HAVE_DYNAMIC_FTRACE
177 select HAVE_DYNAMIC_FTRACE_WITH_REGS \
178 if $(cc-option,-fpatchable-function-entry=2)
179 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
180 if DYNAMIC_FTRACE_WITH_REGS
181 select HAVE_EFFICIENT_UNALIGNED_ACCESS
183 select HAVE_FTRACE_MCOUNT_RECORD
184 select HAVE_FUNCTION_TRACER
185 select HAVE_FUNCTION_ERROR_INJECTION
186 select HAVE_FUNCTION_GRAPH_TRACER
187 select HAVE_GCC_PLUGINS
188 select HAVE_HW_BREAKPOINT if PERF_EVENTS
189 select HAVE_IRQ_TIME_ACCOUNTING
191 select HAVE_PATA_PLATFORM
192 select HAVE_PERF_EVENTS
193 select HAVE_PERF_REGS
194 select HAVE_PERF_USER_STACK_DUMP
195 select HAVE_REGS_AND_STACK_ACCESS_API
196 select HAVE_FUNCTION_ARG_ACCESS_API
197 select HAVE_FUTEX_CMPXCHG if FUTEX
198 select MMU_GATHER_RCU_TABLE_FREE
200 select HAVE_STACKPROTECTOR
201 select HAVE_SYSCALL_TRACEPOINTS
203 select HAVE_KRETPROBES
204 select HAVE_GENERIC_VDSO
205 select IOMMU_DMA if IOMMU_SUPPORT
207 select IRQ_FORCED_THREADING
208 select KASAN_VMALLOC if KASAN_GENERIC
209 select MODULES_USE_ELF_RELA
210 select NEED_DMA_MAP_STATE
211 select NEED_SG_DMA_LENGTH
213 select OF_EARLY_FLATTREE
214 select PCI_DOMAINS_GENERIC if PCI
215 select PCI_ECAM if (ACPI && PCI)
216 select PCI_SYSCALL if PCI
221 select SYSCTL_EXCEPTION_TRACE
222 select THREAD_INFO_IN_TASK
223 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
225 ARM 64-bit (AArch64) Linux support.
233 config ARM64_PAGE_SHIFT
235 default 16 if ARM64_64K_PAGES
236 default 14 if ARM64_16K_PAGES
239 config ARM64_CONT_PTE_SHIFT
241 default 5 if ARM64_64K_PAGES
242 default 7 if ARM64_16K_PAGES
245 config ARM64_CONT_PMD_SHIFT
247 default 5 if ARM64_64K_PAGES
248 default 5 if ARM64_16K_PAGES
251 config ARCH_MMAP_RND_BITS_MIN
252 default 14 if ARM64_64K_PAGES
253 default 16 if ARM64_16K_PAGES
256 # max bits determined by the following formula:
257 # VA_BITS - PAGE_SHIFT - 3
258 config ARCH_MMAP_RND_BITS_MAX
259 default 19 if ARM64_VA_BITS=36
260 default 24 if ARM64_VA_BITS=39
261 default 27 if ARM64_VA_BITS=42
262 default 30 if ARM64_VA_BITS=47
263 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
264 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
265 default 33 if ARM64_VA_BITS=48
266 default 14 if ARM64_64K_PAGES
267 default 16 if ARM64_16K_PAGES
270 config ARCH_MMAP_RND_COMPAT_BITS_MIN
271 default 7 if ARM64_64K_PAGES
272 default 9 if ARM64_16K_PAGES
275 config ARCH_MMAP_RND_COMPAT_BITS_MAX
281 config STACKTRACE_SUPPORT
284 config ILLEGAL_POINTER_VALUE
286 default 0xdead000000000000
288 config LOCKDEP_SUPPORT
291 config TRACE_IRQFLAGS_SUPPORT
298 config GENERIC_BUG_RELATIVE_POINTERS
300 depends on GENERIC_BUG
302 config GENERIC_HWEIGHT
308 config GENERIC_CALIBRATE_DELAY
311 config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
317 config KERNEL_MODE_NEON
320 config FIX_EARLYCON_MEM
323 config PGTABLE_LEVELS
325 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
326 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
327 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
328 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
329 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
330 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
332 config ARCH_SUPPORTS_UPROBES
335 config ARCH_PROC_KCORE_TEXT
338 config BROKEN_GAS_INST
339 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
341 config KASAN_SHADOW_OFFSET
343 depends on KASAN_GENERIC || KASAN_SW_TAGS
344 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
345 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
346 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
347 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
348 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
349 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
350 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
351 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
352 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
353 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
354 default 0xffffffffffffffff
356 source "arch/arm64/Kconfig.platforms"
358 menu "Kernel Features"
360 menu "ARM errata workarounds via the alternatives framework"
362 config ARM64_WORKAROUND_CLEAN_CACHE
365 config ARM64_ERRATUM_826319
366 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
368 select ARM64_WORKAROUND_CLEAN_CACHE
370 This option adds an alternative code sequence to work around ARM
371 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
372 AXI master interface and an L2 cache.
374 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
375 and is unable to accept a certain write via this interface, it will
376 not progress on read data presented on the read data channel and the
379 The workaround promotes data cache clean instructions to
380 data cache clean-and-invalidate.
381 Please note that this does not necessarily enable the workaround,
382 as it depends on the alternative framework, which will only patch
383 the kernel if an affected CPU is detected.
387 config ARM64_ERRATUM_827319
388 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
390 select ARM64_WORKAROUND_CLEAN_CACHE
392 This option adds an alternative code sequence to work around ARM
393 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
394 master interface and an L2 cache.
396 Under certain conditions this erratum can cause a clean line eviction
397 to occur at the same time as another transaction to the same address
398 on the AMBA 5 CHI interface, which can cause data corruption if the
399 interconnect reorders the two transactions.
401 The workaround promotes data cache clean instructions to
402 data cache clean-and-invalidate.
403 Please note that this does not necessarily enable the workaround,
404 as it depends on the alternative framework, which will only patch
405 the kernel if an affected CPU is detected.
409 config ARM64_ERRATUM_824069
410 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
412 select ARM64_WORKAROUND_CLEAN_CACHE
414 This option adds an alternative code sequence to work around ARM
415 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
416 to a coherent interconnect.
418 If a Cortex-A53 processor is executing a store or prefetch for
419 write instruction at the same time as a processor in another
420 cluster is executing a cache maintenance operation to the same
421 address, then this erratum might cause a clean cache line to be
422 incorrectly marked as dirty.
424 The workaround promotes data cache clean instructions to
425 data cache clean-and-invalidate.
426 Please note that this option does not necessarily enable the
427 workaround, as it depends on the alternative framework, which will
428 only patch the kernel if an affected CPU is detected.
432 config ARM64_ERRATUM_819472
433 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
435 select ARM64_WORKAROUND_CLEAN_CACHE
437 This option adds an alternative code sequence to work around ARM
438 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
439 present when it is connected to a coherent interconnect.
441 If the processor is executing a load and store exclusive sequence at
442 the same time as a processor in another cluster is executing a cache
443 maintenance operation to the same address, then this erratum might
444 cause data corruption.
446 The workaround promotes data cache clean instructions to
447 data cache clean-and-invalidate.
448 Please note that this does not necessarily enable the workaround,
449 as it depends on the alternative framework, which will only patch
450 the kernel if an affected CPU is detected.
454 config ARM64_ERRATUM_832075
455 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
458 This option adds an alternative code sequence to work around ARM
459 erratum 832075 on Cortex-A57 parts up to r1p2.
461 Affected Cortex-A57 parts might deadlock when exclusive load/store
462 instructions to Write-Back memory are mixed with Device loads.
464 The workaround is to promote device loads to use Load-Acquire
466 Please note that this does not necessarily enable the workaround,
467 as it depends on the alternative framework, which will only patch
468 the kernel if an affected CPU is detected.
472 config ARM64_ERRATUM_834220
473 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
477 This option adds an alternative code sequence to work around ARM
478 erratum 834220 on Cortex-A57 parts up to r1p2.
480 Affected Cortex-A57 parts might report a Stage 2 translation
481 fault as the result of a Stage 1 fault for load crossing a
482 page boundary when there is a permission or device memory
483 alignment fault at Stage 1 and a translation fault at Stage 2.
485 The workaround is to verify that the Stage 1 translation
486 doesn't generate a fault before handling the Stage 2 fault.
487 Please note that this does not necessarily enable the workaround,
488 as it depends on the alternative framework, which will only patch
489 the kernel if an affected CPU is detected.
493 config ARM64_ERRATUM_845719
494 bool "Cortex-A53: 845719: a load might read incorrect data"
498 This option adds an alternative code sequence to work around ARM
499 erratum 845719 on Cortex-A53 parts up to r0p4.
501 When running a compat (AArch32) userspace on an affected Cortex-A53
502 part, a load at EL0 from a virtual address that matches the bottom 32
503 bits of the virtual address used by a recent load at (AArch64) EL1
504 might return incorrect data.
506 The workaround is to write the contextidr_el1 register on exception
507 return to a 32-bit task.
508 Please note that this does not necessarily enable the workaround,
509 as it depends on the alternative framework, which will only patch
510 the kernel if an affected CPU is detected.
514 config ARM64_ERRATUM_843419
515 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
517 select ARM64_MODULE_PLTS if MODULES
519 This option links the kernel with '--fix-cortex-a53-843419' and
520 enables PLT support to replace certain ADRP instructions, which can
521 cause subsequent memory accesses to use an incorrect address on
522 Cortex-A53 parts up to r0p4.
526 config ARM64_LD_HAS_FIX_ERRATUM_843419
527 def_bool $(ld-option,--fix-cortex-a53-843419)
529 config ARM64_ERRATUM_1024718
530 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
533 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
535 Affected Cortex-A55 cores (all revisions) could cause incorrect
536 update of the hardware dirty bit when the DBM/AP bits are updated
537 without a break-before-make. The workaround is to disable the usage
538 of hardware DBM locally on the affected cores. CPUs not affected by
539 this erratum will continue to use the feature.
543 config ARM64_ERRATUM_1418040
544 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
548 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
549 errata 1188873 and 1418040.
551 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
552 cause register corruption when accessing the timer registers
553 from AArch32 userspace.
557 config ARM64_WORKAROUND_SPECULATIVE_AT
560 config ARM64_ERRATUM_1165522
561 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
563 select ARM64_WORKAROUND_SPECULATIVE_AT
565 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
567 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
568 corrupted TLBs by speculating an AT instruction during a guest
573 config ARM64_ERRATUM_1319367
574 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
576 select ARM64_WORKAROUND_SPECULATIVE_AT
578 This option adds work arounds for ARM Cortex-A57 erratum 1319537
579 and A72 erratum 1319367
581 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
582 speculating an AT instruction during a guest context switch.
586 config ARM64_ERRATUM_1530923
587 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
589 select ARM64_WORKAROUND_SPECULATIVE_AT
591 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
593 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
594 corrupted TLBs by speculating an AT instruction during a guest
599 config ARM64_WORKAROUND_REPEAT_TLBI
602 config ARM64_ERRATUM_1286807
603 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
605 select ARM64_WORKAROUND_REPEAT_TLBI
607 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
609 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
610 address for a cacheable mapping of a location is being
611 accessed by a core while another core is remapping the virtual
612 address to a new physical page using the recommended
613 break-before-make sequence, then under very rare circumstances
614 TLBI+DSB completes before a read using the translation being
615 invalidated has been observed by other observers. The
616 workaround repeats the TLBI+DSB operation.
618 config ARM64_ERRATUM_1463225
619 bool "Cortex-A76: Software Step might prevent interrupt recognition"
622 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
624 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
625 of a system call instruction (SVC) can prevent recognition of
626 subsequent interrupts when software stepping is disabled in the
627 exception handler of the system call and either kernel debugging
628 is enabled or VHE is in use.
630 Work around the erratum by triggering a dummy step exception
631 when handling a system call from a task that is being stepped
632 in a VHE configuration of the kernel.
636 config ARM64_ERRATUM_1542419
637 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
640 This option adds a workaround for ARM Neoverse-N1 erratum
643 Affected Neoverse-N1 cores could execute a stale instruction when
644 modified by another CPU. The workaround depends on a firmware
647 Workaround the issue by hiding the DIC feature from EL0. This
648 forces user-space to perform cache maintenance.
652 config ARM64_ERRATUM_1508412
653 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
656 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
658 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
659 of a store-exclusive or read of PAR_EL1 and a load with device or
660 non-cacheable memory attributes. The workaround depends on a firmware
663 KVM guests must also have the workaround implemented or they can
666 Work around the issue by inserting DMB SY barriers around PAR_EL1
667 register reads and warning KVM users. The DMB barrier is sufficient
668 to prevent a speculative PAR_EL1 read.
672 config CAVIUM_ERRATUM_22375
673 bool "Cavium erratum 22375, 24313"
676 Enable workaround for errata 22375 and 24313.
678 This implements two gicv3-its errata workarounds for ThunderX. Both
679 with a small impact affecting only ITS table allocation.
681 erratum 22375: only alloc 8MB table size
682 erratum 24313: ignore memory access type
684 The fixes are in ITS initialization and basically ignore memory access
685 type and table size provided by the TYPER and BASER registers.
689 config CAVIUM_ERRATUM_23144
690 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
694 ITS SYNC command hang for cross node io and collections/cpu mapping.
698 config CAVIUM_ERRATUM_23154
699 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
702 The gicv3 of ThunderX requires a modified version for
703 reading the IAR status to ensure data synchronization
704 (access to icc_iar1_el1 is not sync'ed before and after).
708 config CAVIUM_ERRATUM_27456
709 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
712 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
713 instructions may cause the icache to become corrupted if it
714 contains data for a non-current ASID. The fix is to
715 invalidate the icache when changing the mm context.
719 config CAVIUM_ERRATUM_30115
720 bool "Cavium erratum 30115: Guest may disable interrupts in host"
723 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
724 1.2, and T83 Pass 1.0, KVM guest execution may disable
725 interrupts in host. Trapping both GICv3 group-0 and group-1
726 accesses sidesteps the issue.
730 config CAVIUM_TX2_ERRATUM_219
731 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
734 On Cavium ThunderX2, a load, store or prefetch instruction between a
735 TTBR update and the corresponding context synchronizing operation can
736 cause a spurious Data Abort to be delivered to any hardware thread in
739 Work around the issue by avoiding the problematic code sequence and
740 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
741 trap handler performs the corresponding register access, skips the
742 instruction and ensures context synchronization by virtue of the
747 config FUJITSU_ERRATUM_010001
748 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
751 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
752 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
753 accesses may cause undefined fault (Data abort, DFSC=0b111111).
754 This fault occurs under a specific hardware condition when a
755 load/store instruction performs an address translation using:
756 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
757 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
758 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
759 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
761 The workaround is to ensure these bits are clear in TCR_ELx.
762 The workaround only affects the Fujitsu-A64FX.
766 config HISILICON_ERRATUM_161600802
767 bool "Hip07 161600802: Erroneous redistributor VLPI base"
770 The HiSilicon Hip07 SoC uses the wrong redistributor base
771 when issued ITS commands such as VMOVP and VMAPP, and requires
772 a 128kB offset to be applied to the target address in this commands.
776 config QCOM_FALKOR_ERRATUM_1003
777 bool "Falkor E1003: Incorrect translation due to ASID change"
780 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
781 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
782 in TTBR1_EL1, this situation only occurs in the entry trampoline and
783 then only for entries in the walk cache, since the leaf translation
784 is unchanged. Work around the erratum by invalidating the walk cache
785 entries for the trampoline before entering the kernel proper.
787 config QCOM_FALKOR_ERRATUM_1009
788 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
790 select ARM64_WORKAROUND_REPEAT_TLBI
792 On Falkor v1, the CPU may prematurely complete a DSB following a
793 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
794 one more time to fix the issue.
798 config QCOM_QDF2400_ERRATUM_0065
799 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
802 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
803 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
804 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
808 config QCOM_FALKOR_ERRATUM_E1041
809 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
812 Falkor CPU may speculatively fetch instructions from an improper
813 memory location when MMU translation is changed from SCTLR_ELn[M]=1
814 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
818 config NVIDIA_CARMEL_CNP_ERRATUM
819 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
822 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
823 invalidate shared TLB entries installed by a different core, as it would
824 on standard ARM cores.
828 config SOCIONEXT_SYNQUACER_PREITS
829 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
832 Socionext Synquacer SoCs implement a separate h/w block to generate
833 MSI doorbell writes with non-zero values for the device ID.
842 default ARM64_4K_PAGES
844 Page size (translation granule) configuration.
846 config ARM64_4K_PAGES
849 This feature enables 4KB pages support.
851 config ARM64_16K_PAGES
854 The system will use 16KB pages support. AArch32 emulation
855 requires applications compiled with 16K (or a multiple of 16K)
858 config ARM64_64K_PAGES
861 This feature enables 64KB pages support (4KB by default)
862 allowing only two levels of page tables and faster TLB
863 look-up. AArch32 emulation requires applications compiled
864 with 64K aligned segments.
869 prompt "Virtual address space size"
870 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
871 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
872 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
874 Allows choosing one of multiple possible virtual address
875 space sizes. The level of translation table is determined by
876 a combination of page size and virtual address space size.
878 config ARM64_VA_BITS_36
879 bool "36-bit" if EXPERT
880 depends on ARM64_16K_PAGES
882 config ARM64_VA_BITS_39
884 depends on ARM64_4K_PAGES
886 config ARM64_VA_BITS_42
888 depends on ARM64_64K_PAGES
890 config ARM64_VA_BITS_47
892 depends on ARM64_16K_PAGES
894 config ARM64_VA_BITS_48
897 config ARM64_VA_BITS_52
899 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
901 Enable 52-bit virtual addressing for userspace when explicitly
902 requested via a hint to mmap(). The kernel will also use 52-bit
903 virtual addresses for its own mappings (provided HW support for
904 this feature is available, otherwise it reverts to 48-bit).
906 NOTE: Enabling 52-bit virtual addressing in conjunction with
907 ARMv8.3 Pointer Authentication will result in the PAC being
908 reduced from 7 bits to 3 bits, which may have a significant
909 impact on its susceptibility to brute-force attacks.
911 If unsure, select 48-bit virtual addressing instead.
915 config ARM64_FORCE_52BIT
916 bool "Force 52-bit virtual addresses for userspace"
917 depends on ARM64_VA_BITS_52 && EXPERT
919 For systems with 52-bit userspace VAs enabled, the kernel will attempt
920 to maintain compatibility with older software by providing 48-bit VAs
921 unless a hint is supplied to mmap.
923 This configuration option disables the 48-bit compatibility logic, and
924 forces all userspace addresses to be 52-bit on HW that supports it. One
925 should only enable this configuration option for stress testing userspace
926 memory management code. If unsure say N here.
930 default 36 if ARM64_VA_BITS_36
931 default 39 if ARM64_VA_BITS_39
932 default 42 if ARM64_VA_BITS_42
933 default 47 if ARM64_VA_BITS_47
934 default 48 if ARM64_VA_BITS_48
935 default 52 if ARM64_VA_BITS_52
938 prompt "Physical address space size"
939 default ARM64_PA_BITS_48
941 Choose the maximum physical address range that the kernel will
944 config ARM64_PA_BITS_48
947 config ARM64_PA_BITS_52
948 bool "52-bit (ARMv8.2)"
949 depends on ARM64_64K_PAGES
950 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
952 Enable support for a 52-bit physical address space, introduced as
953 part of the ARMv8.2-LPA extension.
955 With this enabled, the kernel will also continue to work on CPUs that
956 do not support ARMv8.2-LPA, but with some added memory overhead (and
957 minor performance overhead).
963 default 48 if ARM64_PA_BITS_48
964 default 52 if ARM64_PA_BITS_52
968 default CPU_LITTLE_ENDIAN
970 Select the endianness of data accesses performed by the CPU. Userspace
971 applications will need to be compiled and linked for the endianness
972 that is selected here.
974 config CPU_BIG_ENDIAN
975 bool "Build big-endian kernel"
976 depends on !LD_IS_LLD || LLD_VERSION >= 130000
978 Say Y if you plan on running a kernel with a big-endian userspace.
980 config CPU_LITTLE_ENDIAN
981 bool "Build little-endian kernel"
983 Say Y if you plan on running a kernel with a little-endian userspace.
984 This is usually the case for distributions targeting arm64.
989 bool "Multi-core scheduler support"
991 Multi-core scheduler support improves the CPU scheduler's decision
992 making when dealing with multi-core CPU chips at a cost of slightly
993 increased overhead in some places. If unsure say N here.
996 bool "SMT scheduler support"
998 Improves the CPU scheduler's decision making when dealing with
999 MultiThreading at a cost of slightly increased overhead in some
1000 places. If unsure say N here.
1003 int "Maximum number of CPUs (2-4096)"
1008 bool "Support for hot-pluggable CPUs"
1009 select GENERIC_IRQ_MIGRATION
1011 Say Y here to experiment with turning CPUs off and on. CPUs
1012 can be controlled through /sys/devices/system/cpu.
1014 # Common NUMA Features
1016 bool "NUMA Memory Allocation and Scheduler Support"
1017 select GENERIC_ARCH_NUMA
1018 select ACPI_NUMA if ACPI
1021 Enable NUMA (Non-Uniform Memory Access) support.
1023 The kernel will try to allocate memory used by a CPU on the
1024 local memory of the CPU and add some more
1025 NUMA awareness to the kernel.
1028 int "Maximum NUMA Nodes (as a power of 2)"
1033 Specify the maximum number of NUMA Nodes available on the target
1034 system. Increases memory reserved to accommodate various tables.
1036 config USE_PERCPU_NUMA_NODE_ID
1040 config HAVE_SETUP_PER_CPU_AREA
1044 config NEED_PER_CPU_EMBED_FIRST_CHUNK
1048 source "kernel/Kconfig.hz"
1050 config ARCH_SPARSEMEM_ENABLE
1052 select SPARSEMEM_VMEMMAP_ENABLE
1053 select SPARSEMEM_VMEMMAP
1055 config HW_PERF_EVENTS
1059 config ARCH_HAS_FILTER_PGPROT
1062 # Supported by clang >= 7.0
1063 config CC_HAVE_SHADOW_CALL_STACK
1064 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1067 bool "Enable paravirtualization code"
1069 This changes the kernel so it can modify itself when it is run
1070 under a hypervisor, potentially improving performance significantly
1071 over full virtualization.
1073 config PARAVIRT_TIME_ACCOUNTING
1074 bool "Paravirtual steal time accounting"
1077 Select this option to enable fine granularity task steal time
1078 accounting. Time spent executing other tasks in parallel with
1079 the current vCPU is discounted from the vCPU power. To account for
1080 that, there can be a small performance impact.
1082 If in doubt, say N here.
1085 depends on PM_SLEEP_SMP
1087 bool "kexec system call"
1089 kexec is a system call that implements the ability to shutdown your
1090 current kernel, and to start another kernel. It is like a reboot
1091 but it is independent of the system firmware. And like a reboot
1092 you can start any kernel with it, not just Linux.
1095 bool "kexec file based system call"
1097 select HAVE_IMA_KEXEC if IMA
1099 This is new version of kexec system call. This system call is
1100 file based and takes file descriptors as system call argument
1101 for kernel and initramfs as opposed to list of segments as
1102 accepted by previous system call.
1105 bool "Verify kernel signature during kexec_file_load() syscall"
1106 depends on KEXEC_FILE
1108 Select this option to verify a signature with loaded kernel
1109 image. If configured, any attempt of loading a image without
1110 valid signature will fail.
1112 In addition to that option, you need to enable signature
1113 verification for the corresponding kernel image type being
1114 loaded in order for this to work.
1116 config KEXEC_IMAGE_VERIFY_SIG
1117 bool "Enable Image signature verification support"
1119 depends on KEXEC_SIG
1120 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1122 Enable Image signature verification support.
1124 comment "Support for PE file signature verification disabled"
1125 depends on KEXEC_SIG
1126 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1129 bool "Build kdump crash kernel"
1131 Generate crash dump after being started by kexec. This should
1132 be normally only set in special crash dump kernels which are
1133 loaded in the main kernel with kexec-tools into a specially
1134 reserved region and then later executed after a crash by
1137 For more details see Documentation/admin-guide/kdump/kdump.rst
1141 depends on HIBERNATION
1148 bool "Xen guest support on ARM64"
1149 depends on ARM64 && OF
1153 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1155 config FORCE_MAX_ZONEORDER
1157 default "14" if ARM64_64K_PAGES
1158 default "12" if ARM64_16K_PAGES
1161 The kernel memory allocator divides physically contiguous memory
1162 blocks into "zones", where each zone is a power of two number of
1163 pages. This option selects the largest power of two that the kernel
1164 keeps in the memory allocator. If you need to allocate very large
1165 blocks of physically contiguous memory, then you may need to
1166 increase this value.
1168 This config option is actually maximum order plus one. For example,
1169 a value of 11 means that the largest free memory block is 2^10 pages.
1171 We make sure that we can allocate upto a HugePage size for each configuration.
1173 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1175 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1176 4M allocations matching the default size used by generic code.
1178 config UNMAP_KERNEL_AT_EL0
1179 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1182 Speculation attacks against some high-performance processors can
1183 be used to bypass MMU permission checks and leak kernel data to
1184 userspace. This can be defended against by unmapping the kernel
1185 when running in userspace, mapping it back in on exception entry
1186 via a trampoline page in the vector table.
1190 config RODATA_FULL_DEFAULT_ENABLED
1191 bool "Apply r/o permissions of VM areas also to their linear aliases"
1194 Apply read-only attributes of VM areas to the linear alias of
1195 the backing pages as well. This prevents code or read-only data
1196 from being modified (inadvertently or intentionally) via another
1197 mapping of the same memory page. This additional enhancement can
1198 be turned off at runtime by passing rodata=[off|on] (and turned on
1199 with rodata=full if this option is set to 'n')
1201 This requires the linear region to be mapped down to pages,
1202 which may adversely affect performance in some cases.
1204 config ARM64_SW_TTBR0_PAN
1205 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1207 Enabling this option prevents the kernel from accessing
1208 user-space memory directly by pointing TTBR0_EL1 to a reserved
1209 zeroed area and reserved ASID. The user access routines
1210 restore the valid TTBR0_EL1 temporarily.
1212 config ARM64_TAGGED_ADDR_ABI
1213 bool "Enable the tagged user addresses syscall ABI"
1216 When this option is enabled, user applications can opt in to a
1217 relaxed ABI via prctl() allowing tagged addresses to be passed
1218 to system calls as pointer arguments. For details, see
1219 Documentation/arm64/tagged-address-abi.rst.
1222 bool "Kernel support for 32-bit EL0"
1223 depends on ARM64_4K_PAGES || EXPERT
1225 select OLD_SIGSUSPEND3
1226 select COMPAT_OLD_SIGACTION
1228 This option enables support for a 32-bit EL0 running under a 64-bit
1229 kernel at EL1. AArch32-specific components such as system calls,
1230 the user helper functions, VFP support and the ptrace interface are
1231 handled appropriately by the kernel.
1233 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1234 that you will only be able to execute AArch32 binaries that were compiled
1235 with page size aligned segments.
1237 If you want to execute 32-bit userspace applications, say Y.
1241 config KUSER_HELPERS
1242 bool "Enable kuser helpers page for 32-bit applications"
1245 Warning: disabling this option may break 32-bit user programs.
1247 Provide kuser helpers to compat tasks. The kernel provides
1248 helper code to userspace in read only form at a fixed location
1249 to allow userspace to be independent of the CPU type fitted to
1250 the system. This permits binaries to be run on ARMv4 through
1251 to ARMv8 without modification.
1253 See Documentation/arm/kernel_user_helpers.rst for details.
1255 However, the fixed address nature of these helpers can be used
1256 by ROP (return orientated programming) authors when creating
1259 If all of the binaries and libraries which run on your platform
1260 are built specifically for your platform, and make no use of
1261 these helpers, then you can turn this option off to hinder
1262 such exploits. However, in that case, if a binary or library
1263 relying on those helpers is run, it will not function correctly.
1265 Say N here only if you are absolutely certain that you do not
1266 need these helpers; otherwise, the safe option is to say Y.
1269 bool "Enable vDSO for 32-bit applications"
1270 depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1271 select GENERIC_COMPAT_VDSO
1274 Place in the process address space of 32-bit applications an
1275 ELF shared object providing fast implementations of gettimeofday
1278 You must have a 32-bit build of glibc 2.22 or later for programs
1279 to seamlessly take advantage of this.
1281 config THUMB2_COMPAT_VDSO
1282 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1283 depends on COMPAT_VDSO
1286 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1287 otherwise with '-marm'.
1289 menuconfig ARMV8_DEPRECATED
1290 bool "Emulate deprecated/obsolete ARMv8 instructions"
1293 Legacy software support may require certain instructions
1294 that have been deprecated or obsoleted in the architecture.
1296 Enable this config to enable selective emulation of these
1303 config SWP_EMULATION
1304 bool "Emulate SWP/SWPB instructions"
1306 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1307 they are always undefined. Say Y here to enable software
1308 emulation of these instructions for userspace using LDXR/STXR.
1309 This feature can be controlled at runtime with the abi.swp
1310 sysctl which is disabled by default.
1312 In some older versions of glibc [<=2.8] SWP is used during futex
1313 trylock() operations with the assumption that the code will not
1314 be preempted. This invalid assumption may be more likely to fail
1315 with SWP emulation enabled, leading to deadlock of the user
1318 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1319 on an external transaction monitoring block called a global
1320 monitor to maintain update atomicity. If your system does not
1321 implement a global monitor, this option can cause programs that
1322 perform SWP operations to uncached memory to deadlock.
1326 config CP15_BARRIER_EMULATION
1327 bool "Emulate CP15 Barrier instructions"
1329 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1330 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1331 strongly recommended to use the ISB, DSB, and DMB
1332 instructions instead.
1334 Say Y here to enable software emulation of these
1335 instructions for AArch32 userspace code. When this option is
1336 enabled, CP15 barrier usage is traced which can help
1337 identify software that needs updating. This feature can be
1338 controlled at runtime with the abi.cp15_barrier sysctl.
1342 config SETEND_EMULATION
1343 bool "Emulate SETEND instruction"
1345 The SETEND instruction alters the data-endianness of the
1346 AArch32 EL0, and is deprecated in ARMv8.
1348 Say Y here to enable software emulation of the instruction
1349 for AArch32 userspace code. This feature can be controlled
1350 at runtime with the abi.setend sysctl.
1352 Note: All the cpus on the system must have mixed endian support at EL0
1353 for this feature to be enabled. If a new CPU - which doesn't support mixed
1354 endian - is hotplugged in after this feature has been enabled, there could
1355 be unexpected results in the applications.
1362 menu "ARMv8.1 architectural features"
1364 config ARM64_HW_AFDBM
1365 bool "Support for hardware updates of the Access and Dirty page flags"
1368 The ARMv8.1 architecture extensions introduce support for
1369 hardware updates of the access and dirty information in page
1370 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1371 capable processors, accesses to pages with PTE_AF cleared will
1372 set this bit instead of raising an access flag fault.
1373 Similarly, writes to read-only pages with the DBM bit set will
1374 clear the read-only bit (AP[2]) instead of raising a
1377 Kernels built with this configuration option enabled continue
1378 to work on pre-ARMv8.1 hardware and the performance impact is
1379 minimal. If unsure, say Y.
1382 bool "Enable support for Privileged Access Never (PAN)"
1385 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1386 prevents the kernel or hypervisor from accessing user-space (EL0)
1389 Choosing this option will cause any unprotected (not using
1390 copy_to_user et al) memory access to fail with a permission fault.
1392 The feature is detected at runtime, and will remain as a 'nop'
1393 instruction if the cpu does not implement the feature.
1396 def_bool $(as-instr,.arch_extension rcpc)
1398 config AS_HAS_LSE_ATOMICS
1399 def_bool $(as-instr,.arch_extension lse)
1401 config ARM64_LSE_ATOMICS
1403 default ARM64_USE_LSE_ATOMICS
1404 depends on AS_HAS_LSE_ATOMICS
1406 config ARM64_USE_LSE_ATOMICS
1407 bool "Atomic instructions"
1408 depends on JUMP_LABEL
1411 As part of the Large System Extensions, ARMv8.1 introduces new
1412 atomic instructions that are designed specifically to scale in
1415 Say Y here to make use of these instructions for the in-kernel
1416 atomic routines. This incurs a small overhead on CPUs that do
1417 not support these instructions and requires the kernel to be
1418 built with binutils >= 2.25 in order for the new instructions
1423 menu "ARMv8.2 architectural features"
1426 bool "Enable support for persistent memory"
1427 select ARCH_HAS_PMEM_API
1428 select ARCH_HAS_UACCESS_FLUSHCACHE
1430 Say Y to enable support for the persistent memory API based on the
1431 ARMv8.2 DCPoP feature.
1433 The feature is detected at runtime, and the kernel will use DC CVAC
1434 operations if DC CVAP is not supported (following the behaviour of
1435 DC CVAP itself if the system does not define a point of persistence).
1437 config ARM64_RAS_EXTN
1438 bool "Enable support for RAS CPU Extensions"
1441 CPUs that support the Reliability, Availability and Serviceability
1442 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1443 errors, classify them and report them to software.
1445 On CPUs with these extensions system software can use additional
1446 barriers to determine if faults are pending and read the
1447 classification from a new set of registers.
1449 Selecting this feature will allow the kernel to use these barriers
1450 and access the new registers if the system supports the extension.
1451 Platform RAS features may additionally depend on firmware support.
1454 bool "Enable support for Common Not Private (CNP) translations"
1456 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1458 Common Not Private (CNP) allows translation table entries to
1459 be shared between different PEs in the same inner shareable
1460 domain, so the hardware can use this fact to optimise the
1461 caching of such entries in the TLB.
1463 Selecting this option allows the CNP feature to be detected
1464 at runtime, and does not affect PEs that do not implement
1469 menu "ARMv8.3 architectural features"
1471 config ARM64_PTR_AUTH
1472 bool "Enable support for pointer authentication"
1475 Pointer authentication (part of the ARMv8.3 Extensions) provides
1476 instructions for signing and authenticating pointers against secret
1477 keys, which can be used to mitigate Return Oriented Programming (ROP)
1480 This option enables these instructions at EL0 (i.e. for userspace).
1481 Choosing this option will cause the kernel to initialise secret keys
1482 for each process at exec() time, with these keys being
1483 context-switched along with the process.
1485 The feature is detected at runtime. If the feature is not present in
1486 hardware it will not be advertised to userspace/KVM guest nor will it
1489 If the feature is present on the boot CPU but not on a late CPU, then
1490 the late CPU will be parked. Also, if the boot CPU does not have
1491 address auth and the late CPU has then the late CPU will still boot
1492 but with the feature disabled. On such a system, this option should
1495 config ARM64_PTR_AUTH_KERNEL
1496 bool "Use pointer authentication for kernel"
1498 depends on ARM64_PTR_AUTH
1499 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1500 # Modern compilers insert a .note.gnu.property section note for PAC
1501 # which is only understood by binutils starting with version 2.33.1.
1502 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1503 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1504 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1506 If the compiler supports the -mbranch-protection or
1507 -msign-return-address flag (e.g. GCC 7 or later), then this option
1508 will cause the kernel itself to be compiled with return address
1509 protection. In this case, and if the target hardware is known to
1510 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1511 disabled with minimal loss of protection.
1513 This feature works with FUNCTION_GRAPH_TRACER option only if
1514 DYNAMIC_FTRACE_WITH_REGS is enabled.
1516 config CC_HAS_BRANCH_PROT_PAC_RET
1517 # GCC 9 or later, clang 8 or later
1518 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1520 config CC_HAS_SIGN_RETURN_ADDRESS
1522 def_bool $(cc-option,-msign-return-address=all)
1525 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1527 config AS_HAS_CFI_NEGATE_RA_STATE
1528 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1532 menu "ARMv8.4 architectural features"
1534 config ARM64_AMU_EXTN
1535 bool "Enable support for the Activity Monitors Unit CPU extension"
1538 The activity monitors extension is an optional extension introduced
1539 by the ARMv8.4 CPU architecture. This enables support for version 1
1540 of the activity monitors architecture, AMUv1.
1542 To enable the use of this extension on CPUs that implement it, say Y.
1544 Note that for architectural reasons, firmware _must_ implement AMU
1545 support when running on CPUs that present the activity monitors
1546 extension. The required support is present in:
1547 * Version 1.5 and later of the ARM Trusted Firmware
1549 For kernels that have this configuration enabled but boot with broken
1550 firmware, you may need to say N here until the firmware is fixed.
1551 Otherwise you may experience firmware panics or lockups when
1552 accessing the counter registers. Even if you are not observing these
1553 symptoms, the values returned by the register reads might not
1554 correctly reflect reality. Most commonly, the value read will be 0,
1555 indicating that the counter is not enabled.
1557 config AS_HAS_ARMV8_4
1558 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1560 config ARM64_TLB_RANGE
1561 bool "Enable support for tlbi range feature"
1563 depends on AS_HAS_ARMV8_4
1565 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1566 range of input addresses.
1568 The feature introduces new assembly instructions, and they were
1569 support when binutils >= 2.30.
1573 menu "ARMv8.5 architectural features"
1575 config AS_HAS_ARMV8_5
1576 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1579 bool "Branch Target Identification support"
1582 Branch Target Identification (part of the ARMv8.5 Extensions)
1583 provides a mechanism to limit the set of locations to which computed
1584 branch instructions such as BR or BLR can jump.
1586 To make use of BTI on CPUs that support it, say Y.
1588 BTI is intended to provide complementary protection to other control
1589 flow integrity protection mechanisms, such as the Pointer
1590 authentication mechanism provided as part of the ARMv8.3 Extensions.
1591 For this reason, it does not make sense to enable this option without
1592 also enabling support for pointer authentication. Thus, when
1593 enabling this option you should also select ARM64_PTR_AUTH=y.
1595 Userspace binaries must also be specifically compiled to make use of
1596 this mechanism. If you say N here or the hardware does not support
1597 BTI, such binaries can still run, but you get no additional
1598 enforcement of branch destinations.
1600 config ARM64_BTI_KERNEL
1601 bool "Use Branch Target Identification for kernel"
1603 depends on ARM64_BTI
1604 depends on ARM64_PTR_AUTH_KERNEL
1605 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1606 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1607 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1608 depends on !(CC_IS_CLANG && GCOV_KERNEL)
1609 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1611 Build the kernel with Branch Target Identification annotations
1612 and enable enforcement of this for kernel code. When this option
1613 is enabled and the system supports BTI all kernel code including
1614 modular code must have BTI enabled.
1616 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1617 # GCC 9 or later, clang 8 or later
1618 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1621 bool "Enable support for E0PD"
1624 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1625 that EL0 accesses made via TTBR1 always fault in constant time,
1626 providing similar benefits to KASLR as those provided by KPTI, but
1627 with lower overhead and without disrupting legitimate access to
1628 kernel memory such as SPE.
1630 This option enables E0PD for TTBR1 where available.
1633 bool "Enable support for random number generation"
1636 Random number generation (part of the ARMv8.5 Extensions)
1637 provides a high bandwidth, cryptographically secure
1638 hardware random number generator.
1640 config ARM64_AS_HAS_MTE
1641 # Initial support for MTE went in binutils 2.32.0, checked with
1642 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1643 # as a late addition to the final architecture spec (LDGM/STGM)
1644 # is only supported in the newer 2.32.x and 2.33 binutils
1645 # versions, hence the extra "stgm" instruction check below.
1646 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1649 bool "Memory Tagging Extension support"
1651 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1652 depends on AS_HAS_ARMV8_5
1653 depends on AS_HAS_LSE_ATOMICS
1654 # Required for tag checking in the uaccess routines
1655 depends on ARM64_PAN
1656 select ARCH_USES_HIGH_VMA_FLAGS
1658 Memory Tagging (part of the ARMv8.5 Extensions) provides
1659 architectural support for run-time, always-on detection of
1660 various classes of memory error to aid with software debugging
1661 to eliminate vulnerabilities arising from memory-unsafe
1664 This option enables the support for the Memory Tagging
1665 Extension at EL0 (i.e. for userspace).
1667 Selecting this option allows the feature to be detected at
1668 runtime. Any secondary CPU not implementing this feature will
1669 not be allowed a late bring-up.
1671 Userspace binaries that want to use this feature must
1672 explicitly opt in. The mechanism for the userspace is
1675 Documentation/arm64/memory-tagging-extension.rst.
1679 menu "ARMv8.7 architectural features"
1682 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
1684 depends on ARM64_PAN
1686 Enhanced Privileged Access Never (EPAN) allows Privileged
1687 Access Never to be used with Execute-only mappings.
1689 The feature is detected at runtime, and will remain disabled
1690 if the cpu does not implement the feature.
1694 bool "ARM Scalable Vector Extension support"
1697 The Scalable Vector Extension (SVE) is an extension to the AArch64
1698 execution state which complements and extends the SIMD functionality
1699 of the base architecture to support much larger vectors and to enable
1700 additional vectorisation opportunities.
1702 To enable use of this extension on CPUs that implement it, say Y.
1704 On CPUs that support the SVE2 extensions, this option will enable
1707 Note that for architectural reasons, firmware _must_ implement SVE
1708 support when running on SVE capable hardware. The required support
1711 * version 1.5 and later of the ARM Trusted Firmware
1712 * the AArch64 boot wrapper since commit 5e1261e08abf
1713 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1715 For other firmware implementations, consult the firmware documentation
1718 If you need the kernel to boot on SVE-capable hardware with broken
1719 firmware, you may need to say N here until you get your firmware
1720 fixed. Otherwise, you may experience firmware panics or lockups when
1721 booting the kernel. If unsure and you are not observing these
1722 symptoms, you should assume that it is safe to say Y.
1724 config ARM64_MODULE_PLTS
1725 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1727 select HAVE_MOD_ARCH_SPECIFIC
1729 Allocate PLTs when loading modules so that jumps and calls whose
1730 targets are too far away for their relative offsets to be encoded
1731 in the instructions themselves can be bounced via veneers in the
1732 module's PLT. This allows modules to be allocated in the generic
1733 vmalloc area after the dedicated module memory area has been
1736 When running with address space randomization (KASLR), the module
1737 region itself may be too far away for ordinary relative jumps and
1738 calls, and so in that case, module PLTs are required and cannot be
1741 Specific errata workaround(s) might also force module PLTs to be
1742 enabled (ARM64_ERRATUM_843419).
1744 config ARM64_PSEUDO_NMI
1745 bool "Support for NMI-like interrupts"
1748 Adds support for mimicking Non-Maskable Interrupts through the use of
1749 GIC interrupt priority. This support requires version 3 or later of
1752 This high priority configuration for interrupts needs to be
1753 explicitly enabled by setting the kernel parameter
1754 "irqchip.gicv3_pseudo_nmi" to 1.
1759 config ARM64_DEBUG_PRIORITY_MASKING
1760 bool "Debug interrupt priority masking"
1762 This adds runtime checks to functions enabling/disabling
1763 interrupts when using priority masking. The additional checks verify
1764 the validity of ICC_PMR_EL1 when calling concerned functions.
1770 bool "Build a relocatable kernel image" if EXPERT
1771 select ARCH_HAS_RELR
1774 This builds the kernel as a Position Independent Executable (PIE),
1775 which retains all relocation metadata required to relocate the
1776 kernel binary at runtime to a different virtual address than the
1777 address it was linked at.
1778 Since AArch64 uses the RELA relocation format, this requires a
1779 relocation pass at runtime even if the kernel is loaded at the
1780 same address it was linked at.
1782 config RANDOMIZE_BASE
1783 bool "Randomize the address of the kernel image"
1784 select ARM64_MODULE_PLTS if MODULES
1787 Randomizes the virtual address at which the kernel image is
1788 loaded, as a security feature that deters exploit attempts
1789 relying on knowledge of the location of kernel internals.
1791 It is the bootloader's job to provide entropy, by passing a
1792 random u64 value in /chosen/kaslr-seed at kernel entry.
1794 When booting via the UEFI stub, it will invoke the firmware's
1795 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1796 to the kernel proper. In addition, it will randomise the physical
1797 location of the kernel Image as well.
1801 config RANDOMIZE_MODULE_REGION_FULL
1802 bool "Randomize the module region over a 4 GB range"
1803 depends on RANDOMIZE_BASE
1806 Randomizes the location of the module region inside a 4 GB window
1807 covering the core kernel. This way, it is less likely for modules
1808 to leak information about the location of core kernel data structures
1809 but it does imply that function calls between modules and the core
1810 kernel will need to be resolved via veneers in the module PLT.
1812 When this option is not set, the module region will be randomized over
1813 a limited range that contains the [_stext, _etext] interval of the
1814 core kernel, so branch relocations are always in range.
1816 config CC_HAVE_STACKPROTECTOR_SYSREG
1817 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1819 config STACKPROTECTOR_PER_TASK
1821 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1827 config ARM64_ACPI_PARKING_PROTOCOL
1828 bool "Enable support for the ARM64 ACPI parking protocol"
1831 Enable support for the ARM64 ACPI parking protocol. If disabled
1832 the kernel will not allow booting through the ARM64 ACPI parking
1833 protocol even if the corresponding data is present in the ACPI
1837 string "Default kernel command string"
1840 Provide a set of default command-line options at build time by
1841 entering them here. As a minimum, you should specify the the
1842 root device (e.g. root=/dev/nfs).
1845 prompt "Kernel command line type" if CMDLINE != ""
1846 default CMDLINE_FROM_BOOTLOADER
1848 Choose how the kernel will handle the provided default kernel
1849 command line string.
1851 config CMDLINE_FROM_BOOTLOADER
1852 bool "Use bootloader kernel arguments if available"
1854 Uses the command-line options passed by the boot loader. If
1855 the boot loader doesn't provide any, the default kernel command
1856 string provided in CMDLINE will be used.
1858 config CMDLINE_FORCE
1859 bool "Always use the default kernel command string"
1861 Always use the default kernel command string, even if the boot
1862 loader passes other arguments to the kernel.
1863 This is useful if you cannot or don't want to change the
1864 command-line options your boot loader passes to the kernel.
1872 bool "UEFI runtime support"
1873 depends on OF && !CPU_BIG_ENDIAN
1874 depends on KERNEL_MODE_NEON
1875 select ARCH_SUPPORTS_ACPI
1878 select EFI_PARAMS_FROM_FDT
1879 select EFI_RUNTIME_WRAPPERS
1881 select EFI_GENERIC_STUB
1882 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
1885 This option provides support for runtime services provided
1886 by UEFI firmware (such as non-volatile variables, realtime
1887 clock, and platform reset). A UEFI stub is also provided to
1888 allow the kernel to be booted as an EFI application. This
1889 is only useful on systems that have UEFI firmware.
1892 bool "Enable support for SMBIOS (DMI) tables"
1896 This enables SMBIOS/DMI feature for systems.
1898 This option is only useful on systems that have UEFI firmware.
1899 However, even with this option, the resultant kernel should
1900 continue to boot on existing non-UEFI platforms.
1904 config SYSVIPC_COMPAT
1906 depends on COMPAT && SYSVIPC
1908 menu "Power management options"
1910 source "kernel/power/Kconfig"
1912 config ARCH_HIBERNATION_POSSIBLE
1916 config ARCH_HIBERNATION_HEADER
1918 depends on HIBERNATION
1920 config ARCH_SUSPEND_POSSIBLE
1925 menu "CPU Power Management"
1927 source "drivers/cpuidle/Kconfig"
1929 source "drivers/cpufreq/Kconfig"
1933 source "drivers/firmware/Kconfig"
1935 source "drivers/acpi/Kconfig"
1937 source "arch/arm64/kvm/Kconfig"
1940 source "arch/arm64/crypto/Kconfig"