1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_APMT if ACPI
5 select ACPI_CCA_REQUIRED if ACPI
6 select ACPI_GENERIC_GSI if ACPI
7 select ACPI_GTDT if ACPI
8 select ACPI_IORT if ACPI
9 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
10 select ACPI_MCFG if (ACPI && PCI)
11 select ACPI_SPCR_TABLE if ACPI
12 select ACPI_PPTT if ACPI
13 select ARCH_HAS_DEBUG_WX
14 select ARCH_BINFMT_ELF_EXTRA_PHDRS
15 select ARCH_BINFMT_ELF_STATE
16 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE
17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
18 select ARCH_ENABLE_MEMORY_HOTPLUG
19 select ARCH_ENABLE_MEMORY_HOTREMOVE
20 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
21 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
22 select ARCH_HAS_CACHE_LINE_SIZE
23 select ARCH_HAS_CURRENT_STACK_POINTER
24 select ARCH_HAS_DEBUG_VIRTUAL
25 select ARCH_HAS_DEBUG_VM_PGTABLE
26 select ARCH_HAS_DMA_PREP_COHERENT
27 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
28 select ARCH_HAS_FAST_MULTIPLIER
29 select ARCH_HAS_FORTIFY_SOURCE
30 select ARCH_HAS_GCOV_PROFILE_ALL
31 select ARCH_HAS_GIGANTIC_PAGE
33 select ARCH_HAS_KEEPINITRD
34 select ARCH_HAS_MEMBARRIER_SYNC_CORE
35 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS
36 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
37 select ARCH_HAS_PTE_DEVMAP
38 select ARCH_HAS_PTE_SPECIAL
39 select ARCH_HAS_SETUP_DMA_OPS
40 select ARCH_HAS_SET_DIRECT_MAP
41 select ARCH_HAS_SET_MEMORY
43 select ARCH_HAS_STRICT_KERNEL_RWX
44 select ARCH_HAS_STRICT_MODULE_RWX
45 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
46 select ARCH_HAS_SYNC_DMA_FOR_CPU
47 select ARCH_HAS_SYSCALL_WRAPPER
48 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
49 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
50 select ARCH_HAS_ZONE_DMA_SET if EXPERT
51 select ARCH_HAVE_ELF_PROT
52 select ARCH_HAVE_NMI_SAFE_CMPXCHG
53 select ARCH_HAVE_TRACE_MMIO_ACCESS
54 select ARCH_INLINE_READ_LOCK if !PREEMPTION
55 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
56 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
57 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
58 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
59 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
60 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
61 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
62 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
63 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
64 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
65 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
66 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
67 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
68 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
69 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
70 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
71 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
72 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
73 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
74 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
75 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
76 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
77 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
78 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
79 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
80 select ARCH_KEEP_MEMBLOCK
81 select ARCH_USE_CMPXCHG_LOCKREF
82 select ARCH_USE_GNU_PROPERTY
83 select ARCH_USE_MEMTEST
84 select ARCH_USE_QUEUED_RWLOCKS
85 select ARCH_USE_QUEUED_SPINLOCKS
86 select ARCH_USE_SYM_ANNOTATIONS
87 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
88 select ARCH_SUPPORTS_HUGETLBFS
89 select ARCH_SUPPORTS_MEMORY_FAILURE
90 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
91 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
92 select ARCH_SUPPORTS_LTO_CLANG_THIN
93 select ARCH_SUPPORTS_CFI_CLANG
94 select ARCH_SUPPORTS_ATOMIC_RMW
95 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
96 select ARCH_SUPPORTS_NUMA_BALANCING
97 select ARCH_SUPPORTS_PAGE_TABLE_CHECK
98 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
99 select ARCH_WANT_DEFAULT_BPF_JIT
100 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
101 select ARCH_WANT_FRAME_POINTERS
102 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
103 select ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP
104 select ARCH_WANT_LD_ORPHAN_WARN
105 select ARCH_WANTS_NO_INSTR
106 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES
107 select ARCH_HAS_UBSAN_SANITIZE_ALL
109 select ARM_ARCH_TIMER
111 select AUDIT_ARCH_COMPAT_GENERIC
112 select ARM_GIC_V2M if PCI
114 select ARM_GIC_V3_ITS if PCI
116 select BUILDTIME_TABLE_SORT
117 select CLONE_BACKWARDS
119 select CPU_PM if (SUSPEND || CPU_IDLE)
121 select DCACHE_WORD_ACCESS
122 select DYNAMIC_FTRACE if FUNCTION_TRACER
123 select DMA_DIRECT_REMAP
126 select GENERIC_ALLOCATOR
127 select GENERIC_ARCH_TOPOLOGY
128 select GENERIC_CLOCKEVENTS_BROADCAST
129 select GENERIC_CPU_AUTOPROBE
130 select GENERIC_CPU_VULNERABILITIES
131 select GENERIC_EARLY_IOREMAP
132 select GENERIC_IDLE_POLL_SETUP
133 select GENERIC_IOREMAP
134 select GENERIC_IRQ_IPI
135 select GENERIC_IRQ_PROBE
136 select GENERIC_IRQ_SHOW
137 select GENERIC_IRQ_SHOW_LEVEL
138 select GENERIC_LIB_DEVMEM_IS_ALLOWED
139 select GENERIC_PCI_IOMAP
140 select GENERIC_PTDUMP
141 select GENERIC_SCHED_CLOCK
142 select GENERIC_SMP_IDLE_THREAD
143 select GENERIC_TIME_VSYSCALL
144 select GENERIC_GETTIMEOFDAY
145 select GENERIC_VDSO_TIME_NS
146 select HARDIRQS_SW_RESEND
150 select HAVE_ACPI_APEI if (ACPI && EFI)
151 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
152 select HAVE_ARCH_AUDITSYSCALL
153 select HAVE_ARCH_BITREVERSE
154 select HAVE_ARCH_COMPILER_H
155 select HAVE_ARCH_HUGE_VMALLOC
156 select HAVE_ARCH_HUGE_VMAP
157 select HAVE_ARCH_JUMP_LABEL
158 select HAVE_ARCH_JUMP_LABEL_RELATIVE
159 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
160 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
161 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
162 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
163 # Some instrumentation may be unsound, hence EXPERT
164 select HAVE_ARCH_KCSAN if EXPERT
165 select HAVE_ARCH_KFENCE
166 select HAVE_ARCH_KGDB
167 select HAVE_ARCH_MMAP_RND_BITS
168 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
169 select HAVE_ARCH_PREL32_RELOCATIONS
170 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
171 select HAVE_ARCH_SECCOMP_FILTER
172 select HAVE_ARCH_STACKLEAK
173 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
174 select HAVE_ARCH_TRACEHOOK
175 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
176 select HAVE_ARCH_VMAP_STACK
177 select HAVE_ARM_SMCCC
178 select HAVE_ASM_MODVERSIONS
180 select HAVE_C_RECORDMCOUNT
181 select HAVE_CMPXCHG_DOUBLE
182 select HAVE_CMPXCHG_LOCAL
183 select HAVE_CONTEXT_TRACKING_USER
184 select HAVE_DEBUG_KMEMLEAK
185 select HAVE_DMA_CONTIGUOUS
186 select HAVE_DYNAMIC_FTRACE
187 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \
188 if $(cc-option,-fpatchable-function-entry=2)
189 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
190 if DYNAMIC_FTRACE_WITH_ARGS
191 select HAVE_EFFICIENT_UNALIGNED_ACCESS
193 select HAVE_FTRACE_MCOUNT_RECORD
194 select HAVE_FUNCTION_TRACER
195 select HAVE_FUNCTION_ERROR_INJECTION
196 select HAVE_FUNCTION_GRAPH_TRACER
197 select HAVE_GCC_PLUGINS
198 select HAVE_HW_BREAKPOINT if PERF_EVENTS
199 select HAVE_IOREMAP_PROT
200 select HAVE_IRQ_TIME_ACCOUNTING
203 select HAVE_PERF_EVENTS
204 select HAVE_PERF_REGS
205 select HAVE_PERF_USER_STACK_DUMP
206 select HAVE_PREEMPT_DYNAMIC_KEY
207 select HAVE_REGS_AND_STACK_ACCESS_API
208 select HAVE_POSIX_CPU_TIMERS_TASK_WORK
209 select HAVE_FUNCTION_ARG_ACCESS_API
210 select MMU_GATHER_RCU_TABLE_FREE
212 select HAVE_STACKPROTECTOR
213 select HAVE_SYSCALL_TRACEPOINTS
215 select HAVE_KRETPROBES
216 select HAVE_GENERIC_VDSO
218 select IRQ_FORCED_THREADING
219 select KASAN_VMALLOC if KASAN
220 select MODULES_USE_ELF_RELA
221 select NEED_DMA_MAP_STATE
222 select NEED_SG_DMA_LENGTH
224 select OF_EARLY_FLATTREE
225 select PCI_DOMAINS_GENERIC if PCI
226 select PCI_ECAM if (ACPI && PCI)
227 select PCI_SYSCALL if PCI
232 select SYSCTL_EXCEPTION_TRACE
233 select THREAD_INFO_IN_TASK
234 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
235 select TRACE_IRQFLAGS_SUPPORT
236 select TRACE_IRQFLAGS_NMI_SUPPORT
237 select HAVE_SOFTIRQ_ON_OWN_STACK
239 ARM 64-bit (AArch64) Linux support.
241 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
243 # https://github.com/ClangBuiltLinux/linux/issues/1507
244 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600))
245 select HAVE_DYNAMIC_FTRACE_WITH_ARGS
247 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
249 depends on $(cc-option,-fpatchable-function-entry=2)
250 select HAVE_DYNAMIC_FTRACE_WITH_ARGS
258 config ARM64_PAGE_SHIFT
260 default 16 if ARM64_64K_PAGES
261 default 14 if ARM64_16K_PAGES
264 config ARM64_CONT_PTE_SHIFT
266 default 5 if ARM64_64K_PAGES
267 default 7 if ARM64_16K_PAGES
270 config ARM64_CONT_PMD_SHIFT
272 default 5 if ARM64_64K_PAGES
273 default 5 if ARM64_16K_PAGES
276 config ARCH_MMAP_RND_BITS_MIN
277 default 14 if ARM64_64K_PAGES
278 default 16 if ARM64_16K_PAGES
281 # max bits determined by the following formula:
282 # VA_BITS - PAGE_SHIFT - 3
283 config ARCH_MMAP_RND_BITS_MAX
284 default 19 if ARM64_VA_BITS=36
285 default 24 if ARM64_VA_BITS=39
286 default 27 if ARM64_VA_BITS=42
287 default 30 if ARM64_VA_BITS=47
288 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
289 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
290 default 33 if ARM64_VA_BITS=48
291 default 14 if ARM64_64K_PAGES
292 default 16 if ARM64_16K_PAGES
295 config ARCH_MMAP_RND_COMPAT_BITS_MIN
296 default 7 if ARM64_64K_PAGES
297 default 9 if ARM64_16K_PAGES
300 config ARCH_MMAP_RND_COMPAT_BITS_MAX
306 config STACKTRACE_SUPPORT
309 config ILLEGAL_POINTER_VALUE
311 default 0xdead000000000000
313 config LOCKDEP_SUPPORT
320 config GENERIC_BUG_RELATIVE_POINTERS
322 depends on GENERIC_BUG
324 config GENERIC_HWEIGHT
330 config GENERIC_CALIBRATE_DELAY
333 config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
339 config KERNEL_MODE_NEON
342 config FIX_EARLYCON_MEM
345 config PGTABLE_LEVELS
347 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
348 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
349 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
350 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
351 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
352 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
354 config ARCH_SUPPORTS_UPROBES
357 config ARCH_PROC_KCORE_TEXT
360 config BROKEN_GAS_INST
361 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
363 config KASAN_SHADOW_OFFSET
365 depends on KASAN_GENERIC || KASAN_SW_TAGS
366 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
367 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
368 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
369 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
370 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
371 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
372 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
373 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
374 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
375 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
376 default 0xffffffffffffffff
381 source "arch/arm64/Kconfig.platforms"
383 menu "Kernel Features"
385 menu "ARM errata workarounds via the alternatives framework"
387 config ARM64_WORKAROUND_CLEAN_CACHE
390 config ARM64_ERRATUM_826319
391 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
393 select ARM64_WORKAROUND_CLEAN_CACHE
395 This option adds an alternative code sequence to work around ARM
396 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
397 AXI master interface and an L2 cache.
399 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
400 and is unable to accept a certain write via this interface, it will
401 not progress on read data presented on the read data channel and the
404 The workaround promotes data cache clean instructions to
405 data cache clean-and-invalidate.
406 Please note that this does not necessarily enable the workaround,
407 as it depends on the alternative framework, which will only patch
408 the kernel if an affected CPU is detected.
412 config ARM64_ERRATUM_827319
413 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
415 select ARM64_WORKAROUND_CLEAN_CACHE
417 This option adds an alternative code sequence to work around ARM
418 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
419 master interface and an L2 cache.
421 Under certain conditions this erratum can cause a clean line eviction
422 to occur at the same time as another transaction to the same address
423 on the AMBA 5 CHI interface, which can cause data corruption if the
424 interconnect reorders the two transactions.
426 The workaround promotes data cache clean instructions to
427 data cache clean-and-invalidate.
428 Please note that this does not necessarily enable the workaround,
429 as it depends on the alternative framework, which will only patch
430 the kernel if an affected CPU is detected.
434 config ARM64_ERRATUM_824069
435 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
437 select ARM64_WORKAROUND_CLEAN_CACHE
439 This option adds an alternative code sequence to work around ARM
440 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
441 to a coherent interconnect.
443 If a Cortex-A53 processor is executing a store or prefetch for
444 write instruction at the same time as a processor in another
445 cluster is executing a cache maintenance operation to the same
446 address, then this erratum might cause a clean cache line to be
447 incorrectly marked as dirty.
449 The workaround promotes data cache clean instructions to
450 data cache clean-and-invalidate.
451 Please note that this option does not necessarily enable the
452 workaround, as it depends on the alternative framework, which will
453 only patch the kernel if an affected CPU is detected.
457 config ARM64_ERRATUM_819472
458 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
460 select ARM64_WORKAROUND_CLEAN_CACHE
462 This option adds an alternative code sequence to work around ARM
463 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
464 present when it is connected to a coherent interconnect.
466 If the processor is executing a load and store exclusive sequence at
467 the same time as a processor in another cluster is executing a cache
468 maintenance operation to the same address, then this erratum might
469 cause data corruption.
471 The workaround promotes data cache clean instructions to
472 data cache clean-and-invalidate.
473 Please note that this does not necessarily enable the workaround,
474 as it depends on the alternative framework, which will only patch
475 the kernel if an affected CPU is detected.
479 config ARM64_ERRATUM_832075
480 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
483 This option adds an alternative code sequence to work around ARM
484 erratum 832075 on Cortex-A57 parts up to r1p2.
486 Affected Cortex-A57 parts might deadlock when exclusive load/store
487 instructions to Write-Back memory are mixed with Device loads.
489 The workaround is to promote device loads to use Load-Acquire
491 Please note that this does not necessarily enable the workaround,
492 as it depends on the alternative framework, which will only patch
493 the kernel if an affected CPU is detected.
497 config ARM64_ERRATUM_834220
498 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
502 This option adds an alternative code sequence to work around ARM
503 erratum 834220 on Cortex-A57 parts up to r1p2.
505 Affected Cortex-A57 parts might report a Stage 2 translation
506 fault as the result of a Stage 1 fault for load crossing a
507 page boundary when there is a permission or device memory
508 alignment fault at Stage 1 and a translation fault at Stage 2.
510 The workaround is to verify that the Stage 1 translation
511 doesn't generate a fault before handling the Stage 2 fault.
512 Please note that this does not necessarily enable the workaround,
513 as it depends on the alternative framework, which will only patch
514 the kernel if an affected CPU is detected.
518 config ARM64_ERRATUM_1742098
519 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence"
523 This option removes the AES hwcap for aarch32 user-space to
524 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
526 Affected parts may corrupt the AES state if an interrupt is
527 taken between a pair of AES instructions. These instructions
528 are only present if the cryptography extensions are present.
529 All software should have a fallback implementation for CPUs
530 that don't implement the cryptography extensions.
534 config ARM64_ERRATUM_845719
535 bool "Cortex-A53: 845719: a load might read incorrect data"
539 This option adds an alternative code sequence to work around ARM
540 erratum 845719 on Cortex-A53 parts up to r0p4.
542 When running a compat (AArch32) userspace on an affected Cortex-A53
543 part, a load at EL0 from a virtual address that matches the bottom 32
544 bits of the virtual address used by a recent load at (AArch64) EL1
545 might return incorrect data.
547 The workaround is to write the contextidr_el1 register on exception
548 return to a 32-bit task.
549 Please note that this does not necessarily enable the workaround,
550 as it depends on the alternative framework, which will only patch
551 the kernel if an affected CPU is detected.
555 config ARM64_ERRATUM_843419
556 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
558 select ARM64_MODULE_PLTS if MODULES
560 This option links the kernel with '--fix-cortex-a53-843419' and
561 enables PLT support to replace certain ADRP instructions, which can
562 cause subsequent memory accesses to use an incorrect address on
563 Cortex-A53 parts up to r0p4.
567 config ARM64_LD_HAS_FIX_ERRATUM_843419
568 def_bool $(ld-option,--fix-cortex-a53-843419)
570 config ARM64_ERRATUM_1024718
571 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
574 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
576 Affected Cortex-A55 cores (all revisions) could cause incorrect
577 update of the hardware dirty bit when the DBM/AP bits are updated
578 without a break-before-make. The workaround is to disable the usage
579 of hardware DBM locally on the affected cores. CPUs not affected by
580 this erratum will continue to use the feature.
584 config ARM64_ERRATUM_1418040
585 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
589 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
590 errata 1188873 and 1418040.
592 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
593 cause register corruption when accessing the timer registers
594 from AArch32 userspace.
598 config ARM64_WORKAROUND_SPECULATIVE_AT
601 config ARM64_ERRATUM_1165522
602 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
604 select ARM64_WORKAROUND_SPECULATIVE_AT
606 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
608 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
609 corrupted TLBs by speculating an AT instruction during a guest
614 config ARM64_ERRATUM_1319367
615 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
617 select ARM64_WORKAROUND_SPECULATIVE_AT
619 This option adds work arounds for ARM Cortex-A57 erratum 1319537
620 and A72 erratum 1319367
622 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
623 speculating an AT instruction during a guest context switch.
627 config ARM64_ERRATUM_1530923
628 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
630 select ARM64_WORKAROUND_SPECULATIVE_AT
632 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
634 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
635 corrupted TLBs by speculating an AT instruction during a guest
640 config ARM64_WORKAROUND_REPEAT_TLBI
643 config ARM64_ERRATUM_2441007
644 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
646 select ARM64_WORKAROUND_REPEAT_TLBI
648 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
650 Under very rare circumstances, affected Cortex-A55 CPUs
651 may not handle a race between a break-before-make sequence on one
652 CPU, and another CPU accessing the same page. This could allow a
653 store to a page that has been unmapped.
655 Work around this by adding the affected CPUs to the list that needs
656 TLB sequences to be done twice.
660 config ARM64_ERRATUM_1286807
661 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
663 select ARM64_WORKAROUND_REPEAT_TLBI
665 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
667 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
668 address for a cacheable mapping of a location is being
669 accessed by a core while another core is remapping the virtual
670 address to a new physical page using the recommended
671 break-before-make sequence, then under very rare circumstances
672 TLBI+DSB completes before a read using the translation being
673 invalidated has been observed by other observers. The
674 workaround repeats the TLBI+DSB operation.
676 config ARM64_ERRATUM_1463225
677 bool "Cortex-A76: Software Step might prevent interrupt recognition"
680 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
682 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
683 of a system call instruction (SVC) can prevent recognition of
684 subsequent interrupts when software stepping is disabled in the
685 exception handler of the system call and either kernel debugging
686 is enabled or VHE is in use.
688 Work around the erratum by triggering a dummy step exception
689 when handling a system call from a task that is being stepped
690 in a VHE configuration of the kernel.
694 config ARM64_ERRATUM_1542419
695 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
698 This option adds a workaround for ARM Neoverse-N1 erratum
701 Affected Neoverse-N1 cores could execute a stale instruction when
702 modified by another CPU. The workaround depends on a firmware
705 Workaround the issue by hiding the DIC feature from EL0. This
706 forces user-space to perform cache maintenance.
710 config ARM64_ERRATUM_1508412
711 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
714 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
716 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
717 of a store-exclusive or read of PAR_EL1 and a load with device or
718 non-cacheable memory attributes. The workaround depends on a firmware
721 KVM guests must also have the workaround implemented or they can
724 Work around the issue by inserting DMB SY barriers around PAR_EL1
725 register reads and warning KVM users. The DMB barrier is sufficient
726 to prevent a speculative PAR_EL1 read.
730 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
733 config ARM64_ERRATUM_2051678
734 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
737 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
738 Affected Cortex-A510 might not respect the ordering rules for
739 hardware update of the page table's dirty bit. The workaround
740 is to not enable the feature on affected CPUs.
744 config ARM64_ERRATUM_2077057
745 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
748 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
749 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
750 expected, but a Pointer Authentication trap is taken instead. The
751 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow
752 EL1 to cause a return to EL2 with a guest controlled ELR_EL2.
754 This can only happen when EL2 is stepping EL1.
756 When these conditions occur, the SPSR_EL2 value is unchanged from the
757 previous guest entry, and can be restored from the in-memory copy.
761 config ARM64_ERRATUM_2658417
762 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
765 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
766 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
767 BFMMLA or VMMLA instructions in rare circumstances when a pair of
768 A510 CPUs are using shared neon hardware. As the sharing is not
769 discoverable by the kernel, hide the BF16 HWCAP to indicate that
770 user-space should not be using these instructions.
774 config ARM64_ERRATUM_2119858
775 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
777 depends on CORESIGHT_TRBE
778 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
780 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
782 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
783 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
784 the event of a WRAP event.
786 Work around the issue by always making sure we move the TRBPTR_EL1 by
787 256 bytes before enabling the buffer and filling the first 256 bytes of
788 the buffer with ETM ignore packets upon disabling.
792 config ARM64_ERRATUM_2139208
793 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
795 depends on CORESIGHT_TRBE
796 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
798 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
800 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
801 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
802 the event of a WRAP event.
804 Work around the issue by always making sure we move the TRBPTR_EL1 by
805 256 bytes before enabling the buffer and filling the first 256 bytes of
806 the buffer with ETM ignore packets upon disabling.
810 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
813 config ARM64_ERRATUM_2054223
814 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
816 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
818 Enable workaround for ARM Cortex-A710 erratum 2054223
820 Affected cores may fail to flush the trace data on a TSB instruction, when
821 the PE is in trace prohibited state. This will cause losing a few bytes
824 Workaround is to issue two TSB consecutively on affected cores.
828 config ARM64_ERRATUM_2067961
829 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
831 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
833 Enable workaround for ARM Neoverse-N2 erratum 2067961
835 Affected cores may fail to flush the trace data on a TSB instruction, when
836 the PE is in trace prohibited state. This will cause losing a few bytes
839 Workaround is to issue two TSB consecutively on affected cores.
843 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
846 config ARM64_ERRATUM_2253138
847 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
848 depends on CORESIGHT_TRBE
850 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
852 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
854 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
855 for TRBE. Under some conditions, the TRBE might generate a write to the next
856 virtually addressed page following the last page of the TRBE address space
857 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
859 Work around this in the driver by always making sure that there is a
860 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
864 config ARM64_ERRATUM_2224489
865 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
866 depends on CORESIGHT_TRBE
868 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
870 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
872 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
873 for TRBE. Under some conditions, the TRBE might generate a write to the next
874 virtually addressed page following the last page of the TRBE address space
875 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
877 Work around this in the driver by always making sure that there is a
878 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
882 config ARM64_ERRATUM_2441009
883 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
885 select ARM64_WORKAROUND_REPEAT_TLBI
887 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
889 Under very rare circumstances, affected Cortex-A510 CPUs
890 may not handle a race between a break-before-make sequence on one
891 CPU, and another CPU accessing the same page. This could allow a
892 store to a page that has been unmapped.
894 Work around this by adding the affected CPUs to the list that needs
895 TLB sequences to be done twice.
899 config ARM64_ERRATUM_2064142
900 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
901 depends on CORESIGHT_TRBE
904 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
906 Affected Cortex-A510 core might fail to write into system registers after the
907 TRBE has been disabled. Under some conditions after the TRBE has been disabled
908 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,
909 and TRBTRG_EL1 will be ignored and will not be effected.
911 Work around this in the driver by executing TSB CSYNC and DSB after collection
912 is stopped and before performing a system register write to one of the affected
917 config ARM64_ERRATUM_2038923
918 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
919 depends on CORESIGHT_TRBE
922 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
924 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
925 prohibited within the CPU. As a result, the trace buffer or trace buffer state
926 might be corrupted. This happens after TRBE buffer has been enabled by setting
927 TRBLIMITR_EL1.E, followed by just a single context synchronization event before
928 execution changes from a context, in which trace is prohibited to one where it
929 isn't, or vice versa. In these mentioned conditions, the view of whether trace
930 is prohibited is inconsistent between parts of the CPU, and the trace buffer or
931 the trace buffer state might be corrupted.
933 Work around this in the driver by preventing an inconsistent view of whether the
934 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
935 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
936 two ISB instructions if no ERET is to take place.
940 config ARM64_ERRATUM_1902691
941 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
942 depends on CORESIGHT_TRBE
945 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
947 Affected Cortex-A510 core might cause trace data corruption, when being written
948 into the memory. Effectively TRBE is broken and hence cannot be used to capture
951 Work around this problem in the driver by just preventing TRBE initialization on
952 affected cpus. The firmware must have disabled the access to TRBE for the kernel
953 on such implementations. This will cover the kernel for any firmware that doesn't
958 config ARM64_ERRATUM_2457168
959 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
960 depends on ARM64_AMU_EXTN
963 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
965 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate
966 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
967 incorrectly giving a significantly higher output value.
969 Work around this problem by returning 0 when reading the affected counter in
970 key locations that results in disabling all users of this counter. This effect
971 is the same to firmware disabling affected counters.
975 config CAVIUM_ERRATUM_22375
976 bool "Cavium erratum 22375, 24313"
979 Enable workaround for errata 22375 and 24313.
981 This implements two gicv3-its errata workarounds for ThunderX. Both
982 with a small impact affecting only ITS table allocation.
984 erratum 22375: only alloc 8MB table size
985 erratum 24313: ignore memory access type
987 The fixes are in ITS initialization and basically ignore memory access
988 type and table size provided by the TYPER and BASER registers.
992 config CAVIUM_ERRATUM_23144
993 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
997 ITS SYNC command hang for cross node io and collections/cpu mapping.
1001 config CAVIUM_ERRATUM_23154
1002 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"
1005 The ThunderX GICv3 implementation requires a modified version for
1006 reading the IAR status to ensure data synchronization
1007 (access to icc_iar1_el1 is not sync'ed before and after).
1009 It also suffers from erratum 38545 (also present on Marvell's
1010 OcteonTX and OcteonTX2), resulting in deactivated interrupts being
1011 spuriously presented to the CPU interface.
1015 config CAVIUM_ERRATUM_27456
1016 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
1019 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
1020 instructions may cause the icache to become corrupted if it
1021 contains data for a non-current ASID. The fix is to
1022 invalidate the icache when changing the mm context.
1026 config CAVIUM_ERRATUM_30115
1027 bool "Cavium erratum 30115: Guest may disable interrupts in host"
1030 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
1031 1.2, and T83 Pass 1.0, KVM guest execution may disable
1032 interrupts in host. Trapping both GICv3 group-0 and group-1
1033 accesses sidesteps the issue.
1037 config CAVIUM_TX2_ERRATUM_219
1038 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
1041 On Cavium ThunderX2, a load, store or prefetch instruction between a
1042 TTBR update and the corresponding context synchronizing operation can
1043 cause a spurious Data Abort to be delivered to any hardware thread in
1046 Work around the issue by avoiding the problematic code sequence and
1047 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
1048 trap handler performs the corresponding register access, skips the
1049 instruction and ensures context synchronization by virtue of the
1054 config FUJITSU_ERRATUM_010001
1055 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1058 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1059 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1060 accesses may cause undefined fault (Data abort, DFSC=0b111111).
1061 This fault occurs under a specific hardware condition when a
1062 load/store instruction performs an address translation using:
1063 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1064 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1065 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1066 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1068 The workaround is to ensure these bits are clear in TCR_ELx.
1069 The workaround only affects the Fujitsu-A64FX.
1073 config HISILICON_ERRATUM_161600802
1074 bool "Hip07 161600802: Erroneous redistributor VLPI base"
1077 The HiSilicon Hip07 SoC uses the wrong redistributor base
1078 when issued ITS commands such as VMOVP and VMAPP, and requires
1079 a 128kB offset to be applied to the target address in this commands.
1083 config QCOM_FALKOR_ERRATUM_1003
1084 bool "Falkor E1003: Incorrect translation due to ASID change"
1087 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
1088 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
1089 in TTBR1_EL1, this situation only occurs in the entry trampoline and
1090 then only for entries in the walk cache, since the leaf translation
1091 is unchanged. Work around the erratum by invalidating the walk cache
1092 entries for the trampoline before entering the kernel proper.
1094 config QCOM_FALKOR_ERRATUM_1009
1095 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
1097 select ARM64_WORKAROUND_REPEAT_TLBI
1099 On Falkor v1, the CPU may prematurely complete a DSB following a
1100 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
1101 one more time to fix the issue.
1105 config QCOM_QDF2400_ERRATUM_0065
1106 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
1109 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
1110 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
1111 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
1115 config QCOM_FALKOR_ERRATUM_E1041
1116 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
1119 Falkor CPU may speculatively fetch instructions from an improper
1120 memory location when MMU translation is changed from SCTLR_ELn[M]=1
1121 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
1125 config NVIDIA_CARMEL_CNP_ERRATUM
1126 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
1129 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1130 invalidate shared TLB entries installed by a different core, as it would
1131 on standard ARM cores.
1135 config SOCIONEXT_SYNQUACER_PREITS
1136 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1139 Socionext Synquacer SoCs implement a separate h/w block to generate
1140 MSI doorbell writes with non-zero values for the device ID.
1144 endmenu # "ARM errata workarounds via the alternatives framework"
1148 default ARM64_4K_PAGES
1150 Page size (translation granule) configuration.
1152 config ARM64_4K_PAGES
1155 This feature enables 4KB pages support.
1157 config ARM64_16K_PAGES
1160 The system will use 16KB pages support. AArch32 emulation
1161 requires applications compiled with 16K (or a multiple of 16K)
1164 config ARM64_64K_PAGES
1167 This feature enables 64KB pages support (4KB by default)
1168 allowing only two levels of page tables and faster TLB
1169 look-up. AArch32 emulation requires applications compiled
1170 with 64K aligned segments.
1175 prompt "Virtual address space size"
1176 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
1177 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
1178 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
1180 Allows choosing one of multiple possible virtual address
1181 space sizes. The level of translation table is determined by
1182 a combination of page size and virtual address space size.
1184 config ARM64_VA_BITS_36
1185 bool "36-bit" if EXPERT
1186 depends on ARM64_16K_PAGES
1188 config ARM64_VA_BITS_39
1190 depends on ARM64_4K_PAGES
1192 config ARM64_VA_BITS_42
1194 depends on ARM64_64K_PAGES
1196 config ARM64_VA_BITS_47
1198 depends on ARM64_16K_PAGES
1200 config ARM64_VA_BITS_48
1203 config ARM64_VA_BITS_52
1205 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
1207 Enable 52-bit virtual addressing for userspace when explicitly
1208 requested via a hint to mmap(). The kernel will also use 52-bit
1209 virtual addresses for its own mappings (provided HW support for
1210 this feature is available, otherwise it reverts to 48-bit).
1212 NOTE: Enabling 52-bit virtual addressing in conjunction with
1213 ARMv8.3 Pointer Authentication will result in the PAC being
1214 reduced from 7 bits to 3 bits, which may have a significant
1215 impact on its susceptibility to brute-force attacks.
1217 If unsure, select 48-bit virtual addressing instead.
1221 config ARM64_FORCE_52BIT
1222 bool "Force 52-bit virtual addresses for userspace"
1223 depends on ARM64_VA_BITS_52 && EXPERT
1225 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1226 to maintain compatibility with older software by providing 48-bit VAs
1227 unless a hint is supplied to mmap.
1229 This configuration option disables the 48-bit compatibility logic, and
1230 forces all userspace addresses to be 52-bit on HW that supports it. One
1231 should only enable this configuration option for stress testing userspace
1232 memory management code. If unsure say N here.
1234 config ARM64_VA_BITS
1236 default 36 if ARM64_VA_BITS_36
1237 default 39 if ARM64_VA_BITS_39
1238 default 42 if ARM64_VA_BITS_42
1239 default 47 if ARM64_VA_BITS_47
1240 default 48 if ARM64_VA_BITS_48
1241 default 52 if ARM64_VA_BITS_52
1244 prompt "Physical address space size"
1245 default ARM64_PA_BITS_48
1247 Choose the maximum physical address range that the kernel will
1250 config ARM64_PA_BITS_48
1253 config ARM64_PA_BITS_52
1254 bool "52-bit (ARMv8.2)"
1255 depends on ARM64_64K_PAGES
1256 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1258 Enable support for a 52-bit physical address space, introduced as
1259 part of the ARMv8.2-LPA extension.
1261 With this enabled, the kernel will also continue to work on CPUs that
1262 do not support ARMv8.2-LPA, but with some added memory overhead (and
1263 minor performance overhead).
1267 config ARM64_PA_BITS
1269 default 48 if ARM64_PA_BITS_48
1270 default 52 if ARM64_PA_BITS_52
1274 default CPU_LITTLE_ENDIAN
1276 Select the endianness of data accesses performed by the CPU. Userspace
1277 applications will need to be compiled and linked for the endianness
1278 that is selected here.
1280 config CPU_BIG_ENDIAN
1281 bool "Build big-endian kernel"
1282 depends on !LD_IS_LLD || LLD_VERSION >= 130000
1284 Say Y if you plan on running a kernel with a big-endian userspace.
1286 config CPU_LITTLE_ENDIAN
1287 bool "Build little-endian kernel"
1289 Say Y if you plan on running a kernel with a little-endian userspace.
1290 This is usually the case for distributions targeting arm64.
1295 bool "Multi-core scheduler support"
1297 Multi-core scheduler support improves the CPU scheduler's decision
1298 making when dealing with multi-core CPU chips at a cost of slightly
1299 increased overhead in some places. If unsure say N here.
1301 config SCHED_CLUSTER
1302 bool "Cluster scheduler support"
1304 Cluster scheduler support improves the CPU scheduler's decision
1305 making when dealing with machines that have clusters of CPUs.
1306 Cluster usually means a couple of CPUs which are placed closely
1307 by sharing mid-level caches, last-level cache tags or internal
1311 bool "SMT scheduler support"
1313 Improves the CPU scheduler's decision making when dealing with
1314 MultiThreading at a cost of slightly increased overhead in some
1315 places. If unsure say N here.
1318 int "Maximum number of CPUs (2-4096)"
1323 bool "Support for hot-pluggable CPUs"
1324 select GENERIC_IRQ_MIGRATION
1326 Say Y here to experiment with turning CPUs off and on. CPUs
1327 can be controlled through /sys/devices/system/cpu.
1329 # Common NUMA Features
1331 bool "NUMA Memory Allocation and Scheduler Support"
1332 select GENERIC_ARCH_NUMA
1333 select ACPI_NUMA if ACPI
1335 select HAVE_SETUP_PER_CPU_AREA
1336 select NEED_PER_CPU_EMBED_FIRST_CHUNK
1337 select NEED_PER_CPU_PAGE_FIRST_CHUNK
1338 select USE_PERCPU_NUMA_NODE_ID
1340 Enable NUMA (Non-Uniform Memory Access) support.
1342 The kernel will try to allocate memory used by a CPU on the
1343 local memory of the CPU and add some more
1344 NUMA awareness to the kernel.
1347 int "Maximum NUMA Nodes (as a power of 2)"
1352 Specify the maximum number of NUMA Nodes available on the target
1353 system. Increases memory reserved to accommodate various tables.
1355 source "kernel/Kconfig.hz"
1357 config ARCH_SPARSEMEM_ENABLE
1359 select SPARSEMEM_VMEMMAP_ENABLE
1360 select SPARSEMEM_VMEMMAP
1362 config HW_PERF_EVENTS
1366 # Supported by clang >= 7.0 or GCC >= 12.0.0
1367 config CC_HAVE_SHADOW_CALL_STACK
1368 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1371 bool "Enable paravirtualization code"
1373 This changes the kernel so it can modify itself when it is run
1374 under a hypervisor, potentially improving performance significantly
1375 over full virtualization.
1377 config PARAVIRT_TIME_ACCOUNTING
1378 bool "Paravirtual steal time accounting"
1381 Select this option to enable fine granularity task steal time
1382 accounting. Time spent executing other tasks in parallel with
1383 the current vCPU is discounted from the vCPU power. To account for
1384 that, there can be a small performance impact.
1386 If in doubt, say N here.
1389 depends on PM_SLEEP_SMP
1391 bool "kexec system call"
1393 kexec is a system call that implements the ability to shutdown your
1394 current kernel, and to start another kernel. It is like a reboot
1395 but it is independent of the system firmware. And like a reboot
1396 you can start any kernel with it, not just Linux.
1399 bool "kexec file based system call"
1401 select HAVE_IMA_KEXEC if IMA
1403 This is new version of kexec system call. This system call is
1404 file based and takes file descriptors as system call argument
1405 for kernel and initramfs as opposed to list of segments as
1406 accepted by previous system call.
1409 bool "Verify kernel signature during kexec_file_load() syscall"
1410 depends on KEXEC_FILE
1412 Select this option to verify a signature with loaded kernel
1413 image. If configured, any attempt of loading a image without
1414 valid signature will fail.
1416 In addition to that option, you need to enable signature
1417 verification for the corresponding kernel image type being
1418 loaded in order for this to work.
1420 config KEXEC_IMAGE_VERIFY_SIG
1421 bool "Enable Image signature verification support"
1423 depends on KEXEC_SIG
1424 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1426 Enable Image signature verification support.
1428 comment "Support for PE file signature verification disabled"
1429 depends on KEXEC_SIG
1430 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1433 bool "Build kdump crash kernel"
1435 Generate crash dump after being started by kexec. This should
1436 be normally only set in special crash dump kernels which are
1437 loaded in the main kernel with kexec-tools into a specially
1438 reserved region and then later executed after a crash by
1441 For more details see Documentation/admin-guide/kdump/kdump.rst
1445 depends on HIBERNATION || KEXEC_CORE
1452 bool "Xen guest support on ARM64"
1453 depends on ARM64 && OF
1457 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1459 config ARCH_FORCE_MAX_ORDER
1461 default "14" if ARM64_64K_PAGES
1462 default "12" if ARM64_16K_PAGES
1465 The kernel memory allocator divides physically contiguous memory
1466 blocks into "zones", where each zone is a power of two number of
1467 pages. This option selects the largest power of two that the kernel
1468 keeps in the memory allocator. If you need to allocate very large
1469 blocks of physically contiguous memory, then you may need to
1470 increase this value.
1472 This config option is actually maximum order plus one. For example,
1473 a value of 11 means that the largest free memory block is 2^10 pages.
1475 We make sure that we can allocate upto a HugePage size for each configuration.
1477 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1479 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1480 4M allocations matching the default size used by generic code.
1482 config UNMAP_KERNEL_AT_EL0
1483 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1486 Speculation attacks against some high-performance processors can
1487 be used to bypass MMU permission checks and leak kernel data to
1488 userspace. This can be defended against by unmapping the kernel
1489 when running in userspace, mapping it back in on exception entry
1490 via a trampoline page in the vector table.
1494 config MITIGATE_SPECTRE_BRANCH_HISTORY
1495 bool "Mitigate Spectre style attacks against branch history" if EXPERT
1498 Speculation attacks against some high-performance processors can
1499 make use of branch history to influence future speculation.
1500 When taking an exception from user-space, a sequence of branches
1501 or a firmware call overwrites the branch history.
1503 config RODATA_FULL_DEFAULT_ENABLED
1504 bool "Apply r/o permissions of VM areas also to their linear aliases"
1507 Apply read-only attributes of VM areas to the linear alias of
1508 the backing pages as well. This prevents code or read-only data
1509 from being modified (inadvertently or intentionally) via another
1510 mapping of the same memory page. This additional enhancement can
1511 be turned off at runtime by passing rodata=[off|on] (and turned on
1512 with rodata=full if this option is set to 'n')
1514 This requires the linear region to be mapped down to pages,
1515 which may adversely affect performance in some cases.
1517 config ARM64_SW_TTBR0_PAN
1518 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1520 Enabling this option prevents the kernel from accessing
1521 user-space memory directly by pointing TTBR0_EL1 to a reserved
1522 zeroed area and reserved ASID. The user access routines
1523 restore the valid TTBR0_EL1 temporarily.
1525 config ARM64_TAGGED_ADDR_ABI
1526 bool "Enable the tagged user addresses syscall ABI"
1529 When this option is enabled, user applications can opt in to a
1530 relaxed ABI via prctl() allowing tagged addresses to be passed
1531 to system calls as pointer arguments. For details, see
1532 Documentation/arm64/tagged-address-abi.rst.
1535 bool "Kernel support for 32-bit EL0"
1536 depends on ARM64_4K_PAGES || EXPERT
1538 select OLD_SIGSUSPEND3
1539 select COMPAT_OLD_SIGACTION
1541 This option enables support for a 32-bit EL0 running under a 64-bit
1542 kernel at EL1. AArch32-specific components such as system calls,
1543 the user helper functions, VFP support and the ptrace interface are
1544 handled appropriately by the kernel.
1546 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1547 that you will only be able to execute AArch32 binaries that were compiled
1548 with page size aligned segments.
1550 If you want to execute 32-bit userspace applications, say Y.
1554 config KUSER_HELPERS
1555 bool "Enable kuser helpers page for 32-bit applications"
1558 Warning: disabling this option may break 32-bit user programs.
1560 Provide kuser helpers to compat tasks. The kernel provides
1561 helper code to userspace in read only form at a fixed location
1562 to allow userspace to be independent of the CPU type fitted to
1563 the system. This permits binaries to be run on ARMv4 through
1564 to ARMv8 without modification.
1566 See Documentation/arm/kernel_user_helpers.rst for details.
1568 However, the fixed address nature of these helpers can be used
1569 by ROP (return orientated programming) authors when creating
1572 If all of the binaries and libraries which run on your platform
1573 are built specifically for your platform, and make no use of
1574 these helpers, then you can turn this option off to hinder
1575 such exploits. However, in that case, if a binary or library
1576 relying on those helpers is run, it will not function correctly.
1578 Say N here only if you are absolutely certain that you do not
1579 need these helpers; otherwise, the safe option is to say Y.
1582 bool "Enable vDSO for 32-bit applications"
1583 depends on !CPU_BIG_ENDIAN
1584 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1585 select GENERIC_COMPAT_VDSO
1588 Place in the process address space of 32-bit applications an
1589 ELF shared object providing fast implementations of gettimeofday
1592 You must have a 32-bit build of glibc 2.22 or later for programs
1593 to seamlessly take advantage of this.
1595 config THUMB2_COMPAT_VDSO
1596 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1597 depends on COMPAT_VDSO
1600 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1601 otherwise with '-marm'.
1603 config COMPAT_ALIGNMENT_FIXUPS
1604 bool "Fix up misaligned multi-word loads and stores in user space"
1606 menuconfig ARMV8_DEPRECATED
1607 bool "Emulate deprecated/obsolete ARMv8 instructions"
1610 Legacy software support may require certain instructions
1611 that have been deprecated or obsoleted in the architecture.
1613 Enable this config to enable selective emulation of these
1620 config SWP_EMULATION
1621 bool "Emulate SWP/SWPB instructions"
1623 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1624 they are always undefined. Say Y here to enable software
1625 emulation of these instructions for userspace using LDXR/STXR.
1626 This feature can be controlled at runtime with the abi.swp
1627 sysctl which is disabled by default.
1629 In some older versions of glibc [<=2.8] SWP is used during futex
1630 trylock() operations with the assumption that the code will not
1631 be preempted. This invalid assumption may be more likely to fail
1632 with SWP emulation enabled, leading to deadlock of the user
1635 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1636 on an external transaction monitoring block called a global
1637 monitor to maintain update atomicity. If your system does not
1638 implement a global monitor, this option can cause programs that
1639 perform SWP operations to uncached memory to deadlock.
1643 config CP15_BARRIER_EMULATION
1644 bool "Emulate CP15 Barrier instructions"
1646 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1647 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1648 strongly recommended to use the ISB, DSB, and DMB
1649 instructions instead.
1651 Say Y here to enable software emulation of these
1652 instructions for AArch32 userspace code. When this option is
1653 enabled, CP15 barrier usage is traced which can help
1654 identify software that needs updating. This feature can be
1655 controlled at runtime with the abi.cp15_barrier sysctl.
1659 config SETEND_EMULATION
1660 bool "Emulate SETEND instruction"
1662 The SETEND instruction alters the data-endianness of the
1663 AArch32 EL0, and is deprecated in ARMv8.
1665 Say Y here to enable software emulation of the instruction
1666 for AArch32 userspace code. This feature can be controlled
1667 at runtime with the abi.setend sysctl.
1669 Note: All the cpus on the system must have mixed endian support at EL0
1670 for this feature to be enabled. If a new CPU - which doesn't support mixed
1671 endian - is hotplugged in after this feature has been enabled, there could
1672 be unexpected results in the applications.
1675 endif # ARMV8_DEPRECATED
1679 menu "ARMv8.1 architectural features"
1681 config ARM64_HW_AFDBM
1682 bool "Support for hardware updates of the Access and Dirty page flags"
1685 The ARMv8.1 architecture extensions introduce support for
1686 hardware updates of the access and dirty information in page
1687 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1688 capable processors, accesses to pages with PTE_AF cleared will
1689 set this bit instead of raising an access flag fault.
1690 Similarly, writes to read-only pages with the DBM bit set will
1691 clear the read-only bit (AP[2]) instead of raising a
1694 Kernels built with this configuration option enabled continue
1695 to work on pre-ARMv8.1 hardware and the performance impact is
1696 minimal. If unsure, say Y.
1699 bool "Enable support for Privileged Access Never (PAN)"
1702 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1703 prevents the kernel or hypervisor from accessing user-space (EL0)
1706 Choosing this option will cause any unprotected (not using
1707 copy_to_user et al) memory access to fail with a permission fault.
1709 The feature is detected at runtime, and will remain as a 'nop'
1710 instruction if the cpu does not implement the feature.
1713 def_bool $(as-instr,.arch_extension rcpc)
1715 config AS_HAS_LSE_ATOMICS
1716 def_bool $(as-instr,.arch_extension lse)
1718 config ARM64_LSE_ATOMICS
1720 default ARM64_USE_LSE_ATOMICS
1721 depends on AS_HAS_LSE_ATOMICS
1723 config ARM64_USE_LSE_ATOMICS
1724 bool "Atomic instructions"
1727 As part of the Large System Extensions, ARMv8.1 introduces new
1728 atomic instructions that are designed specifically to scale in
1731 Say Y here to make use of these instructions for the in-kernel
1732 atomic routines. This incurs a small overhead on CPUs that do
1733 not support these instructions and requires the kernel to be
1734 built with binutils >= 2.25 in order for the new instructions
1737 endmenu # "ARMv8.1 architectural features"
1739 menu "ARMv8.2 architectural features"
1741 config AS_HAS_ARMV8_2
1742 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1745 def_bool $(as-instr,.arch armv8.2-a+sha3)
1748 bool "Enable support for persistent memory"
1749 select ARCH_HAS_PMEM_API
1750 select ARCH_HAS_UACCESS_FLUSHCACHE
1752 Say Y to enable support for the persistent memory API based on the
1753 ARMv8.2 DCPoP feature.
1755 The feature is detected at runtime, and the kernel will use DC CVAC
1756 operations if DC CVAP is not supported (following the behaviour of
1757 DC CVAP itself if the system does not define a point of persistence).
1759 config ARM64_RAS_EXTN
1760 bool "Enable support for RAS CPU Extensions"
1763 CPUs that support the Reliability, Availability and Serviceability
1764 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1765 errors, classify them and report them to software.
1767 On CPUs with these extensions system software can use additional
1768 barriers to determine if faults are pending and read the
1769 classification from a new set of registers.
1771 Selecting this feature will allow the kernel to use these barriers
1772 and access the new registers if the system supports the extension.
1773 Platform RAS features may additionally depend on firmware support.
1776 bool "Enable support for Common Not Private (CNP) translations"
1778 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1780 Common Not Private (CNP) allows translation table entries to
1781 be shared between different PEs in the same inner shareable
1782 domain, so the hardware can use this fact to optimise the
1783 caching of such entries in the TLB.
1785 Selecting this option allows the CNP feature to be detected
1786 at runtime, and does not affect PEs that do not implement
1789 endmenu # "ARMv8.2 architectural features"
1791 menu "ARMv8.3 architectural features"
1793 config ARM64_PTR_AUTH
1794 bool "Enable support for pointer authentication"
1797 Pointer authentication (part of the ARMv8.3 Extensions) provides
1798 instructions for signing and authenticating pointers against secret
1799 keys, which can be used to mitigate Return Oriented Programming (ROP)
1802 This option enables these instructions at EL0 (i.e. for userspace).
1803 Choosing this option will cause the kernel to initialise secret keys
1804 for each process at exec() time, with these keys being
1805 context-switched along with the process.
1807 The feature is detected at runtime. If the feature is not present in
1808 hardware it will not be advertised to userspace/KVM guest nor will it
1811 If the feature is present on the boot CPU but not on a late CPU, then
1812 the late CPU will be parked. Also, if the boot CPU does not have
1813 address auth and the late CPU has then the late CPU will still boot
1814 but with the feature disabled. On such a system, this option should
1817 config ARM64_PTR_AUTH_KERNEL
1818 bool "Use pointer authentication for kernel"
1820 depends on ARM64_PTR_AUTH
1821 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1822 # Modern compilers insert a .note.gnu.property section note for PAC
1823 # which is only understood by binutils starting with version 2.33.1.
1824 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1825 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1826 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
1828 If the compiler supports the -mbranch-protection or
1829 -msign-return-address flag (e.g. GCC 7 or later), then this option
1830 will cause the kernel itself to be compiled with return address
1831 protection. In this case, and if the target hardware is known to
1832 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1833 disabled with minimal loss of protection.
1835 This feature works with FUNCTION_GRAPH_TRACER option only if
1836 DYNAMIC_FTRACE_WITH_ARGS is enabled.
1838 config CC_HAS_BRANCH_PROT_PAC_RET
1839 # GCC 9 or later, clang 8 or later
1840 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1842 config CC_HAS_SIGN_RETURN_ADDRESS
1844 def_bool $(cc-option,-msign-return-address=all)
1847 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1849 config AS_HAS_CFI_NEGATE_RA_STATE
1850 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1852 endmenu # "ARMv8.3 architectural features"
1854 menu "ARMv8.4 architectural features"
1856 config ARM64_AMU_EXTN
1857 bool "Enable support for the Activity Monitors Unit CPU extension"
1860 The activity monitors extension is an optional extension introduced
1861 by the ARMv8.4 CPU architecture. This enables support for version 1
1862 of the activity monitors architecture, AMUv1.
1864 To enable the use of this extension on CPUs that implement it, say Y.
1866 Note that for architectural reasons, firmware _must_ implement AMU
1867 support when running on CPUs that present the activity monitors
1868 extension. The required support is present in:
1869 * Version 1.5 and later of the ARM Trusted Firmware
1871 For kernels that have this configuration enabled but boot with broken
1872 firmware, you may need to say N here until the firmware is fixed.
1873 Otherwise you may experience firmware panics or lockups when
1874 accessing the counter registers. Even if you are not observing these
1875 symptoms, the values returned by the register reads might not
1876 correctly reflect reality. Most commonly, the value read will be 0,
1877 indicating that the counter is not enabled.
1879 config AS_HAS_ARMV8_4
1880 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1882 config ARM64_TLB_RANGE
1883 bool "Enable support for tlbi range feature"
1885 depends on AS_HAS_ARMV8_4
1887 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1888 range of input addresses.
1890 The feature introduces new assembly instructions, and they were
1891 support when binutils >= 2.30.
1893 endmenu # "ARMv8.4 architectural features"
1895 menu "ARMv8.5 architectural features"
1897 config AS_HAS_ARMV8_5
1898 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1901 bool "Branch Target Identification support"
1904 Branch Target Identification (part of the ARMv8.5 Extensions)
1905 provides a mechanism to limit the set of locations to which computed
1906 branch instructions such as BR or BLR can jump.
1908 To make use of BTI on CPUs that support it, say Y.
1910 BTI is intended to provide complementary protection to other control
1911 flow integrity protection mechanisms, such as the Pointer
1912 authentication mechanism provided as part of the ARMv8.3 Extensions.
1913 For this reason, it does not make sense to enable this option without
1914 also enabling support for pointer authentication. Thus, when
1915 enabling this option you should also select ARM64_PTR_AUTH=y.
1917 Userspace binaries must also be specifically compiled to make use of
1918 this mechanism. If you say N here or the hardware does not support
1919 BTI, such binaries can still run, but you get no additional
1920 enforcement of branch destinations.
1922 config ARM64_BTI_KERNEL
1923 bool "Use Branch Target Identification for kernel"
1925 depends on ARM64_BTI
1926 depends on ARM64_PTR_AUTH_KERNEL
1927 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1928 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1929 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1930 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671
1931 depends on !CC_IS_GCC
1932 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1933 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
1934 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
1936 Build the kernel with Branch Target Identification annotations
1937 and enable enforcement of this for kernel code. When this option
1938 is enabled and the system supports BTI all kernel code including
1939 modular code must have BTI enabled.
1941 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1942 # GCC 9 or later, clang 8 or later
1943 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1946 bool "Enable support for E0PD"
1949 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1950 that EL0 accesses made via TTBR1 always fault in constant time,
1951 providing similar benefits to KASLR as those provided by KPTI, but
1952 with lower overhead and without disrupting legitimate access to
1953 kernel memory such as SPE.
1955 This option enables E0PD for TTBR1 where available.
1957 config ARM64_AS_HAS_MTE
1958 # Initial support for MTE went in binutils 2.32.0, checked with
1959 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1960 # as a late addition to the final architecture spec (LDGM/STGM)
1961 # is only supported in the newer 2.32.x and 2.33 binutils
1962 # versions, hence the extra "stgm" instruction check below.
1963 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1966 bool "Memory Tagging Extension support"
1968 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1969 depends on AS_HAS_ARMV8_5
1970 depends on AS_HAS_LSE_ATOMICS
1971 # Required for tag checking in the uaccess routines
1972 depends on ARM64_PAN
1973 select ARCH_HAS_SUBPAGE_FAULTS
1974 select ARCH_USES_HIGH_VMA_FLAGS
1975 select ARCH_USES_PG_ARCH_X
1977 Memory Tagging (part of the ARMv8.5 Extensions) provides
1978 architectural support for run-time, always-on detection of
1979 various classes of memory error to aid with software debugging
1980 to eliminate vulnerabilities arising from memory-unsafe
1983 This option enables the support for the Memory Tagging
1984 Extension at EL0 (i.e. for userspace).
1986 Selecting this option allows the feature to be detected at
1987 runtime. Any secondary CPU not implementing this feature will
1988 not be allowed a late bring-up.
1990 Userspace binaries that want to use this feature must
1991 explicitly opt in. The mechanism for the userspace is
1994 Documentation/arm64/memory-tagging-extension.rst.
1996 endmenu # "ARMv8.5 architectural features"
1998 menu "ARMv8.7 architectural features"
2001 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
2003 depends on ARM64_PAN
2005 Enhanced Privileged Access Never (EPAN) allows Privileged
2006 Access Never to be used with Execute-only mappings.
2008 The feature is detected at runtime, and will remain disabled
2009 if the cpu does not implement the feature.
2010 endmenu # "ARMv8.7 architectural features"
2013 bool "ARM Scalable Vector Extension support"
2016 The Scalable Vector Extension (SVE) is an extension to the AArch64
2017 execution state which complements and extends the SIMD functionality
2018 of the base architecture to support much larger vectors and to enable
2019 additional vectorisation opportunities.
2021 To enable use of this extension on CPUs that implement it, say Y.
2023 On CPUs that support the SVE2 extensions, this option will enable
2026 Note that for architectural reasons, firmware _must_ implement SVE
2027 support when running on SVE capable hardware. The required support
2030 * version 1.5 and later of the ARM Trusted Firmware
2031 * the AArch64 boot wrapper since commit 5e1261e08abf
2032 ("bootwrapper: SVE: Enable SVE for EL2 and below").
2034 For other firmware implementations, consult the firmware documentation
2037 If you need the kernel to boot on SVE-capable hardware with broken
2038 firmware, you may need to say N here until you get your firmware
2039 fixed. Otherwise, you may experience firmware panics or lockups when
2040 booting the kernel. If unsure and you are not observing these
2041 symptoms, you should assume that it is safe to say Y.
2044 bool "ARM Scalable Matrix Extension support"
2046 depends on ARM64_SVE
2048 The Scalable Matrix Extension (SME) is an extension to the AArch64
2049 execution state which utilises a substantial subset of the SVE
2050 instruction set, together with the addition of new architectural
2051 register state capable of holding two dimensional matrix tiles to
2052 enable various matrix operations.
2054 config ARM64_MODULE_PLTS
2055 bool "Use PLTs to allow module memory to spill over into vmalloc area"
2057 select HAVE_MOD_ARCH_SPECIFIC
2059 Allocate PLTs when loading modules so that jumps and calls whose
2060 targets are too far away for their relative offsets to be encoded
2061 in the instructions themselves can be bounced via veneers in the
2062 module's PLT. This allows modules to be allocated in the generic
2063 vmalloc area after the dedicated module memory area has been
2066 When running with address space randomization (KASLR), the module
2067 region itself may be too far away for ordinary relative jumps and
2068 calls, and so in that case, module PLTs are required and cannot be
2071 Specific errata workaround(s) might also force module PLTs to be
2072 enabled (ARM64_ERRATUM_843419).
2074 config ARM64_PSEUDO_NMI
2075 bool "Support for NMI-like interrupts"
2078 Adds support for mimicking Non-Maskable Interrupts through the use of
2079 GIC interrupt priority. This support requires version 3 or later of
2082 This high priority configuration for interrupts needs to be
2083 explicitly enabled by setting the kernel parameter
2084 "irqchip.gicv3_pseudo_nmi" to 1.
2089 config ARM64_DEBUG_PRIORITY_MASKING
2090 bool "Debug interrupt priority masking"
2092 This adds runtime checks to functions enabling/disabling
2093 interrupts when using priority masking. The additional checks verify
2094 the validity of ICC_PMR_EL1 when calling concerned functions.
2097 endif # ARM64_PSEUDO_NMI
2100 bool "Build a relocatable kernel image" if EXPERT
2101 select ARCH_HAS_RELR
2104 This builds the kernel as a Position Independent Executable (PIE),
2105 which retains all relocation metadata required to relocate the
2106 kernel binary at runtime to a different virtual address than the
2107 address it was linked at.
2108 Since AArch64 uses the RELA relocation format, this requires a
2109 relocation pass at runtime even if the kernel is loaded at the
2110 same address it was linked at.
2112 config RANDOMIZE_BASE
2113 bool "Randomize the address of the kernel image"
2114 select ARM64_MODULE_PLTS if MODULES
2117 Randomizes the virtual address at which the kernel image is
2118 loaded, as a security feature that deters exploit attempts
2119 relying on knowledge of the location of kernel internals.
2121 It is the bootloader's job to provide entropy, by passing a
2122 random u64 value in /chosen/kaslr-seed at kernel entry.
2124 When booting via the UEFI stub, it will invoke the firmware's
2125 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
2126 to the kernel proper. In addition, it will randomise the physical
2127 location of the kernel Image as well.
2131 config RANDOMIZE_MODULE_REGION_FULL
2132 bool "Randomize the module region over a 2 GB range"
2133 depends on RANDOMIZE_BASE
2136 Randomizes the location of the module region inside a 2 GB window
2137 covering the core kernel. This way, it is less likely for modules
2138 to leak information about the location of core kernel data structures
2139 but it does imply that function calls between modules and the core
2140 kernel will need to be resolved via veneers in the module PLT.
2142 When this option is not set, the module region will be randomized over
2143 a limited range that contains the [_stext, _etext] interval of the
2144 core kernel, so branch relocations are almost always in range unless
2145 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this
2146 particular case of region exhaustion, modules might be able to fall
2147 back to a larger 2GB area.
2149 config CC_HAVE_STACKPROTECTOR_SYSREG
2150 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
2152 config STACKPROTECTOR_PER_TASK
2154 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
2156 config UNWIND_PATCH_PAC_INTO_SCS
2157 bool "Enable shadow call stack dynamically using code patching"
2158 # needs Clang with https://reviews.llvm.org/D111780 incorporated
2159 depends on CC_IS_CLANG && CLANG_VERSION >= 150000
2160 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET
2161 depends on SHADOW_CALL_STACK
2162 select UNWIND_TABLES
2165 endmenu # "Kernel Features"
2169 config ARM64_ACPI_PARKING_PROTOCOL
2170 bool "Enable support for the ARM64 ACPI parking protocol"
2173 Enable support for the ARM64 ACPI parking protocol. If disabled
2174 the kernel will not allow booting through the ARM64 ACPI parking
2175 protocol even if the corresponding data is present in the ACPI
2179 string "Default kernel command string"
2182 Provide a set of default command-line options at build time by
2183 entering them here. As a minimum, you should specify the the
2184 root device (e.g. root=/dev/nfs).
2187 prompt "Kernel command line type" if CMDLINE != ""
2188 default CMDLINE_FROM_BOOTLOADER
2190 Choose how the kernel will handle the provided default kernel
2191 command line string.
2193 config CMDLINE_FROM_BOOTLOADER
2194 bool "Use bootloader kernel arguments if available"
2196 Uses the command-line options passed by the boot loader. If
2197 the boot loader doesn't provide any, the default kernel command
2198 string provided in CMDLINE will be used.
2200 config CMDLINE_FORCE
2201 bool "Always use the default kernel command string"
2203 Always use the default kernel command string, even if the boot
2204 loader passes other arguments to the kernel.
2205 This is useful if you cannot or don't want to change the
2206 command-line options your boot loader passes to the kernel.
2214 bool "UEFI runtime support"
2215 depends on OF && !CPU_BIG_ENDIAN
2216 depends on KERNEL_MODE_NEON
2217 select ARCH_SUPPORTS_ACPI
2220 select EFI_PARAMS_FROM_FDT
2221 select EFI_RUNTIME_WRAPPERS
2223 select EFI_GENERIC_STUB
2224 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
2227 This option provides support for runtime services provided
2228 by UEFI firmware (such as non-volatile variables, realtime
2229 clock, and platform reset). A UEFI stub is also provided to
2230 allow the kernel to be booted as an EFI application. This
2231 is only useful on systems that have UEFI firmware.
2234 bool "Enable support for SMBIOS (DMI) tables"
2238 This enables SMBIOS/DMI feature for systems.
2240 This option is only useful on systems that have UEFI firmware.
2241 However, even with this option, the resultant kernel should
2242 continue to boot on existing non-UEFI platforms.
2244 endmenu # "Boot options"
2246 menu "Power management options"
2248 source "kernel/power/Kconfig"
2250 config ARCH_HIBERNATION_POSSIBLE
2254 config ARCH_HIBERNATION_HEADER
2256 depends on HIBERNATION
2258 config ARCH_SUSPEND_POSSIBLE
2261 endmenu # "Power management options"
2263 menu "CPU Power Management"
2265 source "drivers/cpuidle/Kconfig"
2267 source "drivers/cpufreq/Kconfig"
2269 endmenu # "CPU Power Management"
2271 source "drivers/acpi/Kconfig"
2273 source "arch/arm64/kvm/Kconfig"