1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_APMT if ACPI
5 select ACPI_CCA_REQUIRED if ACPI
6 select ACPI_GENERIC_GSI if ACPI
7 select ACPI_GTDT if ACPI
8 select ACPI_IORT if ACPI
9 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
10 select ACPI_MCFG if (ACPI && PCI)
11 select ACPI_SPCR_TABLE if ACPI
12 select ACPI_PPTT if ACPI
13 select ARCH_HAS_DEBUG_WX
14 select ARCH_BINFMT_ELF_EXTRA_PHDRS
15 select ARCH_BINFMT_ELF_STATE
16 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE
17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
18 select ARCH_ENABLE_MEMORY_HOTPLUG
19 select ARCH_ENABLE_MEMORY_HOTREMOVE
20 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
21 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
22 select ARCH_HAS_CACHE_LINE_SIZE
23 select ARCH_HAS_CURRENT_STACK_POINTER
24 select ARCH_HAS_DEBUG_VIRTUAL
25 select ARCH_HAS_DEBUG_VM_PGTABLE
26 select ARCH_HAS_DMA_PREP_COHERENT
27 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
28 select ARCH_HAS_FAST_MULTIPLIER
29 select ARCH_HAS_FORTIFY_SOURCE
30 select ARCH_HAS_GCOV_PROFILE_ALL
31 select ARCH_HAS_GIGANTIC_PAGE
33 select ARCH_HAS_KEEPINITRD
34 select ARCH_HAS_MEMBARRIER_SYNC_CORE
35 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS
36 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
37 select ARCH_HAS_PTE_DEVMAP
38 select ARCH_HAS_PTE_SPECIAL
39 select ARCH_HAS_SETUP_DMA_OPS
40 select ARCH_HAS_SET_DIRECT_MAP
41 select ARCH_HAS_SET_MEMORY
43 select ARCH_HAS_STRICT_KERNEL_RWX
44 select ARCH_HAS_STRICT_MODULE_RWX
45 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
46 select ARCH_HAS_SYNC_DMA_FOR_CPU
47 select ARCH_HAS_SYSCALL_WRAPPER
48 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
49 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
50 select ARCH_HAS_ZONE_DMA_SET if EXPERT
51 select ARCH_HAVE_ELF_PROT
52 select ARCH_HAVE_NMI_SAFE_CMPXCHG
53 select ARCH_HAVE_TRACE_MMIO_ACCESS
54 select ARCH_INLINE_READ_LOCK if !PREEMPTION
55 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
56 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
57 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
58 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
59 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
60 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
61 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
62 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
63 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
64 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
65 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
66 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
67 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
68 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
69 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
70 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
71 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
72 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
73 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
74 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
75 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
76 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
77 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
78 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
79 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
80 select ARCH_KEEP_MEMBLOCK
81 select ARCH_USE_CMPXCHG_LOCKREF
82 select ARCH_USE_GNU_PROPERTY
83 select ARCH_USE_MEMTEST
84 select ARCH_USE_QUEUED_RWLOCKS
85 select ARCH_USE_QUEUED_SPINLOCKS
86 select ARCH_USE_SYM_ANNOTATIONS
87 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
88 select ARCH_SUPPORTS_HUGETLBFS
89 select ARCH_SUPPORTS_MEMORY_FAILURE
90 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
91 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
92 select ARCH_SUPPORTS_LTO_CLANG_THIN
93 select ARCH_SUPPORTS_CFI_CLANG
94 select ARCH_SUPPORTS_ATOMIC_RMW
95 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
96 select ARCH_SUPPORTS_NUMA_BALANCING
97 select ARCH_SUPPORTS_PAGE_TABLE_CHECK
98 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
99 select ARCH_WANT_DEFAULT_BPF_JIT
100 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
101 select ARCH_WANT_FRAME_POINTERS
102 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
103 select ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP
104 select ARCH_WANT_LD_ORPHAN_WARN
105 select ARCH_WANTS_NO_INSTR
106 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES
107 select ARCH_HAS_UBSAN_SANITIZE_ALL
109 select ARM_ARCH_TIMER
111 select AUDIT_ARCH_COMPAT_GENERIC
112 select ARM_GIC_V2M if PCI
114 select ARM_GIC_V3_ITS if PCI
116 select BUILDTIME_TABLE_SORT
117 select CLONE_BACKWARDS
119 select CPU_PM if (SUSPEND || CPU_IDLE)
121 select DCACHE_WORD_ACCESS
122 select DYNAMIC_FTRACE if FUNCTION_TRACER
123 select DMA_DIRECT_REMAP
126 select GENERIC_ALLOCATOR
127 select GENERIC_ARCH_TOPOLOGY
128 select GENERIC_CLOCKEVENTS_BROADCAST
129 select GENERIC_CPU_AUTOPROBE
130 select GENERIC_CPU_VULNERABILITIES
131 select GENERIC_EARLY_IOREMAP
132 select GENERIC_IDLE_POLL_SETUP
133 select GENERIC_IOREMAP
134 select GENERIC_IRQ_IPI
135 select GENERIC_IRQ_PROBE
136 select GENERIC_IRQ_SHOW
137 select GENERIC_IRQ_SHOW_LEVEL
138 select GENERIC_LIB_DEVMEM_IS_ALLOWED
139 select GENERIC_PCI_IOMAP
140 select GENERIC_PTDUMP
141 select GENERIC_SCHED_CLOCK
142 select GENERIC_SMP_IDLE_THREAD
143 select GENERIC_TIME_VSYSCALL
144 select GENERIC_GETTIMEOFDAY
145 select GENERIC_VDSO_TIME_NS
146 select HARDIRQS_SW_RESEND
150 select HAVE_ACPI_APEI if (ACPI && EFI)
151 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
152 select HAVE_ARCH_AUDITSYSCALL
153 select HAVE_ARCH_BITREVERSE
154 select HAVE_ARCH_COMPILER_H
155 select HAVE_ARCH_HUGE_VMALLOC
156 select HAVE_ARCH_HUGE_VMAP
157 select HAVE_ARCH_JUMP_LABEL
158 select HAVE_ARCH_JUMP_LABEL_RELATIVE
159 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
160 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
161 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
162 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
163 # Some instrumentation may be unsound, hence EXPERT
164 select HAVE_ARCH_KCSAN if EXPERT
165 select HAVE_ARCH_KFENCE
166 select HAVE_ARCH_KGDB
167 select HAVE_ARCH_MMAP_RND_BITS
168 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
169 select HAVE_ARCH_PREL32_RELOCATIONS
170 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
171 select HAVE_ARCH_SECCOMP_FILTER
172 select HAVE_ARCH_STACKLEAK
173 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
174 select HAVE_ARCH_TRACEHOOK
175 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
176 select HAVE_ARCH_VMAP_STACK
177 select HAVE_ARM_SMCCC
178 select HAVE_ASM_MODVERSIONS
180 select HAVE_C_RECORDMCOUNT
181 select HAVE_CMPXCHG_DOUBLE
182 select HAVE_CMPXCHG_LOCAL
183 select HAVE_CONTEXT_TRACKING_USER
184 select HAVE_DEBUG_KMEMLEAK
185 select HAVE_DMA_CONTIGUOUS
186 select HAVE_DYNAMIC_FTRACE
187 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \
188 if $(cc-option,-fpatchable-function-entry=2)
189 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
190 if DYNAMIC_FTRACE_WITH_ARGS
191 select HAVE_EFFICIENT_UNALIGNED_ACCESS
193 select HAVE_FTRACE_MCOUNT_RECORD
194 select HAVE_FUNCTION_TRACER
195 select HAVE_FUNCTION_ERROR_INJECTION
196 select HAVE_FUNCTION_GRAPH_TRACER
197 select HAVE_GCC_PLUGINS
198 select HAVE_HW_BREAKPOINT if PERF_EVENTS
199 select HAVE_IOREMAP_PROT
200 select HAVE_IRQ_TIME_ACCOUNTING
203 select HAVE_PERF_EVENTS
204 select HAVE_PERF_REGS
205 select HAVE_PERF_USER_STACK_DUMP
206 select HAVE_PREEMPT_DYNAMIC_KEY
207 select HAVE_REGS_AND_STACK_ACCESS_API
208 select HAVE_POSIX_CPU_TIMERS_TASK_WORK
209 select HAVE_FUNCTION_ARG_ACCESS_API
210 select MMU_GATHER_RCU_TABLE_FREE
212 select HAVE_STACKPROTECTOR
213 select HAVE_SYSCALL_TRACEPOINTS
215 select HAVE_KRETPROBES
216 select HAVE_GENERIC_VDSO
218 select IRQ_FORCED_THREADING
219 select KASAN_VMALLOC if KASAN
220 select MODULES_USE_ELF_RELA
221 select NEED_DMA_MAP_STATE
222 select NEED_SG_DMA_LENGTH
224 select OF_EARLY_FLATTREE
225 select PCI_DOMAINS_GENERIC if PCI
226 select PCI_ECAM if (ACPI && PCI)
227 select PCI_SYSCALL if PCI
232 select SYSCTL_EXCEPTION_TRACE
233 select THREAD_INFO_IN_TASK
234 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
235 select TRACE_IRQFLAGS_SUPPORT
236 select TRACE_IRQFLAGS_NMI_SUPPORT
237 select HAVE_SOFTIRQ_ON_OWN_STACK
239 ARM 64-bit (AArch64) Linux support.
241 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
243 # https://github.com/ClangBuiltLinux/linux/issues/1507
244 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600))
245 select HAVE_DYNAMIC_FTRACE_WITH_ARGS
247 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
249 depends on $(cc-option,-fpatchable-function-entry=2)
250 select HAVE_DYNAMIC_FTRACE_WITH_ARGS
258 config ARM64_PAGE_SHIFT
260 default 16 if ARM64_64K_PAGES
261 default 14 if ARM64_16K_PAGES
264 config ARM64_CONT_PTE_SHIFT
266 default 5 if ARM64_64K_PAGES
267 default 7 if ARM64_16K_PAGES
270 config ARM64_CONT_PMD_SHIFT
272 default 5 if ARM64_64K_PAGES
273 default 5 if ARM64_16K_PAGES
276 config ARCH_MMAP_RND_BITS_MIN
277 default 14 if ARM64_64K_PAGES
278 default 16 if ARM64_16K_PAGES
281 # max bits determined by the following formula:
282 # VA_BITS - PAGE_SHIFT - 3
283 config ARCH_MMAP_RND_BITS_MAX
284 default 19 if ARM64_VA_BITS=36
285 default 24 if ARM64_VA_BITS=39
286 default 27 if ARM64_VA_BITS=42
287 default 30 if ARM64_VA_BITS=47
288 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
289 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
290 default 33 if ARM64_VA_BITS=48
291 default 14 if ARM64_64K_PAGES
292 default 16 if ARM64_16K_PAGES
295 config ARCH_MMAP_RND_COMPAT_BITS_MIN
296 default 7 if ARM64_64K_PAGES
297 default 9 if ARM64_16K_PAGES
300 config ARCH_MMAP_RND_COMPAT_BITS_MAX
306 config STACKTRACE_SUPPORT
309 config ILLEGAL_POINTER_VALUE
311 default 0xdead000000000000
313 config LOCKDEP_SUPPORT
320 config GENERIC_BUG_RELATIVE_POINTERS
322 depends on GENERIC_BUG
324 config GENERIC_HWEIGHT
330 config GENERIC_CALIBRATE_DELAY
333 config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
339 config KERNEL_MODE_NEON
342 config FIX_EARLYCON_MEM
345 config PGTABLE_LEVELS
347 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
348 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
349 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
350 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
351 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
352 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
354 config ARCH_SUPPORTS_UPROBES
357 config ARCH_PROC_KCORE_TEXT
360 config BROKEN_GAS_INST
361 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
363 config KASAN_SHADOW_OFFSET
365 depends on KASAN_GENERIC || KASAN_SW_TAGS
366 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
367 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
368 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
369 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
370 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
371 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
372 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
373 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
374 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
375 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
376 default 0xffffffffffffffff
381 source "arch/arm64/Kconfig.platforms"
383 menu "Kernel Features"
385 menu "ARM errata workarounds via the alternatives framework"
387 config ARM64_WORKAROUND_CLEAN_CACHE
390 config ARM64_ERRATUM_826319
391 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
393 select ARM64_WORKAROUND_CLEAN_CACHE
395 This option adds an alternative code sequence to work around ARM
396 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
397 AXI master interface and an L2 cache.
399 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
400 and is unable to accept a certain write via this interface, it will
401 not progress on read data presented on the read data channel and the
404 The workaround promotes data cache clean instructions to
405 data cache clean-and-invalidate.
406 Please note that this does not necessarily enable the workaround,
407 as it depends on the alternative framework, which will only patch
408 the kernel if an affected CPU is detected.
412 config ARM64_ERRATUM_827319
413 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
415 select ARM64_WORKAROUND_CLEAN_CACHE
417 This option adds an alternative code sequence to work around ARM
418 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
419 master interface and an L2 cache.
421 Under certain conditions this erratum can cause a clean line eviction
422 to occur at the same time as another transaction to the same address
423 on the AMBA 5 CHI interface, which can cause data corruption if the
424 interconnect reorders the two transactions.
426 The workaround promotes data cache clean instructions to
427 data cache clean-and-invalidate.
428 Please note that this does not necessarily enable the workaround,
429 as it depends on the alternative framework, which will only patch
430 the kernel if an affected CPU is detected.
434 config ARM64_ERRATUM_824069
435 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
437 select ARM64_WORKAROUND_CLEAN_CACHE
439 This option adds an alternative code sequence to work around ARM
440 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
441 to a coherent interconnect.
443 If a Cortex-A53 processor is executing a store or prefetch for
444 write instruction at the same time as a processor in another
445 cluster is executing a cache maintenance operation to the same
446 address, then this erratum might cause a clean cache line to be
447 incorrectly marked as dirty.
449 The workaround promotes data cache clean instructions to
450 data cache clean-and-invalidate.
451 Please note that this option does not necessarily enable the
452 workaround, as it depends on the alternative framework, which will
453 only patch the kernel if an affected CPU is detected.
457 config ARM64_ERRATUM_819472
458 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
460 select ARM64_WORKAROUND_CLEAN_CACHE
462 This option adds an alternative code sequence to work around ARM
463 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
464 present when it is connected to a coherent interconnect.
466 If the processor is executing a load and store exclusive sequence at
467 the same time as a processor in another cluster is executing a cache
468 maintenance operation to the same address, then this erratum might
469 cause data corruption.
471 The workaround promotes data cache clean instructions to
472 data cache clean-and-invalidate.
473 Please note that this does not necessarily enable the workaround,
474 as it depends on the alternative framework, which will only patch
475 the kernel if an affected CPU is detected.
479 config ARM64_ERRATUM_832075
480 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
483 This option adds an alternative code sequence to work around ARM
484 erratum 832075 on Cortex-A57 parts up to r1p2.
486 Affected Cortex-A57 parts might deadlock when exclusive load/store
487 instructions to Write-Back memory are mixed with Device loads.
489 The workaround is to promote device loads to use Load-Acquire
491 Please note that this does not necessarily enable the workaround,
492 as it depends on the alternative framework, which will only patch
493 the kernel if an affected CPU is detected.
497 config ARM64_ERRATUM_834220
498 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
502 This option adds an alternative code sequence to work around ARM
503 erratum 834220 on Cortex-A57 parts up to r1p2.
505 Affected Cortex-A57 parts might report a Stage 2 translation
506 fault as the result of a Stage 1 fault for load crossing a
507 page boundary when there is a permission or device memory
508 alignment fault at Stage 1 and a translation fault at Stage 2.
510 The workaround is to verify that the Stage 1 translation
511 doesn't generate a fault before handling the Stage 2 fault.
512 Please note that this does not necessarily enable the workaround,
513 as it depends on the alternative framework, which will only patch
514 the kernel if an affected CPU is detected.
518 config ARM64_ERRATUM_1742098
519 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence"
523 This option removes the AES hwcap for aarch32 user-space to
524 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
526 Affected parts may corrupt the AES state if an interrupt is
527 taken between a pair of AES instructions. These instructions
528 are only present if the cryptography extensions are present.
529 All software should have a fallback implementation for CPUs
530 that don't implement the cryptography extensions.
534 config ARM64_ERRATUM_845719
535 bool "Cortex-A53: 845719: a load might read incorrect data"
539 This option adds an alternative code sequence to work around ARM
540 erratum 845719 on Cortex-A53 parts up to r0p4.
542 When running a compat (AArch32) userspace on an affected Cortex-A53
543 part, a load at EL0 from a virtual address that matches the bottom 32
544 bits of the virtual address used by a recent load at (AArch64) EL1
545 might return incorrect data.
547 The workaround is to write the contextidr_el1 register on exception
548 return to a 32-bit task.
549 Please note that this does not necessarily enable the workaround,
550 as it depends on the alternative framework, which will only patch
551 the kernel if an affected CPU is detected.
555 config ARM64_ERRATUM_843419
556 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
558 select ARM64_MODULE_PLTS if MODULES
560 This option links the kernel with '--fix-cortex-a53-843419' and
561 enables PLT support to replace certain ADRP instructions, which can
562 cause subsequent memory accesses to use an incorrect address on
563 Cortex-A53 parts up to r0p4.
567 config ARM64_LD_HAS_FIX_ERRATUM_843419
568 def_bool $(ld-option,--fix-cortex-a53-843419)
570 config ARM64_ERRATUM_1024718
571 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
574 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
576 Affected Cortex-A55 cores (all revisions) could cause incorrect
577 update of the hardware dirty bit when the DBM/AP bits are updated
578 without a break-before-make. The workaround is to disable the usage
579 of hardware DBM locally on the affected cores. CPUs not affected by
580 this erratum will continue to use the feature.
584 config ARM64_ERRATUM_1418040
585 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
589 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
590 errata 1188873 and 1418040.
592 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
593 cause register corruption when accessing the timer registers
594 from AArch32 userspace.
598 config ARM64_WORKAROUND_SPECULATIVE_AT
601 config ARM64_ERRATUM_1165522
602 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
604 select ARM64_WORKAROUND_SPECULATIVE_AT
606 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
608 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
609 corrupted TLBs by speculating an AT instruction during a guest
614 config ARM64_ERRATUM_1319367
615 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
617 select ARM64_WORKAROUND_SPECULATIVE_AT
619 This option adds work arounds for ARM Cortex-A57 erratum 1319537
620 and A72 erratum 1319367
622 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
623 speculating an AT instruction during a guest context switch.
627 config ARM64_ERRATUM_1530923
628 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
630 select ARM64_WORKAROUND_SPECULATIVE_AT
632 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
634 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
635 corrupted TLBs by speculating an AT instruction during a guest
640 config ARM64_WORKAROUND_REPEAT_TLBI
643 config ARM64_ERRATUM_2441007
644 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
646 select ARM64_WORKAROUND_REPEAT_TLBI
648 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
650 Under very rare circumstances, affected Cortex-A55 CPUs
651 may not handle a race between a break-before-make sequence on one
652 CPU, and another CPU accessing the same page. This could allow a
653 store to a page that has been unmapped.
655 Work around this by adding the affected CPUs to the list that needs
656 TLB sequences to be done twice.
660 config ARM64_ERRATUM_1286807
661 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
663 select ARM64_WORKAROUND_REPEAT_TLBI
665 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
667 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
668 address for a cacheable mapping of a location is being
669 accessed by a core while another core is remapping the virtual
670 address to a new physical page using the recommended
671 break-before-make sequence, then under very rare circumstances
672 TLBI+DSB completes before a read using the translation being
673 invalidated has been observed by other observers. The
674 workaround repeats the TLBI+DSB operation.
676 config ARM64_ERRATUM_1463225
677 bool "Cortex-A76: Software Step might prevent interrupt recognition"
680 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
682 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
683 of a system call instruction (SVC) can prevent recognition of
684 subsequent interrupts when software stepping is disabled in the
685 exception handler of the system call and either kernel debugging
686 is enabled or VHE is in use.
688 Work around the erratum by triggering a dummy step exception
689 when handling a system call from a task that is being stepped
690 in a VHE configuration of the kernel.
694 config ARM64_ERRATUM_1542419
695 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
698 This option adds a workaround for ARM Neoverse-N1 erratum
701 Affected Neoverse-N1 cores could execute a stale instruction when
702 modified by another CPU. The workaround depends on a firmware
705 Workaround the issue by hiding the DIC feature from EL0. This
706 forces user-space to perform cache maintenance.
710 config ARM64_ERRATUM_1508412
711 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
714 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
716 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
717 of a store-exclusive or read of PAR_EL1 and a load with device or
718 non-cacheable memory attributes. The workaround depends on a firmware
721 KVM guests must also have the workaround implemented or they can
724 Work around the issue by inserting DMB SY barriers around PAR_EL1
725 register reads and warning KVM users. The DMB barrier is sufficient
726 to prevent a speculative PAR_EL1 read.
730 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
733 config ARM64_ERRATUM_2051678
734 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
737 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
738 Affected Cortex-A510 might not respect the ordering rules for
739 hardware update of the page table's dirty bit. The workaround
740 is to not enable the feature on affected CPUs.
744 config ARM64_ERRATUM_2077057
745 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
748 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
749 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
750 expected, but a Pointer Authentication trap is taken instead. The
751 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow
752 EL1 to cause a return to EL2 with a guest controlled ELR_EL2.
754 This can only happen when EL2 is stepping EL1.
756 When these conditions occur, the SPSR_EL2 value is unchanged from the
757 previous guest entry, and can be restored from the in-memory copy.
761 config ARM64_ERRATUM_2658417
762 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
765 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
766 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
767 BFMMLA or VMMLA instructions in rare circumstances when a pair of
768 A510 CPUs are using shared neon hardware. As the sharing is not
769 discoverable by the kernel, hide the BF16 HWCAP to indicate that
770 user-space should not be using these instructions.
774 config ARM64_ERRATUM_2119858
775 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
777 depends on CORESIGHT_TRBE
778 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
780 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
782 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
783 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
784 the event of a WRAP event.
786 Work around the issue by always making sure we move the TRBPTR_EL1 by
787 256 bytes before enabling the buffer and filling the first 256 bytes of
788 the buffer with ETM ignore packets upon disabling.
792 config ARM64_ERRATUM_2139208
793 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
795 depends on CORESIGHT_TRBE
796 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
798 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
800 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
801 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
802 the event of a WRAP event.
804 Work around the issue by always making sure we move the TRBPTR_EL1 by
805 256 bytes before enabling the buffer and filling the first 256 bytes of
806 the buffer with ETM ignore packets upon disabling.
810 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
813 config ARM64_ERRATUM_2054223
814 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
816 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
818 Enable workaround for ARM Cortex-A710 erratum 2054223
820 Affected cores may fail to flush the trace data on a TSB instruction, when
821 the PE is in trace prohibited state. This will cause losing a few bytes
824 Workaround is to issue two TSB consecutively on affected cores.
828 config ARM64_ERRATUM_2067961
829 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
831 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
833 Enable workaround for ARM Neoverse-N2 erratum 2067961
835 Affected cores may fail to flush the trace data on a TSB instruction, when
836 the PE is in trace prohibited state. This will cause losing a few bytes
839 Workaround is to issue two TSB consecutively on affected cores.
843 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
846 config ARM64_ERRATUM_2253138
847 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
848 depends on CORESIGHT_TRBE
850 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
852 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
854 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
855 for TRBE. Under some conditions, the TRBE might generate a write to the next
856 virtually addressed page following the last page of the TRBE address space
857 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
859 Work around this in the driver by always making sure that there is a
860 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
864 config ARM64_ERRATUM_2224489
865 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
866 depends on CORESIGHT_TRBE
868 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
870 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
872 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
873 for TRBE. Under some conditions, the TRBE might generate a write to the next
874 virtually addressed page following the last page of the TRBE address space
875 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
877 Work around this in the driver by always making sure that there is a
878 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
882 config ARM64_ERRATUM_2441009
883 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
885 select ARM64_WORKAROUND_REPEAT_TLBI
887 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
889 Under very rare circumstances, affected Cortex-A510 CPUs
890 may not handle a race between a break-before-make sequence on one
891 CPU, and another CPU accessing the same page. This could allow a
892 store to a page that has been unmapped.
894 Work around this by adding the affected CPUs to the list that needs
895 TLB sequences to be done twice.
899 config ARM64_ERRATUM_2064142
900 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
901 depends on CORESIGHT_TRBE
904 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
906 Affected Cortex-A510 core might fail to write into system registers after the
907 TRBE has been disabled. Under some conditions after the TRBE has been disabled
908 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,
909 and TRBTRG_EL1 will be ignored and will not be effected.
911 Work around this in the driver by executing TSB CSYNC and DSB after collection
912 is stopped and before performing a system register write to one of the affected
917 config ARM64_ERRATUM_2038923
918 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
919 depends on CORESIGHT_TRBE
922 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
924 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
925 prohibited within the CPU. As a result, the trace buffer or trace buffer state
926 might be corrupted. This happens after TRBE buffer has been enabled by setting
927 TRBLIMITR_EL1.E, followed by just a single context synchronization event before
928 execution changes from a context, in which trace is prohibited to one where it
929 isn't, or vice versa. In these mentioned conditions, the view of whether trace
930 is prohibited is inconsistent between parts of the CPU, and the trace buffer or
931 the trace buffer state might be corrupted.
933 Work around this in the driver by preventing an inconsistent view of whether the
934 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
935 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
936 two ISB instructions if no ERET is to take place.
940 config ARM64_ERRATUM_1902691
941 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
942 depends on CORESIGHT_TRBE
945 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
947 Affected Cortex-A510 core might cause trace data corruption, when being written
948 into the memory. Effectively TRBE is broken and hence cannot be used to capture
951 Work around this problem in the driver by just preventing TRBE initialization on
952 affected cpus. The firmware must have disabled the access to TRBE for the kernel
953 on such implementations. This will cover the kernel for any firmware that doesn't
958 config ARM64_ERRATUM_2457168
959 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
960 depends on ARM64_AMU_EXTN
963 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
965 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate
966 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
967 incorrectly giving a significantly higher output value.
969 Work around this problem by returning 0 when reading the affected counter in
970 key locations that results in disabling all users of this counter. This effect
971 is the same to firmware disabling affected counters.
975 config ARM64_ERRATUM_2645198
976 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
979 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
981 If a Cortex-A715 cpu sees a page mapping permissions change from executable
982 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the
983 next instruction abort caused by permission fault.
985 Only user-space does executable to non-executable permission transition via
986 mprotect() system call. Workaround the problem by doing a break-before-make
987 TLB invalidation, for all changes to executable user space mappings.
991 config CAVIUM_ERRATUM_22375
992 bool "Cavium erratum 22375, 24313"
995 Enable workaround for errata 22375 and 24313.
997 This implements two gicv3-its errata workarounds for ThunderX. Both
998 with a small impact affecting only ITS table allocation.
1000 erratum 22375: only alloc 8MB table size
1001 erratum 24313: ignore memory access type
1003 The fixes are in ITS initialization and basically ignore memory access
1004 type and table size provided by the TYPER and BASER registers.
1008 config CAVIUM_ERRATUM_23144
1009 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
1013 ITS SYNC command hang for cross node io and collections/cpu mapping.
1017 config CAVIUM_ERRATUM_23154
1018 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"
1021 The ThunderX GICv3 implementation requires a modified version for
1022 reading the IAR status to ensure data synchronization
1023 (access to icc_iar1_el1 is not sync'ed before and after).
1025 It also suffers from erratum 38545 (also present on Marvell's
1026 OcteonTX and OcteonTX2), resulting in deactivated interrupts being
1027 spuriously presented to the CPU interface.
1031 config CAVIUM_ERRATUM_27456
1032 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
1035 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
1036 instructions may cause the icache to become corrupted if it
1037 contains data for a non-current ASID. The fix is to
1038 invalidate the icache when changing the mm context.
1042 config CAVIUM_ERRATUM_30115
1043 bool "Cavium erratum 30115: Guest may disable interrupts in host"
1046 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
1047 1.2, and T83 Pass 1.0, KVM guest execution may disable
1048 interrupts in host. Trapping both GICv3 group-0 and group-1
1049 accesses sidesteps the issue.
1053 config CAVIUM_TX2_ERRATUM_219
1054 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
1057 On Cavium ThunderX2, a load, store or prefetch instruction between a
1058 TTBR update and the corresponding context synchronizing operation can
1059 cause a spurious Data Abort to be delivered to any hardware thread in
1062 Work around the issue by avoiding the problematic code sequence and
1063 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
1064 trap handler performs the corresponding register access, skips the
1065 instruction and ensures context synchronization by virtue of the
1070 config FUJITSU_ERRATUM_010001
1071 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1074 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1075 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1076 accesses may cause undefined fault (Data abort, DFSC=0b111111).
1077 This fault occurs under a specific hardware condition when a
1078 load/store instruction performs an address translation using:
1079 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1080 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1081 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1082 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1084 The workaround is to ensure these bits are clear in TCR_ELx.
1085 The workaround only affects the Fujitsu-A64FX.
1089 config HISILICON_ERRATUM_161600802
1090 bool "Hip07 161600802: Erroneous redistributor VLPI base"
1093 The HiSilicon Hip07 SoC uses the wrong redistributor base
1094 when issued ITS commands such as VMOVP and VMAPP, and requires
1095 a 128kB offset to be applied to the target address in this commands.
1099 config QCOM_FALKOR_ERRATUM_1003
1100 bool "Falkor E1003: Incorrect translation due to ASID change"
1103 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
1104 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
1105 in TTBR1_EL1, this situation only occurs in the entry trampoline and
1106 then only for entries in the walk cache, since the leaf translation
1107 is unchanged. Work around the erratum by invalidating the walk cache
1108 entries for the trampoline before entering the kernel proper.
1110 config QCOM_FALKOR_ERRATUM_1009
1111 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
1113 select ARM64_WORKAROUND_REPEAT_TLBI
1115 On Falkor v1, the CPU may prematurely complete a DSB following a
1116 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
1117 one more time to fix the issue.
1121 config QCOM_QDF2400_ERRATUM_0065
1122 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
1125 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
1126 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
1127 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
1131 config QCOM_FALKOR_ERRATUM_E1041
1132 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
1135 Falkor CPU may speculatively fetch instructions from an improper
1136 memory location when MMU translation is changed from SCTLR_ELn[M]=1
1137 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
1141 config NVIDIA_CARMEL_CNP_ERRATUM
1142 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
1145 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1146 invalidate shared TLB entries installed by a different core, as it would
1147 on standard ARM cores.
1151 config SOCIONEXT_SYNQUACER_PREITS
1152 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1155 Socionext Synquacer SoCs implement a separate h/w block to generate
1156 MSI doorbell writes with non-zero values for the device ID.
1160 endmenu # "ARM errata workarounds via the alternatives framework"
1164 default ARM64_4K_PAGES
1166 Page size (translation granule) configuration.
1168 config ARM64_4K_PAGES
1171 This feature enables 4KB pages support.
1173 config ARM64_16K_PAGES
1176 The system will use 16KB pages support. AArch32 emulation
1177 requires applications compiled with 16K (or a multiple of 16K)
1180 config ARM64_64K_PAGES
1183 This feature enables 64KB pages support (4KB by default)
1184 allowing only two levels of page tables and faster TLB
1185 look-up. AArch32 emulation requires applications compiled
1186 with 64K aligned segments.
1191 prompt "Virtual address space size"
1192 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
1193 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
1194 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
1196 Allows choosing one of multiple possible virtual address
1197 space sizes. The level of translation table is determined by
1198 a combination of page size and virtual address space size.
1200 config ARM64_VA_BITS_36
1201 bool "36-bit" if EXPERT
1202 depends on ARM64_16K_PAGES
1204 config ARM64_VA_BITS_39
1206 depends on ARM64_4K_PAGES
1208 config ARM64_VA_BITS_42
1210 depends on ARM64_64K_PAGES
1212 config ARM64_VA_BITS_47
1214 depends on ARM64_16K_PAGES
1216 config ARM64_VA_BITS_48
1219 config ARM64_VA_BITS_52
1221 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
1223 Enable 52-bit virtual addressing for userspace when explicitly
1224 requested via a hint to mmap(). The kernel will also use 52-bit
1225 virtual addresses for its own mappings (provided HW support for
1226 this feature is available, otherwise it reverts to 48-bit).
1228 NOTE: Enabling 52-bit virtual addressing in conjunction with
1229 ARMv8.3 Pointer Authentication will result in the PAC being
1230 reduced from 7 bits to 3 bits, which may have a significant
1231 impact on its susceptibility to brute-force attacks.
1233 If unsure, select 48-bit virtual addressing instead.
1237 config ARM64_FORCE_52BIT
1238 bool "Force 52-bit virtual addresses for userspace"
1239 depends on ARM64_VA_BITS_52 && EXPERT
1241 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1242 to maintain compatibility with older software by providing 48-bit VAs
1243 unless a hint is supplied to mmap.
1245 This configuration option disables the 48-bit compatibility logic, and
1246 forces all userspace addresses to be 52-bit on HW that supports it. One
1247 should only enable this configuration option for stress testing userspace
1248 memory management code. If unsure say N here.
1250 config ARM64_VA_BITS
1252 default 36 if ARM64_VA_BITS_36
1253 default 39 if ARM64_VA_BITS_39
1254 default 42 if ARM64_VA_BITS_42
1255 default 47 if ARM64_VA_BITS_47
1256 default 48 if ARM64_VA_BITS_48
1257 default 52 if ARM64_VA_BITS_52
1260 prompt "Physical address space size"
1261 default ARM64_PA_BITS_48
1263 Choose the maximum physical address range that the kernel will
1266 config ARM64_PA_BITS_48
1269 config ARM64_PA_BITS_52
1270 bool "52-bit (ARMv8.2)"
1271 depends on ARM64_64K_PAGES
1272 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1274 Enable support for a 52-bit physical address space, introduced as
1275 part of the ARMv8.2-LPA extension.
1277 With this enabled, the kernel will also continue to work on CPUs that
1278 do not support ARMv8.2-LPA, but with some added memory overhead (and
1279 minor performance overhead).
1283 config ARM64_PA_BITS
1285 default 48 if ARM64_PA_BITS_48
1286 default 52 if ARM64_PA_BITS_52
1290 default CPU_LITTLE_ENDIAN
1292 Select the endianness of data accesses performed by the CPU. Userspace
1293 applications will need to be compiled and linked for the endianness
1294 that is selected here.
1296 config CPU_BIG_ENDIAN
1297 bool "Build big-endian kernel"
1298 depends on !LD_IS_LLD || LLD_VERSION >= 130000
1300 Say Y if you plan on running a kernel with a big-endian userspace.
1302 config CPU_LITTLE_ENDIAN
1303 bool "Build little-endian kernel"
1305 Say Y if you plan on running a kernel with a little-endian userspace.
1306 This is usually the case for distributions targeting arm64.
1311 bool "Multi-core scheduler support"
1313 Multi-core scheduler support improves the CPU scheduler's decision
1314 making when dealing with multi-core CPU chips at a cost of slightly
1315 increased overhead in some places. If unsure say N here.
1317 config SCHED_CLUSTER
1318 bool "Cluster scheduler support"
1320 Cluster scheduler support improves the CPU scheduler's decision
1321 making when dealing with machines that have clusters of CPUs.
1322 Cluster usually means a couple of CPUs which are placed closely
1323 by sharing mid-level caches, last-level cache tags or internal
1327 bool "SMT scheduler support"
1329 Improves the CPU scheduler's decision making when dealing with
1330 MultiThreading at a cost of slightly increased overhead in some
1331 places. If unsure say N here.
1334 int "Maximum number of CPUs (2-4096)"
1339 bool "Support for hot-pluggable CPUs"
1340 select GENERIC_IRQ_MIGRATION
1342 Say Y here to experiment with turning CPUs off and on. CPUs
1343 can be controlled through /sys/devices/system/cpu.
1345 # Common NUMA Features
1347 bool "NUMA Memory Allocation and Scheduler Support"
1348 select GENERIC_ARCH_NUMA
1349 select ACPI_NUMA if ACPI
1351 select HAVE_SETUP_PER_CPU_AREA
1352 select NEED_PER_CPU_EMBED_FIRST_CHUNK
1353 select NEED_PER_CPU_PAGE_FIRST_CHUNK
1354 select USE_PERCPU_NUMA_NODE_ID
1356 Enable NUMA (Non-Uniform Memory Access) support.
1358 The kernel will try to allocate memory used by a CPU on the
1359 local memory of the CPU and add some more
1360 NUMA awareness to the kernel.
1363 int "Maximum NUMA Nodes (as a power of 2)"
1368 Specify the maximum number of NUMA Nodes available on the target
1369 system. Increases memory reserved to accommodate various tables.
1371 source "kernel/Kconfig.hz"
1373 config ARCH_SPARSEMEM_ENABLE
1375 select SPARSEMEM_VMEMMAP_ENABLE
1376 select SPARSEMEM_VMEMMAP
1378 config HW_PERF_EVENTS
1382 # Supported by clang >= 7.0 or GCC >= 12.0.0
1383 config CC_HAVE_SHADOW_CALL_STACK
1384 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1387 bool "Enable paravirtualization code"
1389 This changes the kernel so it can modify itself when it is run
1390 under a hypervisor, potentially improving performance significantly
1391 over full virtualization.
1393 config PARAVIRT_TIME_ACCOUNTING
1394 bool "Paravirtual steal time accounting"
1397 Select this option to enable fine granularity task steal time
1398 accounting. Time spent executing other tasks in parallel with
1399 the current vCPU is discounted from the vCPU power. To account for
1400 that, there can be a small performance impact.
1402 If in doubt, say N here.
1405 depends on PM_SLEEP_SMP
1407 bool "kexec system call"
1409 kexec is a system call that implements the ability to shutdown your
1410 current kernel, and to start another kernel. It is like a reboot
1411 but it is independent of the system firmware. And like a reboot
1412 you can start any kernel with it, not just Linux.
1415 bool "kexec file based system call"
1417 select HAVE_IMA_KEXEC if IMA
1419 This is new version of kexec system call. This system call is
1420 file based and takes file descriptors as system call argument
1421 for kernel and initramfs as opposed to list of segments as
1422 accepted by previous system call.
1425 bool "Verify kernel signature during kexec_file_load() syscall"
1426 depends on KEXEC_FILE
1428 Select this option to verify a signature with loaded kernel
1429 image. If configured, any attempt of loading a image without
1430 valid signature will fail.
1432 In addition to that option, you need to enable signature
1433 verification for the corresponding kernel image type being
1434 loaded in order for this to work.
1436 config KEXEC_IMAGE_VERIFY_SIG
1437 bool "Enable Image signature verification support"
1439 depends on KEXEC_SIG
1440 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1442 Enable Image signature verification support.
1444 comment "Support for PE file signature verification disabled"
1445 depends on KEXEC_SIG
1446 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1449 bool "Build kdump crash kernel"
1451 Generate crash dump after being started by kexec. This should
1452 be normally only set in special crash dump kernels which are
1453 loaded in the main kernel with kexec-tools into a specially
1454 reserved region and then later executed after a crash by
1457 For more details see Documentation/admin-guide/kdump/kdump.rst
1461 depends on HIBERNATION || KEXEC_CORE
1468 bool "Xen guest support on ARM64"
1469 depends on ARM64 && OF
1473 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1475 config ARCH_FORCE_MAX_ORDER
1477 default "14" if ARM64_64K_PAGES
1478 default "12" if ARM64_16K_PAGES
1481 The kernel memory allocator divides physically contiguous memory
1482 blocks into "zones", where each zone is a power of two number of
1483 pages. This option selects the largest power of two that the kernel
1484 keeps in the memory allocator. If you need to allocate very large
1485 blocks of physically contiguous memory, then you may need to
1486 increase this value.
1488 This config option is actually maximum order plus one. For example,
1489 a value of 11 means that the largest free memory block is 2^10 pages.
1491 We make sure that we can allocate upto a HugePage size for each configuration.
1493 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1495 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1496 4M allocations matching the default size used by generic code.
1498 config UNMAP_KERNEL_AT_EL0
1499 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1502 Speculation attacks against some high-performance processors can
1503 be used to bypass MMU permission checks and leak kernel data to
1504 userspace. This can be defended against by unmapping the kernel
1505 when running in userspace, mapping it back in on exception entry
1506 via a trampoline page in the vector table.
1510 config MITIGATE_SPECTRE_BRANCH_HISTORY
1511 bool "Mitigate Spectre style attacks against branch history" if EXPERT
1514 Speculation attacks against some high-performance processors can
1515 make use of branch history to influence future speculation.
1516 When taking an exception from user-space, a sequence of branches
1517 or a firmware call overwrites the branch history.
1519 config RODATA_FULL_DEFAULT_ENABLED
1520 bool "Apply r/o permissions of VM areas also to their linear aliases"
1523 Apply read-only attributes of VM areas to the linear alias of
1524 the backing pages as well. This prevents code or read-only data
1525 from being modified (inadvertently or intentionally) via another
1526 mapping of the same memory page. This additional enhancement can
1527 be turned off at runtime by passing rodata=[off|on] (and turned on
1528 with rodata=full if this option is set to 'n')
1530 This requires the linear region to be mapped down to pages,
1531 which may adversely affect performance in some cases.
1533 config ARM64_SW_TTBR0_PAN
1534 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1536 Enabling this option prevents the kernel from accessing
1537 user-space memory directly by pointing TTBR0_EL1 to a reserved
1538 zeroed area and reserved ASID. The user access routines
1539 restore the valid TTBR0_EL1 temporarily.
1541 config ARM64_TAGGED_ADDR_ABI
1542 bool "Enable the tagged user addresses syscall ABI"
1545 When this option is enabled, user applications can opt in to a
1546 relaxed ABI via prctl() allowing tagged addresses to be passed
1547 to system calls as pointer arguments. For details, see
1548 Documentation/arm64/tagged-address-abi.rst.
1551 bool "Kernel support for 32-bit EL0"
1552 depends on ARM64_4K_PAGES || EXPERT
1554 select OLD_SIGSUSPEND3
1555 select COMPAT_OLD_SIGACTION
1557 This option enables support for a 32-bit EL0 running under a 64-bit
1558 kernel at EL1. AArch32-specific components such as system calls,
1559 the user helper functions, VFP support and the ptrace interface are
1560 handled appropriately by the kernel.
1562 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1563 that you will only be able to execute AArch32 binaries that were compiled
1564 with page size aligned segments.
1566 If you want to execute 32-bit userspace applications, say Y.
1570 config KUSER_HELPERS
1571 bool "Enable kuser helpers page for 32-bit applications"
1574 Warning: disabling this option may break 32-bit user programs.
1576 Provide kuser helpers to compat tasks. The kernel provides
1577 helper code to userspace in read only form at a fixed location
1578 to allow userspace to be independent of the CPU type fitted to
1579 the system. This permits binaries to be run on ARMv4 through
1580 to ARMv8 without modification.
1582 See Documentation/arm/kernel_user_helpers.rst for details.
1584 However, the fixed address nature of these helpers can be used
1585 by ROP (return orientated programming) authors when creating
1588 If all of the binaries and libraries which run on your platform
1589 are built specifically for your platform, and make no use of
1590 these helpers, then you can turn this option off to hinder
1591 such exploits. However, in that case, if a binary or library
1592 relying on those helpers is run, it will not function correctly.
1594 Say N here only if you are absolutely certain that you do not
1595 need these helpers; otherwise, the safe option is to say Y.
1598 bool "Enable vDSO for 32-bit applications"
1599 depends on !CPU_BIG_ENDIAN
1600 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1601 select GENERIC_COMPAT_VDSO
1604 Place in the process address space of 32-bit applications an
1605 ELF shared object providing fast implementations of gettimeofday
1608 You must have a 32-bit build of glibc 2.22 or later for programs
1609 to seamlessly take advantage of this.
1611 config THUMB2_COMPAT_VDSO
1612 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1613 depends on COMPAT_VDSO
1616 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1617 otherwise with '-marm'.
1619 config COMPAT_ALIGNMENT_FIXUPS
1620 bool "Fix up misaligned multi-word loads and stores in user space"
1622 menuconfig ARMV8_DEPRECATED
1623 bool "Emulate deprecated/obsolete ARMv8 instructions"
1626 Legacy software support may require certain instructions
1627 that have been deprecated or obsoleted in the architecture.
1629 Enable this config to enable selective emulation of these
1636 config SWP_EMULATION
1637 bool "Emulate SWP/SWPB instructions"
1639 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1640 they are always undefined. Say Y here to enable software
1641 emulation of these instructions for userspace using LDXR/STXR.
1642 This feature can be controlled at runtime with the abi.swp
1643 sysctl which is disabled by default.
1645 In some older versions of glibc [<=2.8] SWP is used during futex
1646 trylock() operations with the assumption that the code will not
1647 be preempted. This invalid assumption may be more likely to fail
1648 with SWP emulation enabled, leading to deadlock of the user
1651 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1652 on an external transaction monitoring block called a global
1653 monitor to maintain update atomicity. If your system does not
1654 implement a global monitor, this option can cause programs that
1655 perform SWP operations to uncached memory to deadlock.
1659 config CP15_BARRIER_EMULATION
1660 bool "Emulate CP15 Barrier instructions"
1662 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1663 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1664 strongly recommended to use the ISB, DSB, and DMB
1665 instructions instead.
1667 Say Y here to enable software emulation of these
1668 instructions for AArch32 userspace code. When this option is
1669 enabled, CP15 barrier usage is traced which can help
1670 identify software that needs updating. This feature can be
1671 controlled at runtime with the abi.cp15_barrier sysctl.
1675 config SETEND_EMULATION
1676 bool "Emulate SETEND instruction"
1678 The SETEND instruction alters the data-endianness of the
1679 AArch32 EL0, and is deprecated in ARMv8.
1681 Say Y here to enable software emulation of the instruction
1682 for AArch32 userspace code. This feature can be controlled
1683 at runtime with the abi.setend sysctl.
1685 Note: All the cpus on the system must have mixed endian support at EL0
1686 for this feature to be enabled. If a new CPU - which doesn't support mixed
1687 endian - is hotplugged in after this feature has been enabled, there could
1688 be unexpected results in the applications.
1691 endif # ARMV8_DEPRECATED
1695 menu "ARMv8.1 architectural features"
1697 config ARM64_HW_AFDBM
1698 bool "Support for hardware updates of the Access and Dirty page flags"
1701 The ARMv8.1 architecture extensions introduce support for
1702 hardware updates of the access and dirty information in page
1703 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1704 capable processors, accesses to pages with PTE_AF cleared will
1705 set this bit instead of raising an access flag fault.
1706 Similarly, writes to read-only pages with the DBM bit set will
1707 clear the read-only bit (AP[2]) instead of raising a
1710 Kernels built with this configuration option enabled continue
1711 to work on pre-ARMv8.1 hardware and the performance impact is
1712 minimal. If unsure, say Y.
1715 bool "Enable support for Privileged Access Never (PAN)"
1718 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1719 prevents the kernel or hypervisor from accessing user-space (EL0)
1722 Choosing this option will cause any unprotected (not using
1723 copy_to_user et al) memory access to fail with a permission fault.
1725 The feature is detected at runtime, and will remain as a 'nop'
1726 instruction if the cpu does not implement the feature.
1729 def_bool $(as-instr,.arch_extension rcpc)
1731 config AS_HAS_LSE_ATOMICS
1732 def_bool $(as-instr,.arch_extension lse)
1734 config ARM64_LSE_ATOMICS
1736 default ARM64_USE_LSE_ATOMICS
1737 depends on AS_HAS_LSE_ATOMICS
1739 config ARM64_USE_LSE_ATOMICS
1740 bool "Atomic instructions"
1743 As part of the Large System Extensions, ARMv8.1 introduces new
1744 atomic instructions that are designed specifically to scale in
1747 Say Y here to make use of these instructions for the in-kernel
1748 atomic routines. This incurs a small overhead on CPUs that do
1749 not support these instructions and requires the kernel to be
1750 built with binutils >= 2.25 in order for the new instructions
1753 endmenu # "ARMv8.1 architectural features"
1755 menu "ARMv8.2 architectural features"
1757 config AS_HAS_ARMV8_2
1758 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1761 def_bool $(as-instr,.arch armv8.2-a+sha3)
1764 bool "Enable support for persistent memory"
1765 select ARCH_HAS_PMEM_API
1766 select ARCH_HAS_UACCESS_FLUSHCACHE
1768 Say Y to enable support for the persistent memory API based on the
1769 ARMv8.2 DCPoP feature.
1771 The feature is detected at runtime, and the kernel will use DC CVAC
1772 operations if DC CVAP is not supported (following the behaviour of
1773 DC CVAP itself if the system does not define a point of persistence).
1775 config ARM64_RAS_EXTN
1776 bool "Enable support for RAS CPU Extensions"
1779 CPUs that support the Reliability, Availability and Serviceability
1780 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1781 errors, classify them and report them to software.
1783 On CPUs with these extensions system software can use additional
1784 barriers to determine if faults are pending and read the
1785 classification from a new set of registers.
1787 Selecting this feature will allow the kernel to use these barriers
1788 and access the new registers if the system supports the extension.
1789 Platform RAS features may additionally depend on firmware support.
1792 bool "Enable support for Common Not Private (CNP) translations"
1794 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1796 Common Not Private (CNP) allows translation table entries to
1797 be shared between different PEs in the same inner shareable
1798 domain, so the hardware can use this fact to optimise the
1799 caching of such entries in the TLB.
1801 Selecting this option allows the CNP feature to be detected
1802 at runtime, and does not affect PEs that do not implement
1805 endmenu # "ARMv8.2 architectural features"
1807 menu "ARMv8.3 architectural features"
1809 config ARM64_PTR_AUTH
1810 bool "Enable support for pointer authentication"
1813 Pointer authentication (part of the ARMv8.3 Extensions) provides
1814 instructions for signing and authenticating pointers against secret
1815 keys, which can be used to mitigate Return Oriented Programming (ROP)
1818 This option enables these instructions at EL0 (i.e. for userspace).
1819 Choosing this option will cause the kernel to initialise secret keys
1820 for each process at exec() time, with these keys being
1821 context-switched along with the process.
1823 The feature is detected at runtime. If the feature is not present in
1824 hardware it will not be advertised to userspace/KVM guest nor will it
1827 If the feature is present on the boot CPU but not on a late CPU, then
1828 the late CPU will be parked. Also, if the boot CPU does not have
1829 address auth and the late CPU has then the late CPU will still boot
1830 but with the feature disabled. On such a system, this option should
1833 config ARM64_PTR_AUTH_KERNEL
1834 bool "Use pointer authentication for kernel"
1836 depends on ARM64_PTR_AUTH
1837 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1838 # Modern compilers insert a .note.gnu.property section note for PAC
1839 # which is only understood by binutils starting with version 2.33.1.
1840 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1841 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1842 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
1844 If the compiler supports the -mbranch-protection or
1845 -msign-return-address flag (e.g. GCC 7 or later), then this option
1846 will cause the kernel itself to be compiled with return address
1847 protection. In this case, and if the target hardware is known to
1848 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1849 disabled with minimal loss of protection.
1851 This feature works with FUNCTION_GRAPH_TRACER option only if
1852 DYNAMIC_FTRACE_WITH_ARGS is enabled.
1854 config CC_HAS_BRANCH_PROT_PAC_RET
1855 # GCC 9 or later, clang 8 or later
1856 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1858 config CC_HAS_SIGN_RETURN_ADDRESS
1860 def_bool $(cc-option,-msign-return-address=all)
1863 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1865 config AS_HAS_CFI_NEGATE_RA_STATE
1866 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1868 endmenu # "ARMv8.3 architectural features"
1870 menu "ARMv8.4 architectural features"
1872 config ARM64_AMU_EXTN
1873 bool "Enable support for the Activity Monitors Unit CPU extension"
1876 The activity monitors extension is an optional extension introduced
1877 by the ARMv8.4 CPU architecture. This enables support for version 1
1878 of the activity monitors architecture, AMUv1.
1880 To enable the use of this extension on CPUs that implement it, say Y.
1882 Note that for architectural reasons, firmware _must_ implement AMU
1883 support when running on CPUs that present the activity monitors
1884 extension. The required support is present in:
1885 * Version 1.5 and later of the ARM Trusted Firmware
1887 For kernels that have this configuration enabled but boot with broken
1888 firmware, you may need to say N here until the firmware is fixed.
1889 Otherwise you may experience firmware panics or lockups when
1890 accessing the counter registers. Even if you are not observing these
1891 symptoms, the values returned by the register reads might not
1892 correctly reflect reality. Most commonly, the value read will be 0,
1893 indicating that the counter is not enabled.
1895 config AS_HAS_ARMV8_4
1896 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1898 config ARM64_TLB_RANGE
1899 bool "Enable support for tlbi range feature"
1901 depends on AS_HAS_ARMV8_4
1903 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1904 range of input addresses.
1906 The feature introduces new assembly instructions, and they were
1907 support when binutils >= 2.30.
1909 endmenu # "ARMv8.4 architectural features"
1911 menu "ARMv8.5 architectural features"
1913 config AS_HAS_ARMV8_5
1914 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1917 bool "Branch Target Identification support"
1920 Branch Target Identification (part of the ARMv8.5 Extensions)
1921 provides a mechanism to limit the set of locations to which computed
1922 branch instructions such as BR or BLR can jump.
1924 To make use of BTI on CPUs that support it, say Y.
1926 BTI is intended to provide complementary protection to other control
1927 flow integrity protection mechanisms, such as the Pointer
1928 authentication mechanism provided as part of the ARMv8.3 Extensions.
1929 For this reason, it does not make sense to enable this option without
1930 also enabling support for pointer authentication. Thus, when
1931 enabling this option you should also select ARM64_PTR_AUTH=y.
1933 Userspace binaries must also be specifically compiled to make use of
1934 this mechanism. If you say N here or the hardware does not support
1935 BTI, such binaries can still run, but you get no additional
1936 enforcement of branch destinations.
1938 config ARM64_BTI_KERNEL
1939 bool "Use Branch Target Identification for kernel"
1941 depends on ARM64_BTI
1942 depends on ARM64_PTR_AUTH_KERNEL
1943 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1944 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1945 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1946 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671
1947 depends on !CC_IS_GCC
1948 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1949 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
1950 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
1952 Build the kernel with Branch Target Identification annotations
1953 and enable enforcement of this for kernel code. When this option
1954 is enabled and the system supports BTI all kernel code including
1955 modular code must have BTI enabled.
1957 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1958 # GCC 9 or later, clang 8 or later
1959 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1962 bool "Enable support for E0PD"
1965 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1966 that EL0 accesses made via TTBR1 always fault in constant time,
1967 providing similar benefits to KASLR as those provided by KPTI, but
1968 with lower overhead and without disrupting legitimate access to
1969 kernel memory such as SPE.
1971 This option enables E0PD for TTBR1 where available.
1973 config ARM64_AS_HAS_MTE
1974 # Initial support for MTE went in binutils 2.32.0, checked with
1975 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1976 # as a late addition to the final architecture spec (LDGM/STGM)
1977 # is only supported in the newer 2.32.x and 2.33 binutils
1978 # versions, hence the extra "stgm" instruction check below.
1979 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1982 bool "Memory Tagging Extension support"
1984 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1985 depends on AS_HAS_ARMV8_5
1986 depends on AS_HAS_LSE_ATOMICS
1987 # Required for tag checking in the uaccess routines
1988 depends on ARM64_PAN
1989 select ARCH_HAS_SUBPAGE_FAULTS
1990 select ARCH_USES_HIGH_VMA_FLAGS
1992 Memory Tagging (part of the ARMv8.5 Extensions) provides
1993 architectural support for run-time, always-on detection of
1994 various classes of memory error to aid with software debugging
1995 to eliminate vulnerabilities arising from memory-unsafe
1998 This option enables the support for the Memory Tagging
1999 Extension at EL0 (i.e. for userspace).
2001 Selecting this option allows the feature to be detected at
2002 runtime. Any secondary CPU not implementing this feature will
2003 not be allowed a late bring-up.
2005 Userspace binaries that want to use this feature must
2006 explicitly opt in. The mechanism for the userspace is
2009 Documentation/arm64/memory-tagging-extension.rst.
2011 endmenu # "ARMv8.5 architectural features"
2013 menu "ARMv8.7 architectural features"
2016 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
2018 depends on ARM64_PAN
2020 Enhanced Privileged Access Never (EPAN) allows Privileged
2021 Access Never to be used with Execute-only mappings.
2023 The feature is detected at runtime, and will remain disabled
2024 if the cpu does not implement the feature.
2025 endmenu # "ARMv8.7 architectural features"
2028 bool "ARM Scalable Vector Extension support"
2031 The Scalable Vector Extension (SVE) is an extension to the AArch64
2032 execution state which complements and extends the SIMD functionality
2033 of the base architecture to support much larger vectors and to enable
2034 additional vectorisation opportunities.
2036 To enable use of this extension on CPUs that implement it, say Y.
2038 On CPUs that support the SVE2 extensions, this option will enable
2041 Note that for architectural reasons, firmware _must_ implement SVE
2042 support when running on SVE capable hardware. The required support
2045 * version 1.5 and later of the ARM Trusted Firmware
2046 * the AArch64 boot wrapper since commit 5e1261e08abf
2047 ("bootwrapper: SVE: Enable SVE for EL2 and below").
2049 For other firmware implementations, consult the firmware documentation
2052 If you need the kernel to boot on SVE-capable hardware with broken
2053 firmware, you may need to say N here until you get your firmware
2054 fixed. Otherwise, you may experience firmware panics or lockups when
2055 booting the kernel. If unsure and you are not observing these
2056 symptoms, you should assume that it is safe to say Y.
2059 bool "ARM Scalable Matrix Extension support"
2061 depends on ARM64_SVE
2063 The Scalable Matrix Extension (SME) is an extension to the AArch64
2064 execution state which utilises a substantial subset of the SVE
2065 instruction set, together with the addition of new architectural
2066 register state capable of holding two dimensional matrix tiles to
2067 enable various matrix operations.
2069 config ARM64_MODULE_PLTS
2070 bool "Use PLTs to allow module memory to spill over into vmalloc area"
2072 select HAVE_MOD_ARCH_SPECIFIC
2074 Allocate PLTs when loading modules so that jumps and calls whose
2075 targets are too far away for their relative offsets to be encoded
2076 in the instructions themselves can be bounced via veneers in the
2077 module's PLT. This allows modules to be allocated in the generic
2078 vmalloc area after the dedicated module memory area has been
2081 When running with address space randomization (KASLR), the module
2082 region itself may be too far away for ordinary relative jumps and
2083 calls, and so in that case, module PLTs are required and cannot be
2086 Specific errata workaround(s) might also force module PLTs to be
2087 enabled (ARM64_ERRATUM_843419).
2089 config ARM64_PSEUDO_NMI
2090 bool "Support for NMI-like interrupts"
2093 Adds support for mimicking Non-Maskable Interrupts through the use of
2094 GIC interrupt priority. This support requires version 3 or later of
2097 This high priority configuration for interrupts needs to be
2098 explicitly enabled by setting the kernel parameter
2099 "irqchip.gicv3_pseudo_nmi" to 1.
2104 config ARM64_DEBUG_PRIORITY_MASKING
2105 bool "Debug interrupt priority masking"
2107 This adds runtime checks to functions enabling/disabling
2108 interrupts when using priority masking. The additional checks verify
2109 the validity of ICC_PMR_EL1 when calling concerned functions.
2112 endif # ARM64_PSEUDO_NMI
2115 bool "Build a relocatable kernel image" if EXPERT
2116 select ARCH_HAS_RELR
2119 This builds the kernel as a Position Independent Executable (PIE),
2120 which retains all relocation metadata required to relocate the
2121 kernel binary at runtime to a different virtual address than the
2122 address it was linked at.
2123 Since AArch64 uses the RELA relocation format, this requires a
2124 relocation pass at runtime even if the kernel is loaded at the
2125 same address it was linked at.
2127 config RANDOMIZE_BASE
2128 bool "Randomize the address of the kernel image"
2129 select ARM64_MODULE_PLTS if MODULES
2132 Randomizes the virtual address at which the kernel image is
2133 loaded, as a security feature that deters exploit attempts
2134 relying on knowledge of the location of kernel internals.
2136 It is the bootloader's job to provide entropy, by passing a
2137 random u64 value in /chosen/kaslr-seed at kernel entry.
2139 When booting via the UEFI stub, it will invoke the firmware's
2140 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
2141 to the kernel proper. In addition, it will randomise the physical
2142 location of the kernel Image as well.
2146 config RANDOMIZE_MODULE_REGION_FULL
2147 bool "Randomize the module region over a 2 GB range"
2148 depends on RANDOMIZE_BASE
2151 Randomizes the location of the module region inside a 2 GB window
2152 covering the core kernel. This way, it is less likely for modules
2153 to leak information about the location of core kernel data structures
2154 but it does imply that function calls between modules and the core
2155 kernel will need to be resolved via veneers in the module PLT.
2157 When this option is not set, the module region will be randomized over
2158 a limited range that contains the [_stext, _etext] interval of the
2159 core kernel, so branch relocations are almost always in range unless
2160 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this
2161 particular case of region exhaustion, modules might be able to fall
2162 back to a larger 2GB area.
2164 config CC_HAVE_STACKPROTECTOR_SYSREG
2165 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
2167 config STACKPROTECTOR_PER_TASK
2169 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
2171 # The GPIO number here must be sorted by descending number. In case of
2172 # a multiplatform kernel, we just want the highest value required by the
2173 # selected platforms.
2176 default 2048 if ARCH_APPLE
2179 Maximum number of GPIOs in the system.
2181 If unsure, leave the default value.
2183 config UNWIND_PATCH_PAC_INTO_SCS
2184 bool "Enable shadow call stack dynamically using code patching"
2185 # needs Clang with https://reviews.llvm.org/D111780 incorporated
2186 depends on CC_IS_CLANG && CLANG_VERSION >= 150000
2187 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET
2188 depends on SHADOW_CALL_STACK
2189 select UNWIND_TABLES
2192 endmenu # "Kernel Features"
2196 config ARM64_ACPI_PARKING_PROTOCOL
2197 bool "Enable support for the ARM64 ACPI parking protocol"
2200 Enable support for the ARM64 ACPI parking protocol. If disabled
2201 the kernel will not allow booting through the ARM64 ACPI parking
2202 protocol even if the corresponding data is present in the ACPI
2206 string "Default kernel command string"
2209 Provide a set of default command-line options at build time by
2210 entering them here. As a minimum, you should specify the the
2211 root device (e.g. root=/dev/nfs).
2214 prompt "Kernel command line type" if CMDLINE != ""
2215 default CMDLINE_FROM_BOOTLOADER
2217 Choose how the kernel will handle the provided default kernel
2218 command line string.
2220 config CMDLINE_FROM_BOOTLOADER
2221 bool "Use bootloader kernel arguments if available"
2223 Uses the command-line options passed by the boot loader. If
2224 the boot loader doesn't provide any, the default kernel command
2225 string provided in CMDLINE will be used.
2227 config CMDLINE_FORCE
2228 bool "Always use the default kernel command string"
2230 Always use the default kernel command string, even if the boot
2231 loader passes other arguments to the kernel.
2232 This is useful if you cannot or don't want to change the
2233 command-line options your boot loader passes to the kernel.
2241 bool "UEFI runtime support"
2242 depends on OF && !CPU_BIG_ENDIAN
2243 depends on KERNEL_MODE_NEON
2244 select ARCH_SUPPORTS_ACPI
2247 select EFI_PARAMS_FROM_FDT
2248 select EFI_RUNTIME_WRAPPERS
2250 select EFI_GENERIC_STUB
2251 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
2254 This option provides support for runtime services provided
2255 by UEFI firmware (such as non-volatile variables, realtime
2256 clock, and platform reset). A UEFI stub is also provided to
2257 allow the kernel to be booted as an EFI application. This
2258 is only useful on systems that have UEFI firmware.
2261 bool "Enable support for SMBIOS (DMI) tables"
2265 This enables SMBIOS/DMI feature for systems.
2267 This option is only useful on systems that have UEFI firmware.
2268 However, even with this option, the resultant kernel should
2269 continue to boot on existing non-UEFI platforms.
2271 endmenu # "Boot options"
2273 menu "Power management options"
2275 source "kernel/power/Kconfig"
2277 config ARCH_HIBERNATION_POSSIBLE
2281 config ARCH_HIBERNATION_HEADER
2283 depends on HIBERNATION
2285 config ARCH_SUSPEND_POSSIBLE
2288 endmenu # "Power management options"
2290 menu "CPU Power Management"
2292 source "drivers/cpuidle/Kconfig"
2294 source "drivers/cpufreq/Kconfig"
2296 endmenu # "CPU Power Management"
2298 source "drivers/acpi/Kconfig"
2300 source "arch/arm64/kvm/Kconfig"