1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_WX
13 select ARCH_BINFMT_ELF_EXTRA_PHDRS
14 select ARCH_BINFMT_ELF_STATE
15 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE
16 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
17 select ARCH_ENABLE_MEMORY_HOTPLUG
18 select ARCH_ENABLE_MEMORY_HOTREMOVE
19 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
20 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
21 select ARCH_HAS_CACHE_LINE_SIZE
22 select ARCH_HAS_CURRENT_STACK_POINTER
23 select ARCH_HAS_DEBUG_VIRTUAL
24 select ARCH_HAS_DEBUG_VM_PGTABLE
25 select ARCH_HAS_DMA_PREP_COHERENT
26 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
27 select ARCH_HAS_FAST_MULTIPLIER
28 select ARCH_HAS_FORTIFY_SOURCE
29 select ARCH_HAS_GCOV_PROFILE_ALL
30 select ARCH_HAS_GIGANTIC_PAGE
32 select ARCH_HAS_KEEPINITRD
33 select ARCH_HAS_MEMBARRIER_SYNC_CORE
34 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
35 select ARCH_HAS_PTE_DEVMAP
36 select ARCH_HAS_PTE_SPECIAL
37 select ARCH_HAS_SETUP_DMA_OPS
38 select ARCH_HAS_SET_DIRECT_MAP
39 select ARCH_HAS_SET_MEMORY
41 select ARCH_HAS_STRICT_KERNEL_RWX
42 select ARCH_HAS_STRICT_MODULE_RWX
43 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
44 select ARCH_HAS_SYNC_DMA_FOR_CPU
45 select ARCH_HAS_SYSCALL_WRAPPER
46 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
47 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
48 select ARCH_HAS_ZONE_DMA_SET if EXPERT
49 select ARCH_HAVE_ELF_PROT
50 select ARCH_HAVE_NMI_SAFE_CMPXCHG
51 select ARCH_INLINE_READ_LOCK if !PREEMPTION
52 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
53 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
54 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
55 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
56 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
57 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
58 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
59 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
60 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
61 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
62 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
63 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
64 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
65 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
66 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
67 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
68 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
69 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
70 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
71 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
72 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
73 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
74 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
75 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
76 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
77 select ARCH_KEEP_MEMBLOCK
78 select ARCH_USE_CMPXCHG_LOCKREF
79 select ARCH_USE_GNU_PROPERTY
80 select ARCH_USE_MEMTEST
81 select ARCH_USE_QUEUED_RWLOCKS
82 select ARCH_USE_QUEUED_SPINLOCKS
83 select ARCH_USE_SYM_ANNOTATIONS
84 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
85 select ARCH_SUPPORTS_HUGETLBFS
86 select ARCH_SUPPORTS_MEMORY_FAILURE
87 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
88 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
89 select ARCH_SUPPORTS_LTO_CLANG_THIN
90 select ARCH_SUPPORTS_CFI_CLANG
91 select ARCH_SUPPORTS_ATOMIC_RMW
92 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
93 select ARCH_SUPPORTS_NUMA_BALANCING
94 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
95 select ARCH_WANT_DEFAULT_BPF_JIT
96 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
97 select ARCH_WANT_FRAME_POINTERS
98 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
99 select ARCH_WANT_LD_ORPHAN_WARN
100 select ARCH_WANTS_NO_INSTR
101 select ARCH_HAS_UBSAN_SANITIZE_ALL
103 select ARM_ARCH_TIMER
105 select AUDIT_ARCH_COMPAT_GENERIC
106 select ARM_GIC_V2M if PCI
108 select ARM_GIC_V3_ITS if PCI
110 select BUILDTIME_TABLE_SORT
111 select CLONE_BACKWARDS
113 select CPU_PM if (SUSPEND || CPU_IDLE)
115 select DCACHE_WORD_ACCESS
116 select DMA_DIRECT_REMAP
119 select GENERIC_ALLOCATOR
120 select GENERIC_ARCH_TOPOLOGY
121 select GENERIC_CLOCKEVENTS_BROADCAST
122 select GENERIC_CPU_AUTOPROBE
123 select GENERIC_CPU_VULNERABILITIES
124 select GENERIC_EARLY_IOREMAP
125 select GENERIC_IDLE_POLL_SETUP
126 select GENERIC_IRQ_IPI
127 select GENERIC_IRQ_PROBE
128 select GENERIC_IRQ_SHOW
129 select GENERIC_IRQ_SHOW_LEVEL
130 select GENERIC_LIB_DEVMEM_IS_ALLOWED
131 select GENERIC_PCI_IOMAP
132 select GENERIC_PTDUMP
133 select GENERIC_SCHED_CLOCK
134 select GENERIC_SMP_IDLE_THREAD
135 select GENERIC_TIME_VSYSCALL
136 select GENERIC_GETTIMEOFDAY
137 select GENERIC_VDSO_TIME_NS
138 select HARDIRQS_SW_RESEND
142 select HAVE_ACPI_APEI if (ACPI && EFI)
143 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
144 select HAVE_ARCH_AUDITSYSCALL
145 select HAVE_ARCH_BITREVERSE
146 select HAVE_ARCH_COMPILER_H
147 select HAVE_ARCH_HUGE_VMAP
148 select HAVE_ARCH_JUMP_LABEL
149 select HAVE_ARCH_JUMP_LABEL_RELATIVE
150 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
151 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
152 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
153 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
154 # Some instrumentation may be unsound, hence EXPERT
155 select HAVE_ARCH_KCSAN if EXPERT
156 select HAVE_ARCH_KFENCE
157 select HAVE_ARCH_KGDB
158 select HAVE_ARCH_MMAP_RND_BITS
159 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
160 select HAVE_ARCH_PREL32_RELOCATIONS
161 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
162 select HAVE_ARCH_SECCOMP_FILTER
163 select HAVE_ARCH_STACKLEAK
164 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
165 select HAVE_ARCH_TRACEHOOK
166 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
167 select HAVE_ARCH_VMAP_STACK
168 select HAVE_ARM_SMCCC
169 select HAVE_ASM_MODVERSIONS
171 select HAVE_C_RECORDMCOUNT
172 select HAVE_CMPXCHG_DOUBLE
173 select HAVE_CMPXCHG_LOCAL
174 select HAVE_CONTEXT_TRACKING
175 select HAVE_DEBUG_KMEMLEAK
176 select HAVE_DMA_CONTIGUOUS
177 select HAVE_DYNAMIC_FTRACE
178 select HAVE_DYNAMIC_FTRACE_WITH_REGS \
179 if $(cc-option,-fpatchable-function-entry=2)
180 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
181 if DYNAMIC_FTRACE_WITH_REGS
182 select HAVE_EFFICIENT_UNALIGNED_ACCESS
184 select HAVE_FTRACE_MCOUNT_RECORD
185 select HAVE_FUNCTION_TRACER
186 select HAVE_FUNCTION_ERROR_INJECTION
187 select HAVE_FUNCTION_GRAPH_TRACER
188 select HAVE_GCC_PLUGINS
189 select HAVE_HW_BREAKPOINT if PERF_EVENTS
190 select HAVE_IRQ_TIME_ACCOUNTING
193 select HAVE_PATA_PLATFORM
194 select HAVE_PERF_EVENTS
195 select HAVE_PERF_REGS
196 select HAVE_PERF_USER_STACK_DUMP
197 select HAVE_REGS_AND_STACK_ACCESS_API
198 select HAVE_POSIX_CPU_TIMERS_TASK_WORK
199 select HAVE_FUNCTION_ARG_ACCESS_API
200 select MMU_GATHER_RCU_TABLE_FREE
202 select HAVE_STACKPROTECTOR
203 select HAVE_SYSCALL_TRACEPOINTS
205 select HAVE_KRETPROBES
206 select HAVE_GENERIC_VDSO
207 select IOMMU_DMA if IOMMU_SUPPORT
209 select IRQ_FORCED_THREADING
210 select KASAN_VMALLOC if KASAN_GENERIC
211 select MODULES_USE_ELF_RELA
212 select NEED_DMA_MAP_STATE
213 select NEED_SG_DMA_LENGTH
215 select OF_EARLY_FLATTREE
216 select PCI_DOMAINS_GENERIC if PCI
217 select PCI_ECAM if (ACPI && PCI)
218 select PCI_SYSCALL if PCI
223 select SYSCTL_EXCEPTION_TRACE
224 select THREAD_INFO_IN_TASK
225 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
226 select TRACE_IRQFLAGS_SUPPORT
228 ARM 64-bit (AArch64) Linux support.
236 config ARM64_PAGE_SHIFT
238 default 16 if ARM64_64K_PAGES
239 default 14 if ARM64_16K_PAGES
242 config ARM64_CONT_PTE_SHIFT
244 default 5 if ARM64_64K_PAGES
245 default 7 if ARM64_16K_PAGES
248 config ARM64_CONT_PMD_SHIFT
250 default 5 if ARM64_64K_PAGES
251 default 5 if ARM64_16K_PAGES
254 config ARCH_MMAP_RND_BITS_MIN
255 default 14 if ARM64_64K_PAGES
256 default 16 if ARM64_16K_PAGES
259 # max bits determined by the following formula:
260 # VA_BITS - PAGE_SHIFT - 3
261 config ARCH_MMAP_RND_BITS_MAX
262 default 19 if ARM64_VA_BITS=36
263 default 24 if ARM64_VA_BITS=39
264 default 27 if ARM64_VA_BITS=42
265 default 30 if ARM64_VA_BITS=47
266 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
267 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
268 default 33 if ARM64_VA_BITS=48
269 default 14 if ARM64_64K_PAGES
270 default 16 if ARM64_16K_PAGES
273 config ARCH_MMAP_RND_COMPAT_BITS_MIN
274 default 7 if ARM64_64K_PAGES
275 default 9 if ARM64_16K_PAGES
278 config ARCH_MMAP_RND_COMPAT_BITS_MAX
284 config STACKTRACE_SUPPORT
287 config ILLEGAL_POINTER_VALUE
289 default 0xdead000000000000
291 config LOCKDEP_SUPPORT
298 config GENERIC_BUG_RELATIVE_POINTERS
300 depends on GENERIC_BUG
302 config GENERIC_HWEIGHT
308 config GENERIC_CALIBRATE_DELAY
311 config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
317 config KERNEL_MODE_NEON
320 config FIX_EARLYCON_MEM
323 config PGTABLE_LEVELS
325 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
326 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
327 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
328 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
329 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
330 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
332 config ARCH_SUPPORTS_UPROBES
335 config ARCH_PROC_KCORE_TEXT
338 config BROKEN_GAS_INST
339 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
341 config KASAN_SHADOW_OFFSET
343 depends on KASAN_GENERIC || KASAN_SW_TAGS
344 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
345 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
346 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
347 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
348 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
349 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
350 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
351 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
352 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
353 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
354 default 0xffffffffffffffff
356 source "arch/arm64/Kconfig.platforms"
358 menu "Kernel Features"
360 menu "ARM errata workarounds via the alternatives framework"
362 config ARM64_WORKAROUND_CLEAN_CACHE
365 config ARM64_ERRATUM_826319
366 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
368 select ARM64_WORKAROUND_CLEAN_CACHE
370 This option adds an alternative code sequence to work around ARM
371 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
372 AXI master interface and an L2 cache.
374 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
375 and is unable to accept a certain write via this interface, it will
376 not progress on read data presented on the read data channel and the
379 The workaround promotes data cache clean instructions to
380 data cache clean-and-invalidate.
381 Please note that this does not necessarily enable the workaround,
382 as it depends on the alternative framework, which will only patch
383 the kernel if an affected CPU is detected.
387 config ARM64_ERRATUM_827319
388 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
390 select ARM64_WORKAROUND_CLEAN_CACHE
392 This option adds an alternative code sequence to work around ARM
393 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
394 master interface and an L2 cache.
396 Under certain conditions this erratum can cause a clean line eviction
397 to occur at the same time as another transaction to the same address
398 on the AMBA 5 CHI interface, which can cause data corruption if the
399 interconnect reorders the two transactions.
401 The workaround promotes data cache clean instructions to
402 data cache clean-and-invalidate.
403 Please note that this does not necessarily enable the workaround,
404 as it depends on the alternative framework, which will only patch
405 the kernel if an affected CPU is detected.
409 config ARM64_ERRATUM_824069
410 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
412 select ARM64_WORKAROUND_CLEAN_CACHE
414 This option adds an alternative code sequence to work around ARM
415 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
416 to a coherent interconnect.
418 If a Cortex-A53 processor is executing a store or prefetch for
419 write instruction at the same time as a processor in another
420 cluster is executing a cache maintenance operation to the same
421 address, then this erratum might cause a clean cache line to be
422 incorrectly marked as dirty.
424 The workaround promotes data cache clean instructions to
425 data cache clean-and-invalidate.
426 Please note that this option does not necessarily enable the
427 workaround, as it depends on the alternative framework, which will
428 only patch the kernel if an affected CPU is detected.
432 config ARM64_ERRATUM_819472
433 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
435 select ARM64_WORKAROUND_CLEAN_CACHE
437 This option adds an alternative code sequence to work around ARM
438 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
439 present when it is connected to a coherent interconnect.
441 If the processor is executing a load and store exclusive sequence at
442 the same time as a processor in another cluster is executing a cache
443 maintenance operation to the same address, then this erratum might
444 cause data corruption.
446 The workaround promotes data cache clean instructions to
447 data cache clean-and-invalidate.
448 Please note that this does not necessarily enable the workaround,
449 as it depends on the alternative framework, which will only patch
450 the kernel if an affected CPU is detected.
454 config ARM64_ERRATUM_832075
455 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
458 This option adds an alternative code sequence to work around ARM
459 erratum 832075 on Cortex-A57 parts up to r1p2.
461 Affected Cortex-A57 parts might deadlock when exclusive load/store
462 instructions to Write-Back memory are mixed with Device loads.
464 The workaround is to promote device loads to use Load-Acquire
466 Please note that this does not necessarily enable the workaround,
467 as it depends on the alternative framework, which will only patch
468 the kernel if an affected CPU is detected.
472 config ARM64_ERRATUM_834220
473 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
477 This option adds an alternative code sequence to work around ARM
478 erratum 834220 on Cortex-A57 parts up to r1p2.
480 Affected Cortex-A57 parts might report a Stage 2 translation
481 fault as the result of a Stage 1 fault for load crossing a
482 page boundary when there is a permission or device memory
483 alignment fault at Stage 1 and a translation fault at Stage 2.
485 The workaround is to verify that the Stage 1 translation
486 doesn't generate a fault before handling the Stage 2 fault.
487 Please note that this does not necessarily enable the workaround,
488 as it depends on the alternative framework, which will only patch
489 the kernel if an affected CPU is detected.
493 config ARM64_ERRATUM_845719
494 bool "Cortex-A53: 845719: a load might read incorrect data"
498 This option adds an alternative code sequence to work around ARM
499 erratum 845719 on Cortex-A53 parts up to r0p4.
501 When running a compat (AArch32) userspace on an affected Cortex-A53
502 part, a load at EL0 from a virtual address that matches the bottom 32
503 bits of the virtual address used by a recent load at (AArch64) EL1
504 might return incorrect data.
506 The workaround is to write the contextidr_el1 register on exception
507 return to a 32-bit task.
508 Please note that this does not necessarily enable the workaround,
509 as it depends on the alternative framework, which will only patch
510 the kernel if an affected CPU is detected.
514 config ARM64_ERRATUM_843419
515 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
517 select ARM64_MODULE_PLTS if MODULES
519 This option links the kernel with '--fix-cortex-a53-843419' and
520 enables PLT support to replace certain ADRP instructions, which can
521 cause subsequent memory accesses to use an incorrect address on
522 Cortex-A53 parts up to r0p4.
526 config ARM64_LD_HAS_FIX_ERRATUM_843419
527 def_bool $(ld-option,--fix-cortex-a53-843419)
529 config ARM64_ERRATUM_1024718
530 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
533 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
535 Affected Cortex-A55 cores (all revisions) could cause incorrect
536 update of the hardware dirty bit when the DBM/AP bits are updated
537 without a break-before-make. The workaround is to disable the usage
538 of hardware DBM locally on the affected cores. CPUs not affected by
539 this erratum will continue to use the feature.
543 config ARM64_ERRATUM_1418040
544 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
548 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
549 errata 1188873 and 1418040.
551 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
552 cause register corruption when accessing the timer registers
553 from AArch32 userspace.
557 config ARM64_WORKAROUND_SPECULATIVE_AT
560 config ARM64_ERRATUM_1165522
561 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
563 select ARM64_WORKAROUND_SPECULATIVE_AT
565 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
567 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
568 corrupted TLBs by speculating an AT instruction during a guest
573 config ARM64_ERRATUM_1319367
574 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
576 select ARM64_WORKAROUND_SPECULATIVE_AT
578 This option adds work arounds for ARM Cortex-A57 erratum 1319537
579 and A72 erratum 1319367
581 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
582 speculating an AT instruction during a guest context switch.
586 config ARM64_ERRATUM_1530923
587 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
589 select ARM64_WORKAROUND_SPECULATIVE_AT
591 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
593 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
594 corrupted TLBs by speculating an AT instruction during a guest
599 config ARM64_WORKAROUND_REPEAT_TLBI
602 config ARM64_ERRATUM_1286807
603 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
605 select ARM64_WORKAROUND_REPEAT_TLBI
607 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
609 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
610 address for a cacheable mapping of a location is being
611 accessed by a core while another core is remapping the virtual
612 address to a new physical page using the recommended
613 break-before-make sequence, then under very rare circumstances
614 TLBI+DSB completes before a read using the translation being
615 invalidated has been observed by other observers. The
616 workaround repeats the TLBI+DSB operation.
618 config ARM64_ERRATUM_1463225
619 bool "Cortex-A76: Software Step might prevent interrupt recognition"
622 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
624 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
625 of a system call instruction (SVC) can prevent recognition of
626 subsequent interrupts when software stepping is disabled in the
627 exception handler of the system call and either kernel debugging
628 is enabled or VHE is in use.
630 Work around the erratum by triggering a dummy step exception
631 when handling a system call from a task that is being stepped
632 in a VHE configuration of the kernel.
636 config ARM64_ERRATUM_1542419
637 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
640 This option adds a workaround for ARM Neoverse-N1 erratum
643 Affected Neoverse-N1 cores could execute a stale instruction when
644 modified by another CPU. The workaround depends on a firmware
647 Workaround the issue by hiding the DIC feature from EL0. This
648 forces user-space to perform cache maintenance.
652 config ARM64_ERRATUM_1508412
653 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
656 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
658 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
659 of a store-exclusive or read of PAR_EL1 and a load with device or
660 non-cacheable memory attributes. The workaround depends on a firmware
663 KVM guests must also have the workaround implemented or they can
666 Work around the issue by inserting DMB SY barriers around PAR_EL1
667 register reads and warning KVM users. The DMB barrier is sufficient
668 to prevent a speculative PAR_EL1 read.
672 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
675 config ARM64_ERRATUM_2051678
676 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
679 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
680 Affected Coretex-A510 might not respect the ordering rules for
681 hardware update of the page table's dirty bit. The workaround
682 is to not enable the feature on affected CPUs.
686 config ARM64_ERRATUM_2077057
687 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
689 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
690 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
691 expected, but a Pointer Authentication trap is taken instead. The
692 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow
693 EL1 to cause a return to EL2 with a guest controlled ELR_EL2.
695 This can only happen when EL2 is stepping EL1.
697 When these conditions occur, the SPSR_EL2 value is unchanged from the
698 previous guest entry, and can be restored from the in-memory copy.
702 config ARM64_ERRATUM_2119858
703 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
705 depends on CORESIGHT_TRBE
706 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
708 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
710 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
711 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
712 the event of a WRAP event.
714 Work around the issue by always making sure we move the TRBPTR_EL1 by
715 256 bytes before enabling the buffer and filling the first 256 bytes of
716 the buffer with ETM ignore packets upon disabling.
720 config ARM64_ERRATUM_2139208
721 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
723 depends on CORESIGHT_TRBE
724 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
726 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
728 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
729 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
730 the event of a WRAP event.
732 Work around the issue by always making sure we move the TRBPTR_EL1 by
733 256 bytes before enabling the buffer and filling the first 256 bytes of
734 the buffer with ETM ignore packets upon disabling.
738 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
741 config ARM64_ERRATUM_2054223
742 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
744 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
746 Enable workaround for ARM Cortex-A710 erratum 2054223
748 Affected cores may fail to flush the trace data on a TSB instruction, when
749 the PE is in trace prohibited state. This will cause losing a few bytes
752 Workaround is to issue two TSB consecutively on affected cores.
756 config ARM64_ERRATUM_2067961
757 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
759 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
761 Enable workaround for ARM Neoverse-N2 erratum 2067961
763 Affected cores may fail to flush the trace data on a TSB instruction, when
764 the PE is in trace prohibited state. This will cause losing a few bytes
767 Workaround is to issue two TSB consecutively on affected cores.
771 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
774 config ARM64_ERRATUM_2253138
775 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
776 depends on CORESIGHT_TRBE
778 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
780 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
782 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
783 for TRBE. Under some conditions, the TRBE might generate a write to the next
784 virtually addressed page following the last page of the TRBE address space
785 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
787 Work around this in the driver by always making sure that there is a
788 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
792 config ARM64_ERRATUM_2224489
793 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
794 depends on CORESIGHT_TRBE
796 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
798 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
800 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
801 for TRBE. Under some conditions, the TRBE might generate a write to the next
802 virtually addressed page following the last page of the TRBE address space
803 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
805 Work around this in the driver by always making sure that there is a
806 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
810 config ARM64_ERRATUM_2064142
811 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
812 depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
815 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
817 Affected Cortex-A510 core might fail to write into system registers after the
818 TRBE has been disabled. Under some conditions after the TRBE has been disabled
819 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,
820 and TRBTRG_EL1 will be ignored and will not be effected.
822 Work around this in the driver by executing TSB CSYNC and DSB after collection
823 is stopped and before performing a system register write to one of the affected
828 config ARM64_ERRATUM_2038923
829 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
830 depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
833 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
835 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
836 prohibited within the CPU. As a result, the trace buffer or trace buffer state
837 might be corrupted. This happens after TRBE buffer has been enabled by setting
838 TRBLIMITR_EL1.E, followed by just a single context synchronization event before
839 execution changes from a context, in which trace is prohibited to one where it
840 isn't, or vice versa. In these mentioned conditions, the view of whether trace
841 is prohibited is inconsistent between parts of the CPU, and the trace buffer or
842 the trace buffer state might be corrupted.
844 Work around this in the driver by preventing an inconsistent view of whether the
845 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
846 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
847 two ISB instructions if no ERET is to take place.
851 config ARM64_ERRATUM_1902691
852 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
853 depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
856 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
858 Affected Cortex-A510 core might cause trace data corruption, when being written
859 into the memory. Effectively TRBE is broken and hence cannot be used to capture
862 Work around this problem in the driver by just preventing TRBE initialization on
863 affected cpus. The firmware must have disabled the access to TRBE for the kernel
864 on such implementations. This will cover the kernel for any firmware that doesn't
869 config CAVIUM_ERRATUM_22375
870 bool "Cavium erratum 22375, 24313"
873 Enable workaround for errata 22375 and 24313.
875 This implements two gicv3-its errata workarounds for ThunderX. Both
876 with a small impact affecting only ITS table allocation.
878 erratum 22375: only alloc 8MB table size
879 erratum 24313: ignore memory access type
881 The fixes are in ITS initialization and basically ignore memory access
882 type and table size provided by the TYPER and BASER registers.
886 config CAVIUM_ERRATUM_23144
887 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
891 ITS SYNC command hang for cross node io and collections/cpu mapping.
895 config CAVIUM_ERRATUM_23154
896 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"
899 The ThunderX GICv3 implementation requires a modified version for
900 reading the IAR status to ensure data synchronization
901 (access to icc_iar1_el1 is not sync'ed before and after).
903 It also suffers from erratum 38545 (also present on Marvell's
904 OcteonTX and OcteonTX2), resulting in deactivated interrupts being
905 spuriously presented to the CPU interface.
909 config CAVIUM_ERRATUM_27456
910 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
913 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
914 instructions may cause the icache to become corrupted if it
915 contains data for a non-current ASID. The fix is to
916 invalidate the icache when changing the mm context.
920 config CAVIUM_ERRATUM_30115
921 bool "Cavium erratum 30115: Guest may disable interrupts in host"
924 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
925 1.2, and T83 Pass 1.0, KVM guest execution may disable
926 interrupts in host. Trapping both GICv3 group-0 and group-1
927 accesses sidesteps the issue.
931 config CAVIUM_TX2_ERRATUM_219
932 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
935 On Cavium ThunderX2, a load, store or prefetch instruction between a
936 TTBR update and the corresponding context synchronizing operation can
937 cause a spurious Data Abort to be delivered to any hardware thread in
940 Work around the issue by avoiding the problematic code sequence and
941 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
942 trap handler performs the corresponding register access, skips the
943 instruction and ensures context synchronization by virtue of the
948 config FUJITSU_ERRATUM_010001
949 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
952 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
953 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
954 accesses may cause undefined fault (Data abort, DFSC=0b111111).
955 This fault occurs under a specific hardware condition when a
956 load/store instruction performs an address translation using:
957 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
958 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
959 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
960 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
962 The workaround is to ensure these bits are clear in TCR_ELx.
963 The workaround only affects the Fujitsu-A64FX.
967 config HISILICON_ERRATUM_161600802
968 bool "Hip07 161600802: Erroneous redistributor VLPI base"
971 The HiSilicon Hip07 SoC uses the wrong redistributor base
972 when issued ITS commands such as VMOVP and VMAPP, and requires
973 a 128kB offset to be applied to the target address in this commands.
977 config QCOM_FALKOR_ERRATUM_1003
978 bool "Falkor E1003: Incorrect translation due to ASID change"
981 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
982 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
983 in TTBR1_EL1, this situation only occurs in the entry trampoline and
984 then only for entries in the walk cache, since the leaf translation
985 is unchanged. Work around the erratum by invalidating the walk cache
986 entries for the trampoline before entering the kernel proper.
988 config QCOM_FALKOR_ERRATUM_1009
989 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
991 select ARM64_WORKAROUND_REPEAT_TLBI
993 On Falkor v1, the CPU may prematurely complete a DSB following a
994 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
995 one more time to fix the issue.
999 config QCOM_QDF2400_ERRATUM_0065
1000 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
1003 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
1004 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
1005 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
1009 config QCOM_FALKOR_ERRATUM_E1041
1010 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
1013 Falkor CPU may speculatively fetch instructions from an improper
1014 memory location when MMU translation is changed from SCTLR_ELn[M]=1
1015 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
1019 config NVIDIA_CARMEL_CNP_ERRATUM
1020 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
1023 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1024 invalidate shared TLB entries installed by a different core, as it would
1025 on standard ARM cores.
1029 config SOCIONEXT_SYNQUACER_PREITS
1030 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1033 Socionext Synquacer SoCs implement a separate h/w block to generate
1034 MSI doorbell writes with non-zero values for the device ID.
1043 default ARM64_4K_PAGES
1045 Page size (translation granule) configuration.
1047 config ARM64_4K_PAGES
1050 This feature enables 4KB pages support.
1052 config ARM64_16K_PAGES
1055 The system will use 16KB pages support. AArch32 emulation
1056 requires applications compiled with 16K (or a multiple of 16K)
1059 config ARM64_64K_PAGES
1062 This feature enables 64KB pages support (4KB by default)
1063 allowing only two levels of page tables and faster TLB
1064 look-up. AArch32 emulation requires applications compiled
1065 with 64K aligned segments.
1070 prompt "Virtual address space size"
1071 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
1072 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
1073 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
1075 Allows choosing one of multiple possible virtual address
1076 space sizes. The level of translation table is determined by
1077 a combination of page size and virtual address space size.
1079 config ARM64_VA_BITS_36
1080 bool "36-bit" if EXPERT
1081 depends on ARM64_16K_PAGES
1083 config ARM64_VA_BITS_39
1085 depends on ARM64_4K_PAGES
1087 config ARM64_VA_BITS_42
1089 depends on ARM64_64K_PAGES
1091 config ARM64_VA_BITS_47
1093 depends on ARM64_16K_PAGES
1095 config ARM64_VA_BITS_48
1098 config ARM64_VA_BITS_52
1100 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
1102 Enable 52-bit virtual addressing for userspace when explicitly
1103 requested via a hint to mmap(). The kernel will also use 52-bit
1104 virtual addresses for its own mappings (provided HW support for
1105 this feature is available, otherwise it reverts to 48-bit).
1107 NOTE: Enabling 52-bit virtual addressing in conjunction with
1108 ARMv8.3 Pointer Authentication will result in the PAC being
1109 reduced from 7 bits to 3 bits, which may have a significant
1110 impact on its susceptibility to brute-force attacks.
1112 If unsure, select 48-bit virtual addressing instead.
1116 config ARM64_FORCE_52BIT
1117 bool "Force 52-bit virtual addresses for userspace"
1118 depends on ARM64_VA_BITS_52 && EXPERT
1120 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1121 to maintain compatibility with older software by providing 48-bit VAs
1122 unless a hint is supplied to mmap.
1124 This configuration option disables the 48-bit compatibility logic, and
1125 forces all userspace addresses to be 52-bit on HW that supports it. One
1126 should only enable this configuration option for stress testing userspace
1127 memory management code. If unsure say N here.
1129 config ARM64_VA_BITS
1131 default 36 if ARM64_VA_BITS_36
1132 default 39 if ARM64_VA_BITS_39
1133 default 42 if ARM64_VA_BITS_42
1134 default 47 if ARM64_VA_BITS_47
1135 default 48 if ARM64_VA_BITS_48
1136 default 52 if ARM64_VA_BITS_52
1139 prompt "Physical address space size"
1140 default ARM64_PA_BITS_48
1142 Choose the maximum physical address range that the kernel will
1145 config ARM64_PA_BITS_48
1148 config ARM64_PA_BITS_52
1149 bool "52-bit (ARMv8.2)"
1150 depends on ARM64_64K_PAGES
1151 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1153 Enable support for a 52-bit physical address space, introduced as
1154 part of the ARMv8.2-LPA extension.
1156 With this enabled, the kernel will also continue to work on CPUs that
1157 do not support ARMv8.2-LPA, but with some added memory overhead (and
1158 minor performance overhead).
1162 config ARM64_PA_BITS
1164 default 48 if ARM64_PA_BITS_48
1165 default 52 if ARM64_PA_BITS_52
1169 default CPU_LITTLE_ENDIAN
1171 Select the endianness of data accesses performed by the CPU. Userspace
1172 applications will need to be compiled and linked for the endianness
1173 that is selected here.
1175 config CPU_BIG_ENDIAN
1176 bool "Build big-endian kernel"
1177 depends on !LD_IS_LLD || LLD_VERSION >= 130000
1179 Say Y if you plan on running a kernel with a big-endian userspace.
1181 config CPU_LITTLE_ENDIAN
1182 bool "Build little-endian kernel"
1184 Say Y if you plan on running a kernel with a little-endian userspace.
1185 This is usually the case for distributions targeting arm64.
1190 bool "Multi-core scheduler support"
1192 Multi-core scheduler support improves the CPU scheduler's decision
1193 making when dealing with multi-core CPU chips at a cost of slightly
1194 increased overhead in some places. If unsure say N here.
1196 config SCHED_CLUSTER
1197 bool "Cluster scheduler support"
1199 Cluster scheduler support improves the CPU scheduler's decision
1200 making when dealing with machines that have clusters of CPUs.
1201 Cluster usually means a couple of CPUs which are placed closely
1202 by sharing mid-level caches, last-level cache tags or internal
1206 bool "SMT scheduler support"
1208 Improves the CPU scheduler's decision making when dealing with
1209 MultiThreading at a cost of slightly increased overhead in some
1210 places. If unsure say N here.
1213 int "Maximum number of CPUs (2-4096)"
1218 bool "Support for hot-pluggable CPUs"
1219 select GENERIC_IRQ_MIGRATION
1221 Say Y here to experiment with turning CPUs off and on. CPUs
1222 can be controlled through /sys/devices/system/cpu.
1224 # Common NUMA Features
1226 bool "NUMA Memory Allocation and Scheduler Support"
1227 select GENERIC_ARCH_NUMA
1228 select ACPI_NUMA if ACPI
1230 select HAVE_SETUP_PER_CPU_AREA
1231 select NEED_PER_CPU_EMBED_FIRST_CHUNK
1232 select NEED_PER_CPU_PAGE_FIRST_CHUNK
1233 select USE_PERCPU_NUMA_NODE_ID
1235 Enable NUMA (Non-Uniform Memory Access) support.
1237 The kernel will try to allocate memory used by a CPU on the
1238 local memory of the CPU and add some more
1239 NUMA awareness to the kernel.
1242 int "Maximum NUMA Nodes (as a power of 2)"
1247 Specify the maximum number of NUMA Nodes available on the target
1248 system. Increases memory reserved to accommodate various tables.
1250 source "kernel/Kconfig.hz"
1252 config ARCH_SPARSEMEM_ENABLE
1254 select SPARSEMEM_VMEMMAP_ENABLE
1255 select SPARSEMEM_VMEMMAP
1257 config HW_PERF_EVENTS
1261 # Supported by clang >= 7.0 or GCC >= 12.0.0
1262 config CC_HAVE_SHADOW_CALL_STACK
1263 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1266 bool "Enable paravirtualization code"
1268 This changes the kernel so it can modify itself when it is run
1269 under a hypervisor, potentially improving performance significantly
1270 over full virtualization.
1272 config PARAVIRT_TIME_ACCOUNTING
1273 bool "Paravirtual steal time accounting"
1276 Select this option to enable fine granularity task steal time
1277 accounting. Time spent executing other tasks in parallel with
1278 the current vCPU is discounted from the vCPU power. To account for
1279 that, there can be a small performance impact.
1281 If in doubt, say N here.
1284 depends on PM_SLEEP_SMP
1286 bool "kexec system call"
1288 kexec is a system call that implements the ability to shutdown your
1289 current kernel, and to start another kernel. It is like a reboot
1290 but it is independent of the system firmware. And like a reboot
1291 you can start any kernel with it, not just Linux.
1294 bool "kexec file based system call"
1296 select HAVE_IMA_KEXEC if IMA
1298 This is new version of kexec system call. This system call is
1299 file based and takes file descriptors as system call argument
1300 for kernel and initramfs as opposed to list of segments as
1301 accepted by previous system call.
1304 bool "Verify kernel signature during kexec_file_load() syscall"
1305 depends on KEXEC_FILE
1307 Select this option to verify a signature with loaded kernel
1308 image. If configured, any attempt of loading a image without
1309 valid signature will fail.
1311 In addition to that option, you need to enable signature
1312 verification for the corresponding kernel image type being
1313 loaded in order for this to work.
1315 config KEXEC_IMAGE_VERIFY_SIG
1316 bool "Enable Image signature verification support"
1318 depends on KEXEC_SIG
1319 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1321 Enable Image signature verification support.
1323 comment "Support for PE file signature verification disabled"
1324 depends on KEXEC_SIG
1325 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1328 bool "Build kdump crash kernel"
1330 Generate crash dump after being started by kexec. This should
1331 be normally only set in special crash dump kernels which are
1332 loaded in the main kernel with kexec-tools into a specially
1333 reserved region and then later executed after a crash by
1336 For more details see Documentation/admin-guide/kdump/kdump.rst
1340 depends on HIBERNATION || KEXEC_CORE
1347 bool "Xen guest support on ARM64"
1348 depends on ARM64 && OF
1352 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1354 config FORCE_MAX_ZONEORDER
1356 default "14" if ARM64_64K_PAGES
1357 default "12" if ARM64_16K_PAGES
1360 The kernel memory allocator divides physically contiguous memory
1361 blocks into "zones", where each zone is a power of two number of
1362 pages. This option selects the largest power of two that the kernel
1363 keeps in the memory allocator. If you need to allocate very large
1364 blocks of physically contiguous memory, then you may need to
1365 increase this value.
1367 This config option is actually maximum order plus one. For example,
1368 a value of 11 means that the largest free memory block is 2^10 pages.
1370 We make sure that we can allocate upto a HugePage size for each configuration.
1372 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1374 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1375 4M allocations matching the default size used by generic code.
1377 config UNMAP_KERNEL_AT_EL0
1378 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1381 Speculation attacks against some high-performance processors can
1382 be used to bypass MMU permission checks and leak kernel data to
1383 userspace. This can be defended against by unmapping the kernel
1384 when running in userspace, mapping it back in on exception entry
1385 via a trampoline page in the vector table.
1389 config MITIGATE_SPECTRE_BRANCH_HISTORY
1390 bool "Mitigate Spectre style attacks against branch history" if EXPERT
1393 Speculation attacks against some high-performance processors can
1394 make use of branch history to influence future speculation.
1395 When taking an exception from user-space, a sequence of branches
1396 or a firmware call overwrites the branch history.
1398 config RODATA_FULL_DEFAULT_ENABLED
1399 bool "Apply r/o permissions of VM areas also to their linear aliases"
1402 Apply read-only attributes of VM areas to the linear alias of
1403 the backing pages as well. This prevents code or read-only data
1404 from being modified (inadvertently or intentionally) via another
1405 mapping of the same memory page. This additional enhancement can
1406 be turned off at runtime by passing rodata=[off|on] (and turned on
1407 with rodata=full if this option is set to 'n')
1409 This requires the linear region to be mapped down to pages,
1410 which may adversely affect performance in some cases.
1412 config ARM64_SW_TTBR0_PAN
1413 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1415 Enabling this option prevents the kernel from accessing
1416 user-space memory directly by pointing TTBR0_EL1 to a reserved
1417 zeroed area and reserved ASID. The user access routines
1418 restore the valid TTBR0_EL1 temporarily.
1420 config ARM64_TAGGED_ADDR_ABI
1421 bool "Enable the tagged user addresses syscall ABI"
1424 When this option is enabled, user applications can opt in to a
1425 relaxed ABI via prctl() allowing tagged addresses to be passed
1426 to system calls as pointer arguments. For details, see
1427 Documentation/arm64/tagged-address-abi.rst.
1430 bool "Kernel support for 32-bit EL0"
1431 depends on ARM64_4K_PAGES || EXPERT
1433 select OLD_SIGSUSPEND3
1434 select COMPAT_OLD_SIGACTION
1436 This option enables support for a 32-bit EL0 running under a 64-bit
1437 kernel at EL1. AArch32-specific components such as system calls,
1438 the user helper functions, VFP support and the ptrace interface are
1439 handled appropriately by the kernel.
1441 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1442 that you will only be able to execute AArch32 binaries that were compiled
1443 with page size aligned segments.
1445 If you want to execute 32-bit userspace applications, say Y.
1449 config KUSER_HELPERS
1450 bool "Enable kuser helpers page for 32-bit applications"
1453 Warning: disabling this option may break 32-bit user programs.
1455 Provide kuser helpers to compat tasks. The kernel provides
1456 helper code to userspace in read only form at a fixed location
1457 to allow userspace to be independent of the CPU type fitted to
1458 the system. This permits binaries to be run on ARMv4 through
1459 to ARMv8 without modification.
1461 See Documentation/arm/kernel_user_helpers.rst for details.
1463 However, the fixed address nature of these helpers can be used
1464 by ROP (return orientated programming) authors when creating
1467 If all of the binaries and libraries which run on your platform
1468 are built specifically for your platform, and make no use of
1469 these helpers, then you can turn this option off to hinder
1470 such exploits. However, in that case, if a binary or library
1471 relying on those helpers is run, it will not function correctly.
1473 Say N here only if you are absolutely certain that you do not
1474 need these helpers; otherwise, the safe option is to say Y.
1477 bool "Enable vDSO for 32-bit applications"
1478 depends on !CPU_BIG_ENDIAN
1479 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1480 select GENERIC_COMPAT_VDSO
1483 Place in the process address space of 32-bit applications an
1484 ELF shared object providing fast implementations of gettimeofday
1487 You must have a 32-bit build of glibc 2.22 or later for programs
1488 to seamlessly take advantage of this.
1490 config THUMB2_COMPAT_VDSO
1491 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1492 depends on COMPAT_VDSO
1495 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1496 otherwise with '-marm'.
1498 menuconfig ARMV8_DEPRECATED
1499 bool "Emulate deprecated/obsolete ARMv8 instructions"
1502 Legacy software support may require certain instructions
1503 that have been deprecated or obsoleted in the architecture.
1505 Enable this config to enable selective emulation of these
1512 config SWP_EMULATION
1513 bool "Emulate SWP/SWPB instructions"
1515 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1516 they are always undefined. Say Y here to enable software
1517 emulation of these instructions for userspace using LDXR/STXR.
1518 This feature can be controlled at runtime with the abi.swp
1519 sysctl which is disabled by default.
1521 In some older versions of glibc [<=2.8] SWP is used during futex
1522 trylock() operations with the assumption that the code will not
1523 be preempted. This invalid assumption may be more likely to fail
1524 with SWP emulation enabled, leading to deadlock of the user
1527 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1528 on an external transaction monitoring block called a global
1529 monitor to maintain update atomicity. If your system does not
1530 implement a global monitor, this option can cause programs that
1531 perform SWP operations to uncached memory to deadlock.
1535 config CP15_BARRIER_EMULATION
1536 bool "Emulate CP15 Barrier instructions"
1538 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1539 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1540 strongly recommended to use the ISB, DSB, and DMB
1541 instructions instead.
1543 Say Y here to enable software emulation of these
1544 instructions for AArch32 userspace code. When this option is
1545 enabled, CP15 barrier usage is traced which can help
1546 identify software that needs updating. This feature can be
1547 controlled at runtime with the abi.cp15_barrier sysctl.
1551 config SETEND_EMULATION
1552 bool "Emulate SETEND instruction"
1554 The SETEND instruction alters the data-endianness of the
1555 AArch32 EL0, and is deprecated in ARMv8.
1557 Say Y here to enable software emulation of the instruction
1558 for AArch32 userspace code. This feature can be controlled
1559 at runtime with the abi.setend sysctl.
1561 Note: All the cpus on the system must have mixed endian support at EL0
1562 for this feature to be enabled. If a new CPU - which doesn't support mixed
1563 endian - is hotplugged in after this feature has been enabled, there could
1564 be unexpected results in the applications.
1571 menu "ARMv8.1 architectural features"
1573 config ARM64_HW_AFDBM
1574 bool "Support for hardware updates of the Access and Dirty page flags"
1577 The ARMv8.1 architecture extensions introduce support for
1578 hardware updates of the access and dirty information in page
1579 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1580 capable processors, accesses to pages with PTE_AF cleared will
1581 set this bit instead of raising an access flag fault.
1582 Similarly, writes to read-only pages with the DBM bit set will
1583 clear the read-only bit (AP[2]) instead of raising a
1586 Kernels built with this configuration option enabled continue
1587 to work on pre-ARMv8.1 hardware and the performance impact is
1588 minimal. If unsure, say Y.
1591 bool "Enable support for Privileged Access Never (PAN)"
1594 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1595 prevents the kernel or hypervisor from accessing user-space (EL0)
1598 Choosing this option will cause any unprotected (not using
1599 copy_to_user et al) memory access to fail with a permission fault.
1601 The feature is detected at runtime, and will remain as a 'nop'
1602 instruction if the cpu does not implement the feature.
1605 def_bool $(as-instr,.arch_extension rcpc)
1607 config AS_HAS_LSE_ATOMICS
1608 def_bool $(as-instr,.arch_extension lse)
1610 config ARM64_LSE_ATOMICS
1612 default ARM64_USE_LSE_ATOMICS
1613 depends on AS_HAS_LSE_ATOMICS
1615 config ARM64_USE_LSE_ATOMICS
1616 bool "Atomic instructions"
1617 depends on JUMP_LABEL
1620 As part of the Large System Extensions, ARMv8.1 introduces new
1621 atomic instructions that are designed specifically to scale in
1624 Say Y here to make use of these instructions for the in-kernel
1625 atomic routines. This incurs a small overhead on CPUs that do
1626 not support these instructions and requires the kernel to be
1627 built with binutils >= 2.25 in order for the new instructions
1632 menu "ARMv8.2 architectural features"
1634 config AS_HAS_ARMV8_2
1635 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1638 def_bool $(as-instr,.arch armv8.2-a+sha3)
1641 bool "Enable support for persistent memory"
1642 select ARCH_HAS_PMEM_API
1643 select ARCH_HAS_UACCESS_FLUSHCACHE
1645 Say Y to enable support for the persistent memory API based on the
1646 ARMv8.2 DCPoP feature.
1648 The feature is detected at runtime, and the kernel will use DC CVAC
1649 operations if DC CVAP is not supported (following the behaviour of
1650 DC CVAP itself if the system does not define a point of persistence).
1652 config ARM64_RAS_EXTN
1653 bool "Enable support for RAS CPU Extensions"
1656 CPUs that support the Reliability, Availability and Serviceability
1657 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1658 errors, classify them and report them to software.
1660 On CPUs with these extensions system software can use additional
1661 barriers to determine if faults are pending and read the
1662 classification from a new set of registers.
1664 Selecting this feature will allow the kernel to use these barriers
1665 and access the new registers if the system supports the extension.
1666 Platform RAS features may additionally depend on firmware support.
1669 bool "Enable support for Common Not Private (CNP) translations"
1671 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1673 Common Not Private (CNP) allows translation table entries to
1674 be shared between different PEs in the same inner shareable
1675 domain, so the hardware can use this fact to optimise the
1676 caching of such entries in the TLB.
1678 Selecting this option allows the CNP feature to be detected
1679 at runtime, and does not affect PEs that do not implement
1684 menu "ARMv8.3 architectural features"
1686 config ARM64_PTR_AUTH
1687 bool "Enable support for pointer authentication"
1690 Pointer authentication (part of the ARMv8.3 Extensions) provides
1691 instructions for signing and authenticating pointers against secret
1692 keys, which can be used to mitigate Return Oriented Programming (ROP)
1695 This option enables these instructions at EL0 (i.e. for userspace).
1696 Choosing this option will cause the kernel to initialise secret keys
1697 for each process at exec() time, with these keys being
1698 context-switched along with the process.
1700 The feature is detected at runtime. If the feature is not present in
1701 hardware it will not be advertised to userspace/KVM guest nor will it
1704 If the feature is present on the boot CPU but not on a late CPU, then
1705 the late CPU will be parked. Also, if the boot CPU does not have
1706 address auth and the late CPU has then the late CPU will still boot
1707 but with the feature disabled. On such a system, this option should
1710 config ARM64_PTR_AUTH_KERNEL
1711 bool "Use pointer authentication for kernel"
1713 depends on ARM64_PTR_AUTH
1714 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1715 # Modern compilers insert a .note.gnu.property section note for PAC
1716 # which is only understood by binutils starting with version 2.33.1.
1717 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1718 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1719 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1721 If the compiler supports the -mbranch-protection or
1722 -msign-return-address flag (e.g. GCC 7 or later), then this option
1723 will cause the kernel itself to be compiled with return address
1724 protection. In this case, and if the target hardware is known to
1725 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1726 disabled with minimal loss of protection.
1728 This feature works with FUNCTION_GRAPH_TRACER option only if
1729 DYNAMIC_FTRACE_WITH_REGS is enabled.
1731 config CC_HAS_BRANCH_PROT_PAC_RET
1732 # GCC 9 or later, clang 8 or later
1733 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1735 config CC_HAS_SIGN_RETURN_ADDRESS
1737 def_bool $(cc-option,-msign-return-address=all)
1740 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1742 config AS_HAS_CFI_NEGATE_RA_STATE
1743 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1747 menu "ARMv8.4 architectural features"
1749 config ARM64_AMU_EXTN
1750 bool "Enable support for the Activity Monitors Unit CPU extension"
1753 The activity monitors extension is an optional extension introduced
1754 by the ARMv8.4 CPU architecture. This enables support for version 1
1755 of the activity monitors architecture, AMUv1.
1757 To enable the use of this extension on CPUs that implement it, say Y.
1759 Note that for architectural reasons, firmware _must_ implement AMU
1760 support when running on CPUs that present the activity monitors
1761 extension. The required support is present in:
1762 * Version 1.5 and later of the ARM Trusted Firmware
1764 For kernels that have this configuration enabled but boot with broken
1765 firmware, you may need to say N here until the firmware is fixed.
1766 Otherwise you may experience firmware panics or lockups when
1767 accessing the counter registers. Even if you are not observing these
1768 symptoms, the values returned by the register reads might not
1769 correctly reflect reality. Most commonly, the value read will be 0,
1770 indicating that the counter is not enabled.
1772 config AS_HAS_ARMV8_4
1773 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1775 config ARM64_TLB_RANGE
1776 bool "Enable support for tlbi range feature"
1778 depends on AS_HAS_ARMV8_4
1780 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1781 range of input addresses.
1783 The feature introduces new assembly instructions, and they were
1784 support when binutils >= 2.30.
1788 menu "ARMv8.5 architectural features"
1790 config AS_HAS_ARMV8_5
1791 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1794 bool "Branch Target Identification support"
1797 Branch Target Identification (part of the ARMv8.5 Extensions)
1798 provides a mechanism to limit the set of locations to which computed
1799 branch instructions such as BR or BLR can jump.
1801 To make use of BTI on CPUs that support it, say Y.
1803 BTI is intended to provide complementary protection to other control
1804 flow integrity protection mechanisms, such as the Pointer
1805 authentication mechanism provided as part of the ARMv8.3 Extensions.
1806 For this reason, it does not make sense to enable this option without
1807 also enabling support for pointer authentication. Thus, when
1808 enabling this option you should also select ARM64_PTR_AUTH=y.
1810 Userspace binaries must also be specifically compiled to make use of
1811 this mechanism. If you say N here or the hardware does not support
1812 BTI, such binaries can still run, but you get no additional
1813 enforcement of branch destinations.
1815 config ARM64_BTI_KERNEL
1816 bool "Use Branch Target Identification for kernel"
1818 depends on ARM64_BTI
1819 depends on ARM64_PTR_AUTH_KERNEL
1820 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1821 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1822 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1823 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1824 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
1825 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1827 Build the kernel with Branch Target Identification annotations
1828 and enable enforcement of this for kernel code. When this option
1829 is enabled and the system supports BTI all kernel code including
1830 modular code must have BTI enabled.
1832 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1833 # GCC 9 or later, clang 8 or later
1834 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1837 bool "Enable support for E0PD"
1840 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1841 that EL0 accesses made via TTBR1 always fault in constant time,
1842 providing similar benefits to KASLR as those provided by KPTI, but
1843 with lower overhead and without disrupting legitimate access to
1844 kernel memory such as SPE.
1846 This option enables E0PD for TTBR1 where available.
1849 bool "Enable support for random number generation"
1852 Random number generation (part of the ARMv8.5 Extensions)
1853 provides a high bandwidth, cryptographically secure
1854 hardware random number generator.
1856 config ARM64_AS_HAS_MTE
1857 # Initial support for MTE went in binutils 2.32.0, checked with
1858 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1859 # as a late addition to the final architecture spec (LDGM/STGM)
1860 # is only supported in the newer 2.32.x and 2.33 binutils
1861 # versions, hence the extra "stgm" instruction check below.
1862 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1865 bool "Memory Tagging Extension support"
1867 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1868 depends on AS_HAS_ARMV8_5
1869 depends on AS_HAS_LSE_ATOMICS
1870 # Required for tag checking in the uaccess routines
1871 depends on ARM64_PAN
1872 select ARCH_USES_HIGH_VMA_FLAGS
1874 Memory Tagging (part of the ARMv8.5 Extensions) provides
1875 architectural support for run-time, always-on detection of
1876 various classes of memory error to aid with software debugging
1877 to eliminate vulnerabilities arising from memory-unsafe
1880 This option enables the support for the Memory Tagging
1881 Extension at EL0 (i.e. for userspace).
1883 Selecting this option allows the feature to be detected at
1884 runtime. Any secondary CPU not implementing this feature will
1885 not be allowed a late bring-up.
1887 Userspace binaries that want to use this feature must
1888 explicitly opt in. The mechanism for the userspace is
1891 Documentation/arm64/memory-tagging-extension.rst.
1895 menu "ARMv8.7 architectural features"
1898 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
1900 depends on ARM64_PAN
1902 Enhanced Privileged Access Never (EPAN) allows Privileged
1903 Access Never to be used with Execute-only mappings.
1905 The feature is detected at runtime, and will remain disabled
1906 if the cpu does not implement the feature.
1910 bool "ARM Scalable Vector Extension support"
1913 The Scalable Vector Extension (SVE) is an extension to the AArch64
1914 execution state which complements and extends the SIMD functionality
1915 of the base architecture to support much larger vectors and to enable
1916 additional vectorisation opportunities.
1918 To enable use of this extension on CPUs that implement it, say Y.
1920 On CPUs that support the SVE2 extensions, this option will enable
1923 Note that for architectural reasons, firmware _must_ implement SVE
1924 support when running on SVE capable hardware. The required support
1927 * version 1.5 and later of the ARM Trusted Firmware
1928 * the AArch64 boot wrapper since commit 5e1261e08abf
1929 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1931 For other firmware implementations, consult the firmware documentation
1934 If you need the kernel to boot on SVE-capable hardware with broken
1935 firmware, you may need to say N here until you get your firmware
1936 fixed. Otherwise, you may experience firmware panics or lockups when
1937 booting the kernel. If unsure and you are not observing these
1938 symptoms, you should assume that it is safe to say Y.
1940 config ARM64_MODULE_PLTS
1941 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1943 select HAVE_MOD_ARCH_SPECIFIC
1945 Allocate PLTs when loading modules so that jumps and calls whose
1946 targets are too far away for their relative offsets to be encoded
1947 in the instructions themselves can be bounced via veneers in the
1948 module's PLT. This allows modules to be allocated in the generic
1949 vmalloc area after the dedicated module memory area has been
1952 When running with address space randomization (KASLR), the module
1953 region itself may be too far away for ordinary relative jumps and
1954 calls, and so in that case, module PLTs are required and cannot be
1957 Specific errata workaround(s) might also force module PLTs to be
1958 enabled (ARM64_ERRATUM_843419).
1960 config ARM64_PSEUDO_NMI
1961 bool "Support for NMI-like interrupts"
1964 Adds support for mimicking Non-Maskable Interrupts through the use of
1965 GIC interrupt priority. This support requires version 3 or later of
1968 This high priority configuration for interrupts needs to be
1969 explicitly enabled by setting the kernel parameter
1970 "irqchip.gicv3_pseudo_nmi" to 1.
1975 config ARM64_DEBUG_PRIORITY_MASKING
1976 bool "Debug interrupt priority masking"
1978 This adds runtime checks to functions enabling/disabling
1979 interrupts when using priority masking. The additional checks verify
1980 the validity of ICC_PMR_EL1 when calling concerned functions.
1986 bool "Build a relocatable kernel image" if EXPERT
1987 select ARCH_HAS_RELR
1990 This builds the kernel as a Position Independent Executable (PIE),
1991 which retains all relocation metadata required to relocate the
1992 kernel binary at runtime to a different virtual address than the
1993 address it was linked at.
1994 Since AArch64 uses the RELA relocation format, this requires a
1995 relocation pass at runtime even if the kernel is loaded at the
1996 same address it was linked at.
1998 config RANDOMIZE_BASE
1999 bool "Randomize the address of the kernel image"
2000 select ARM64_MODULE_PLTS if MODULES
2003 Randomizes the virtual address at which the kernel image is
2004 loaded, as a security feature that deters exploit attempts
2005 relying on knowledge of the location of kernel internals.
2007 It is the bootloader's job to provide entropy, by passing a
2008 random u64 value in /chosen/kaslr-seed at kernel entry.
2010 When booting via the UEFI stub, it will invoke the firmware's
2011 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
2012 to the kernel proper. In addition, it will randomise the physical
2013 location of the kernel Image as well.
2017 config RANDOMIZE_MODULE_REGION_FULL
2018 bool "Randomize the module region over a 2 GB range"
2019 depends on RANDOMIZE_BASE
2022 Randomizes the location of the module region inside a 2 GB window
2023 covering the core kernel. This way, it is less likely for modules
2024 to leak information about the location of core kernel data structures
2025 but it does imply that function calls between modules and the core
2026 kernel will need to be resolved via veneers in the module PLT.
2028 When this option is not set, the module region will be randomized over
2029 a limited range that contains the [_stext, _etext] interval of the
2030 core kernel, so branch relocations are almost always in range unless
2031 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this
2032 particular case of region exhaustion, modules might be able to fall
2033 back to a larger 2GB area.
2035 config CC_HAVE_STACKPROTECTOR_SYSREG
2036 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
2038 config STACKPROTECTOR_PER_TASK
2040 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
2046 config ARM64_ACPI_PARKING_PROTOCOL
2047 bool "Enable support for the ARM64 ACPI parking protocol"
2050 Enable support for the ARM64 ACPI parking protocol. If disabled
2051 the kernel will not allow booting through the ARM64 ACPI parking
2052 protocol even if the corresponding data is present in the ACPI
2056 string "Default kernel command string"
2059 Provide a set of default command-line options at build time by
2060 entering them here. As a minimum, you should specify the the
2061 root device (e.g. root=/dev/nfs).
2064 prompt "Kernel command line type" if CMDLINE != ""
2065 default CMDLINE_FROM_BOOTLOADER
2067 Choose how the kernel will handle the provided default kernel
2068 command line string.
2070 config CMDLINE_FROM_BOOTLOADER
2071 bool "Use bootloader kernel arguments if available"
2073 Uses the command-line options passed by the boot loader. If
2074 the boot loader doesn't provide any, the default kernel command
2075 string provided in CMDLINE will be used.
2077 config CMDLINE_FORCE
2078 bool "Always use the default kernel command string"
2080 Always use the default kernel command string, even if the boot
2081 loader passes other arguments to the kernel.
2082 This is useful if you cannot or don't want to change the
2083 command-line options your boot loader passes to the kernel.
2091 bool "UEFI runtime support"
2092 depends on OF && !CPU_BIG_ENDIAN
2093 depends on KERNEL_MODE_NEON
2094 select ARCH_SUPPORTS_ACPI
2097 select EFI_PARAMS_FROM_FDT
2098 select EFI_RUNTIME_WRAPPERS
2100 select EFI_GENERIC_STUB
2101 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
2104 This option provides support for runtime services provided
2105 by UEFI firmware (such as non-volatile variables, realtime
2106 clock, and platform reset). A UEFI stub is also provided to
2107 allow the kernel to be booted as an EFI application. This
2108 is only useful on systems that have UEFI firmware.
2111 bool "Enable support for SMBIOS (DMI) tables"
2115 This enables SMBIOS/DMI feature for systems.
2117 This option is only useful on systems that have UEFI firmware.
2118 However, even with this option, the resultant kernel should
2119 continue to boot on existing non-UEFI platforms.
2123 config SYSVIPC_COMPAT
2125 depends on COMPAT && SYSVIPC
2127 menu "Power management options"
2129 source "kernel/power/Kconfig"
2131 config ARCH_HIBERNATION_POSSIBLE
2135 config ARCH_HIBERNATION_HEADER
2137 depends on HIBERNATION
2139 config ARCH_SUSPEND_POSSIBLE
2144 menu "CPU Power Management"
2146 source "drivers/cpuidle/Kconfig"
2148 source "drivers/cpufreq/Kconfig"
2152 source "drivers/acpi/Kconfig"
2154 source "arch/arm64/kvm/Kconfig"
2157 source "arch/arm64/crypto/Kconfig"