1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_WX
13 select ARCH_BINFMT_ELF_STATE
14 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
15 select ARCH_ENABLE_MEMORY_HOTPLUG
16 select ARCH_ENABLE_MEMORY_HOTREMOVE
17 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
18 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
19 select ARCH_HAS_CACHE_LINE_SIZE
20 select ARCH_HAS_DEBUG_VIRTUAL
21 select ARCH_HAS_DEBUG_VM_PGTABLE
22 select ARCH_HAS_DMA_PREP_COHERENT
23 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
24 select ARCH_HAS_FAST_MULTIPLIER
25 select ARCH_HAS_FORTIFY_SOURCE
26 select ARCH_HAS_GCOV_PROFILE_ALL
27 select ARCH_HAS_GIGANTIC_PAGE
29 select ARCH_HAS_KEEPINITRD
30 select ARCH_HAS_MEMBARRIER_SYNC_CORE
31 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
32 select ARCH_HAS_PTE_DEVMAP
33 select ARCH_HAS_PTE_SPECIAL
34 select ARCH_HAS_SETUP_DMA_OPS
35 select ARCH_HAS_SET_DIRECT_MAP
36 select ARCH_HAS_SET_MEMORY
38 select ARCH_HAS_STRICT_KERNEL_RWX
39 select ARCH_HAS_STRICT_MODULE_RWX
40 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
41 select ARCH_HAS_SYNC_DMA_FOR_CPU
42 select ARCH_HAS_SYSCALL_WRAPPER
43 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
44 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
45 select ARCH_HAS_ZONE_DMA_SET if EXPERT
46 select ARCH_HAVE_ELF_PROT
47 select ARCH_HAVE_NMI_SAFE_CMPXCHG
48 select ARCH_INLINE_READ_LOCK if !PREEMPTION
49 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
50 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
51 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
52 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
53 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
54 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
55 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
56 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
57 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
58 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
59 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
60 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
61 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
62 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
63 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
64 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
65 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
66 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
67 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
68 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
69 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
70 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
71 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
72 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
73 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
74 select ARCH_KEEP_MEMBLOCK
75 select ARCH_USE_CMPXCHG_LOCKREF
76 select ARCH_USE_GNU_PROPERTY
77 select ARCH_USE_MEMTEST
78 select ARCH_USE_QUEUED_RWLOCKS
79 select ARCH_USE_QUEUED_SPINLOCKS
80 select ARCH_USE_SYM_ANNOTATIONS
81 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
82 select ARCH_SUPPORTS_HUGETLBFS
83 select ARCH_SUPPORTS_MEMORY_FAILURE
84 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
85 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
86 select ARCH_SUPPORTS_LTO_CLANG_THIN
87 select ARCH_SUPPORTS_CFI_CLANG
88 select ARCH_SUPPORTS_ATOMIC_RMW
89 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG)
90 select ARCH_SUPPORTS_NUMA_BALANCING
91 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
92 select ARCH_WANT_DEFAULT_BPF_JIT
93 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
94 select ARCH_WANT_FRAME_POINTERS
95 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
96 select ARCH_WANT_LD_ORPHAN_WARN
97 select ARCH_WANTS_NO_INSTR
98 select ARCH_HAS_UBSAN_SANITIZE_ALL
100 select ARM_ARCH_TIMER
102 select AUDIT_ARCH_COMPAT_GENERIC
103 select ARM_GIC_V2M if PCI
105 select ARM_GIC_V3_ITS if PCI
107 select BUILDTIME_TABLE_SORT
108 select CLONE_BACKWARDS
110 select CPU_PM if (SUSPEND || CPU_IDLE)
112 select DCACHE_WORD_ACCESS
113 select DMA_DIRECT_REMAP
116 select GENERIC_ALLOCATOR
117 select GENERIC_ARCH_TOPOLOGY
118 select GENERIC_CLOCKEVENTS_BROADCAST
119 select GENERIC_CPU_AUTOPROBE
120 select GENERIC_CPU_VULNERABILITIES
121 select GENERIC_EARLY_IOREMAP
122 select GENERIC_FIND_FIRST_BIT
123 select GENERIC_IDLE_POLL_SETUP
124 select GENERIC_IRQ_IPI
125 select GENERIC_IRQ_PROBE
126 select GENERIC_IRQ_SHOW
127 select GENERIC_IRQ_SHOW_LEVEL
128 select GENERIC_LIB_DEVMEM_IS_ALLOWED
129 select GENERIC_PCI_IOMAP
130 select GENERIC_PTDUMP
131 select GENERIC_SCHED_CLOCK
132 select GENERIC_SMP_IDLE_THREAD
133 select GENERIC_STRNCPY_FROM_USER
134 select GENERIC_STRNLEN_USER
135 select GENERIC_TIME_VSYSCALL
136 select GENERIC_GETTIMEOFDAY
137 select GENERIC_VDSO_TIME_NS
138 select HANDLE_DOMAIN_IRQ
139 select HARDIRQS_SW_RESEND
143 select HAVE_ACPI_APEI if (ACPI && EFI)
144 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
145 select HAVE_ARCH_AUDITSYSCALL
146 select HAVE_ARCH_BITREVERSE
147 select HAVE_ARCH_COMPILER_H
148 select HAVE_ARCH_HUGE_VMAP
149 select HAVE_ARCH_JUMP_LABEL
150 select HAVE_ARCH_JUMP_LABEL_RELATIVE
151 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
152 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
153 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
154 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
155 select HAVE_ARCH_KFENCE
156 select HAVE_ARCH_KGDB
157 select HAVE_ARCH_MMAP_RND_BITS
158 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
159 select HAVE_ARCH_PFN_VALID
160 select HAVE_ARCH_PREL32_RELOCATIONS
161 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
162 select HAVE_ARCH_SECCOMP_FILTER
163 select HAVE_ARCH_STACKLEAK
164 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
165 select HAVE_ARCH_TRACEHOOK
166 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
167 select HAVE_ARCH_VMAP_STACK
168 select HAVE_ARM_SMCCC
169 select HAVE_ASM_MODVERSIONS
171 select HAVE_C_RECORDMCOUNT
172 select HAVE_CMPXCHG_DOUBLE
173 select HAVE_CMPXCHG_LOCAL
174 select HAVE_CONTEXT_TRACKING
175 select HAVE_DEBUG_KMEMLEAK
176 select HAVE_DMA_CONTIGUOUS
177 select HAVE_DYNAMIC_FTRACE
178 select HAVE_DYNAMIC_FTRACE_WITH_REGS \
179 if $(cc-option,-fpatchable-function-entry=2)
180 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
181 if DYNAMIC_FTRACE_WITH_REGS
182 select HAVE_EFFICIENT_UNALIGNED_ACCESS
184 select HAVE_FTRACE_MCOUNT_RECORD
185 select HAVE_FUNCTION_TRACER
186 select HAVE_FUNCTION_ERROR_INJECTION
187 select HAVE_FUNCTION_GRAPH_TRACER
188 select HAVE_GCC_PLUGINS
189 select HAVE_HW_BREAKPOINT if PERF_EVENTS
190 select HAVE_IRQ_TIME_ACCOUNTING
192 select HAVE_PATA_PLATFORM
193 select HAVE_PERF_EVENTS
194 select HAVE_PERF_REGS
195 select HAVE_PERF_USER_STACK_DUMP
196 select HAVE_REGS_AND_STACK_ACCESS_API
197 select HAVE_FUNCTION_ARG_ACCESS_API
198 select HAVE_FUTEX_CMPXCHG if FUTEX
199 select MMU_GATHER_RCU_TABLE_FREE
201 select HAVE_STACKPROTECTOR
202 select HAVE_SYSCALL_TRACEPOINTS
204 select HAVE_KRETPROBES
205 select HAVE_GENERIC_VDSO
206 select IOMMU_DMA if IOMMU_SUPPORT
208 select IRQ_FORCED_THREADING
209 select KASAN_VMALLOC if KASAN_GENERIC
210 select MODULES_USE_ELF_RELA
211 select NEED_DMA_MAP_STATE
212 select NEED_SG_DMA_LENGTH
214 select OF_EARLY_FLATTREE
215 select PCI_DOMAINS_GENERIC if PCI
216 select PCI_ECAM if (ACPI && PCI)
217 select PCI_SYSCALL if PCI
222 select SYSCTL_EXCEPTION_TRACE
223 select THREAD_INFO_IN_TASK
224 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
226 ARM 64-bit (AArch64) Linux support.
234 config ARM64_PAGE_SHIFT
236 default 16 if ARM64_64K_PAGES
237 default 14 if ARM64_16K_PAGES
240 config ARM64_CONT_PTE_SHIFT
242 default 5 if ARM64_64K_PAGES
243 default 7 if ARM64_16K_PAGES
246 config ARM64_CONT_PMD_SHIFT
248 default 5 if ARM64_64K_PAGES
249 default 5 if ARM64_16K_PAGES
252 config ARCH_MMAP_RND_BITS_MIN
253 default 14 if ARM64_64K_PAGES
254 default 16 if ARM64_16K_PAGES
257 # max bits determined by the following formula:
258 # VA_BITS - PAGE_SHIFT - 3
259 config ARCH_MMAP_RND_BITS_MAX
260 default 19 if ARM64_VA_BITS=36
261 default 24 if ARM64_VA_BITS=39
262 default 27 if ARM64_VA_BITS=42
263 default 30 if ARM64_VA_BITS=47
264 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
265 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
266 default 33 if ARM64_VA_BITS=48
267 default 14 if ARM64_64K_PAGES
268 default 16 if ARM64_16K_PAGES
271 config ARCH_MMAP_RND_COMPAT_BITS_MIN
272 default 7 if ARM64_64K_PAGES
273 default 9 if ARM64_16K_PAGES
276 config ARCH_MMAP_RND_COMPAT_BITS_MAX
282 config STACKTRACE_SUPPORT
285 config ILLEGAL_POINTER_VALUE
287 default 0xdead000000000000
289 config LOCKDEP_SUPPORT
292 config TRACE_IRQFLAGS_SUPPORT
299 config GENERIC_BUG_RELATIVE_POINTERS
301 depends on GENERIC_BUG
303 config GENERIC_HWEIGHT
309 config GENERIC_CALIBRATE_DELAY
312 config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
318 config KERNEL_MODE_NEON
321 config FIX_EARLYCON_MEM
324 config PGTABLE_LEVELS
326 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
327 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
328 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
329 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
330 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
331 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
333 config ARCH_SUPPORTS_UPROBES
336 config ARCH_PROC_KCORE_TEXT
339 config BROKEN_GAS_INST
340 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
342 config KASAN_SHADOW_OFFSET
344 depends on KASAN_GENERIC || KASAN_SW_TAGS
345 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
346 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
347 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
348 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
349 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
350 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
351 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
352 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
353 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
354 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
355 default 0xffffffffffffffff
357 source "arch/arm64/Kconfig.platforms"
359 menu "Kernel Features"
361 menu "ARM errata workarounds via the alternatives framework"
363 config ARM64_WORKAROUND_CLEAN_CACHE
366 config ARM64_ERRATUM_826319
367 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
369 select ARM64_WORKAROUND_CLEAN_CACHE
371 This option adds an alternative code sequence to work around ARM
372 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
373 AXI master interface and an L2 cache.
375 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
376 and is unable to accept a certain write via this interface, it will
377 not progress on read data presented on the read data channel and the
380 The workaround promotes data cache clean instructions to
381 data cache clean-and-invalidate.
382 Please note that this does not necessarily enable the workaround,
383 as it depends on the alternative framework, which will only patch
384 the kernel if an affected CPU is detected.
388 config ARM64_ERRATUM_827319
389 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
391 select ARM64_WORKAROUND_CLEAN_CACHE
393 This option adds an alternative code sequence to work around ARM
394 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
395 master interface and an L2 cache.
397 Under certain conditions this erratum can cause a clean line eviction
398 to occur at the same time as another transaction to the same address
399 on the AMBA 5 CHI interface, which can cause data corruption if the
400 interconnect reorders the two transactions.
402 The workaround promotes data cache clean instructions to
403 data cache clean-and-invalidate.
404 Please note that this does not necessarily enable the workaround,
405 as it depends on the alternative framework, which will only patch
406 the kernel if an affected CPU is detected.
410 config ARM64_ERRATUM_824069
411 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
413 select ARM64_WORKAROUND_CLEAN_CACHE
415 This option adds an alternative code sequence to work around ARM
416 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
417 to a coherent interconnect.
419 If a Cortex-A53 processor is executing a store or prefetch for
420 write instruction at the same time as a processor in another
421 cluster is executing a cache maintenance operation to the same
422 address, then this erratum might cause a clean cache line to be
423 incorrectly marked as dirty.
425 The workaround promotes data cache clean instructions to
426 data cache clean-and-invalidate.
427 Please note that this option does not necessarily enable the
428 workaround, as it depends on the alternative framework, which will
429 only patch the kernel if an affected CPU is detected.
433 config ARM64_ERRATUM_819472
434 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
436 select ARM64_WORKAROUND_CLEAN_CACHE
438 This option adds an alternative code sequence to work around ARM
439 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
440 present when it is connected to a coherent interconnect.
442 If the processor is executing a load and store exclusive sequence at
443 the same time as a processor in another cluster is executing a cache
444 maintenance operation to the same address, then this erratum might
445 cause data corruption.
447 The workaround promotes data cache clean instructions to
448 data cache clean-and-invalidate.
449 Please note that this does not necessarily enable the workaround,
450 as it depends on the alternative framework, which will only patch
451 the kernel if an affected CPU is detected.
455 config ARM64_ERRATUM_832075
456 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
459 This option adds an alternative code sequence to work around ARM
460 erratum 832075 on Cortex-A57 parts up to r1p2.
462 Affected Cortex-A57 parts might deadlock when exclusive load/store
463 instructions to Write-Back memory are mixed with Device loads.
465 The workaround is to promote device loads to use Load-Acquire
467 Please note that this does not necessarily enable the workaround,
468 as it depends on the alternative framework, which will only patch
469 the kernel if an affected CPU is detected.
473 config ARM64_ERRATUM_834220
474 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
478 This option adds an alternative code sequence to work around ARM
479 erratum 834220 on Cortex-A57 parts up to r1p2.
481 Affected Cortex-A57 parts might report a Stage 2 translation
482 fault as the result of a Stage 1 fault for load crossing a
483 page boundary when there is a permission or device memory
484 alignment fault at Stage 1 and a translation fault at Stage 2.
486 The workaround is to verify that the Stage 1 translation
487 doesn't generate a fault before handling the Stage 2 fault.
488 Please note that this does not necessarily enable the workaround,
489 as it depends on the alternative framework, which will only patch
490 the kernel if an affected CPU is detected.
494 config ARM64_ERRATUM_845719
495 bool "Cortex-A53: 845719: a load might read incorrect data"
499 This option adds an alternative code sequence to work around ARM
500 erratum 845719 on Cortex-A53 parts up to r0p4.
502 When running a compat (AArch32) userspace on an affected Cortex-A53
503 part, a load at EL0 from a virtual address that matches the bottom 32
504 bits of the virtual address used by a recent load at (AArch64) EL1
505 might return incorrect data.
507 The workaround is to write the contextidr_el1 register on exception
508 return to a 32-bit task.
509 Please note that this does not necessarily enable the workaround,
510 as it depends on the alternative framework, which will only patch
511 the kernel if an affected CPU is detected.
515 config ARM64_ERRATUM_843419
516 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
518 select ARM64_MODULE_PLTS if MODULES
520 This option links the kernel with '--fix-cortex-a53-843419' and
521 enables PLT support to replace certain ADRP instructions, which can
522 cause subsequent memory accesses to use an incorrect address on
523 Cortex-A53 parts up to r0p4.
527 config ARM64_LD_HAS_FIX_ERRATUM_843419
528 def_bool $(ld-option,--fix-cortex-a53-843419)
530 config ARM64_ERRATUM_1024718
531 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
534 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
536 Affected Cortex-A55 cores (all revisions) could cause incorrect
537 update of the hardware dirty bit when the DBM/AP bits are updated
538 without a break-before-make. The workaround is to disable the usage
539 of hardware DBM locally on the affected cores. CPUs not affected by
540 this erratum will continue to use the feature.
544 config ARM64_ERRATUM_1418040
545 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
549 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
550 errata 1188873 and 1418040.
552 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
553 cause register corruption when accessing the timer registers
554 from AArch32 userspace.
558 config ARM64_WORKAROUND_SPECULATIVE_AT
561 config ARM64_ERRATUM_1165522
562 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
564 select ARM64_WORKAROUND_SPECULATIVE_AT
566 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
568 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
569 corrupted TLBs by speculating an AT instruction during a guest
574 config ARM64_ERRATUM_1319367
575 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
577 select ARM64_WORKAROUND_SPECULATIVE_AT
579 This option adds work arounds for ARM Cortex-A57 erratum 1319537
580 and A72 erratum 1319367
582 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
583 speculating an AT instruction during a guest context switch.
587 config ARM64_ERRATUM_1530923
588 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
590 select ARM64_WORKAROUND_SPECULATIVE_AT
592 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
594 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
595 corrupted TLBs by speculating an AT instruction during a guest
600 config ARM64_WORKAROUND_REPEAT_TLBI
603 config ARM64_ERRATUM_1286807
604 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
606 select ARM64_WORKAROUND_REPEAT_TLBI
608 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
610 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
611 address for a cacheable mapping of a location is being
612 accessed by a core while another core is remapping the virtual
613 address to a new physical page using the recommended
614 break-before-make sequence, then under very rare circumstances
615 TLBI+DSB completes before a read using the translation being
616 invalidated has been observed by other observers. The
617 workaround repeats the TLBI+DSB operation.
619 config ARM64_ERRATUM_1463225
620 bool "Cortex-A76: Software Step might prevent interrupt recognition"
623 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
625 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
626 of a system call instruction (SVC) can prevent recognition of
627 subsequent interrupts when software stepping is disabled in the
628 exception handler of the system call and either kernel debugging
629 is enabled or VHE is in use.
631 Work around the erratum by triggering a dummy step exception
632 when handling a system call from a task that is being stepped
633 in a VHE configuration of the kernel.
637 config ARM64_ERRATUM_1542419
638 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
641 This option adds a workaround for ARM Neoverse-N1 erratum
644 Affected Neoverse-N1 cores could execute a stale instruction when
645 modified by another CPU. The workaround depends on a firmware
648 Workaround the issue by hiding the DIC feature from EL0. This
649 forces user-space to perform cache maintenance.
653 config ARM64_ERRATUM_1508412
654 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
657 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
659 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
660 of a store-exclusive or read of PAR_EL1 and a load with device or
661 non-cacheable memory attributes. The workaround depends on a firmware
664 KVM guests must also have the workaround implemented or they can
667 Work around the issue by inserting DMB SY barriers around PAR_EL1
668 register reads and warning KVM users. The DMB barrier is sufficient
669 to prevent a speculative PAR_EL1 read.
673 config CAVIUM_ERRATUM_22375
674 bool "Cavium erratum 22375, 24313"
677 Enable workaround for errata 22375 and 24313.
679 This implements two gicv3-its errata workarounds for ThunderX. Both
680 with a small impact affecting only ITS table allocation.
682 erratum 22375: only alloc 8MB table size
683 erratum 24313: ignore memory access type
685 The fixes are in ITS initialization and basically ignore memory access
686 type and table size provided by the TYPER and BASER registers.
690 config CAVIUM_ERRATUM_23144
691 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
695 ITS SYNC command hang for cross node io and collections/cpu mapping.
699 config CAVIUM_ERRATUM_23154
700 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
703 The gicv3 of ThunderX requires a modified version for
704 reading the IAR status to ensure data synchronization
705 (access to icc_iar1_el1 is not sync'ed before and after).
709 config CAVIUM_ERRATUM_27456
710 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
713 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
714 instructions may cause the icache to become corrupted if it
715 contains data for a non-current ASID. The fix is to
716 invalidate the icache when changing the mm context.
720 config CAVIUM_ERRATUM_30115
721 bool "Cavium erratum 30115: Guest may disable interrupts in host"
724 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
725 1.2, and T83 Pass 1.0, KVM guest execution may disable
726 interrupts in host. Trapping both GICv3 group-0 and group-1
727 accesses sidesteps the issue.
731 config CAVIUM_TX2_ERRATUM_219
732 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
735 On Cavium ThunderX2, a load, store or prefetch instruction between a
736 TTBR update and the corresponding context synchronizing operation can
737 cause a spurious Data Abort to be delivered to any hardware thread in
740 Work around the issue by avoiding the problematic code sequence and
741 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
742 trap handler performs the corresponding register access, skips the
743 instruction and ensures context synchronization by virtue of the
748 config FUJITSU_ERRATUM_010001
749 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
752 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
753 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
754 accesses may cause undefined fault (Data abort, DFSC=0b111111).
755 This fault occurs under a specific hardware condition when a
756 load/store instruction performs an address translation using:
757 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
758 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
759 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
760 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
762 The workaround is to ensure these bits are clear in TCR_ELx.
763 The workaround only affects the Fujitsu-A64FX.
767 config HISILICON_ERRATUM_161600802
768 bool "Hip07 161600802: Erroneous redistributor VLPI base"
771 The HiSilicon Hip07 SoC uses the wrong redistributor base
772 when issued ITS commands such as VMOVP and VMAPP, and requires
773 a 128kB offset to be applied to the target address in this commands.
777 config QCOM_FALKOR_ERRATUM_1003
778 bool "Falkor E1003: Incorrect translation due to ASID change"
781 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
782 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
783 in TTBR1_EL1, this situation only occurs in the entry trampoline and
784 then only for entries in the walk cache, since the leaf translation
785 is unchanged. Work around the erratum by invalidating the walk cache
786 entries for the trampoline before entering the kernel proper.
788 config QCOM_FALKOR_ERRATUM_1009
789 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
791 select ARM64_WORKAROUND_REPEAT_TLBI
793 On Falkor v1, the CPU may prematurely complete a DSB following a
794 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
795 one more time to fix the issue.
799 config QCOM_QDF2400_ERRATUM_0065
800 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
803 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
804 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
805 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
809 config QCOM_FALKOR_ERRATUM_E1041
810 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
813 Falkor CPU may speculatively fetch instructions from an improper
814 memory location when MMU translation is changed from SCTLR_ELn[M]=1
815 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
819 config NVIDIA_CARMEL_CNP_ERRATUM
820 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
823 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
824 invalidate shared TLB entries installed by a different core, as it would
825 on standard ARM cores.
829 config SOCIONEXT_SYNQUACER_PREITS
830 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
833 Socionext Synquacer SoCs implement a separate h/w block to generate
834 MSI doorbell writes with non-zero values for the device ID.
843 default ARM64_4K_PAGES
845 Page size (translation granule) configuration.
847 config ARM64_4K_PAGES
850 This feature enables 4KB pages support.
852 config ARM64_16K_PAGES
855 The system will use 16KB pages support. AArch32 emulation
856 requires applications compiled with 16K (or a multiple of 16K)
859 config ARM64_64K_PAGES
862 This feature enables 64KB pages support (4KB by default)
863 allowing only two levels of page tables and faster TLB
864 look-up. AArch32 emulation requires applications compiled
865 with 64K aligned segments.
870 prompt "Virtual address space size"
871 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
872 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
873 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
875 Allows choosing one of multiple possible virtual address
876 space sizes. The level of translation table is determined by
877 a combination of page size and virtual address space size.
879 config ARM64_VA_BITS_36
880 bool "36-bit" if EXPERT
881 depends on ARM64_16K_PAGES
883 config ARM64_VA_BITS_39
885 depends on ARM64_4K_PAGES
887 config ARM64_VA_BITS_42
889 depends on ARM64_64K_PAGES
891 config ARM64_VA_BITS_47
893 depends on ARM64_16K_PAGES
895 config ARM64_VA_BITS_48
898 config ARM64_VA_BITS_52
900 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
902 Enable 52-bit virtual addressing for userspace when explicitly
903 requested via a hint to mmap(). The kernel will also use 52-bit
904 virtual addresses for its own mappings (provided HW support for
905 this feature is available, otherwise it reverts to 48-bit).
907 NOTE: Enabling 52-bit virtual addressing in conjunction with
908 ARMv8.3 Pointer Authentication will result in the PAC being
909 reduced from 7 bits to 3 bits, which may have a significant
910 impact on its susceptibility to brute-force attacks.
912 If unsure, select 48-bit virtual addressing instead.
916 config ARM64_FORCE_52BIT
917 bool "Force 52-bit virtual addresses for userspace"
918 depends on ARM64_VA_BITS_52 && EXPERT
920 For systems with 52-bit userspace VAs enabled, the kernel will attempt
921 to maintain compatibility with older software by providing 48-bit VAs
922 unless a hint is supplied to mmap.
924 This configuration option disables the 48-bit compatibility logic, and
925 forces all userspace addresses to be 52-bit on HW that supports it. One
926 should only enable this configuration option for stress testing userspace
927 memory management code. If unsure say N here.
931 default 36 if ARM64_VA_BITS_36
932 default 39 if ARM64_VA_BITS_39
933 default 42 if ARM64_VA_BITS_42
934 default 47 if ARM64_VA_BITS_47
935 default 48 if ARM64_VA_BITS_48
936 default 52 if ARM64_VA_BITS_52
939 prompt "Physical address space size"
940 default ARM64_PA_BITS_48
942 Choose the maximum physical address range that the kernel will
945 config ARM64_PA_BITS_48
948 config ARM64_PA_BITS_52
949 bool "52-bit (ARMv8.2)"
950 depends on ARM64_64K_PAGES
951 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
953 Enable support for a 52-bit physical address space, introduced as
954 part of the ARMv8.2-LPA extension.
956 With this enabled, the kernel will also continue to work on CPUs that
957 do not support ARMv8.2-LPA, but with some added memory overhead (and
958 minor performance overhead).
964 default 48 if ARM64_PA_BITS_48
965 default 52 if ARM64_PA_BITS_52
969 default CPU_LITTLE_ENDIAN
971 Select the endianness of data accesses performed by the CPU. Userspace
972 applications will need to be compiled and linked for the endianness
973 that is selected here.
975 config CPU_BIG_ENDIAN
976 bool "Build big-endian kernel"
977 depends on !LD_IS_LLD || LLD_VERSION >= 130000
979 Say Y if you plan on running a kernel with a big-endian userspace.
981 config CPU_LITTLE_ENDIAN
982 bool "Build little-endian kernel"
984 Say Y if you plan on running a kernel with a little-endian userspace.
985 This is usually the case for distributions targeting arm64.
990 bool "Multi-core scheduler support"
992 Multi-core scheduler support improves the CPU scheduler's decision
993 making when dealing with multi-core CPU chips at a cost of slightly
994 increased overhead in some places. If unsure say N here.
997 bool "SMT scheduler support"
999 Improves the CPU scheduler's decision making when dealing with
1000 MultiThreading at a cost of slightly increased overhead in some
1001 places. If unsure say N here.
1004 int "Maximum number of CPUs (2-4096)"
1009 bool "Support for hot-pluggable CPUs"
1010 select GENERIC_IRQ_MIGRATION
1012 Say Y here to experiment with turning CPUs off and on. CPUs
1013 can be controlled through /sys/devices/system/cpu.
1015 # Common NUMA Features
1017 bool "NUMA Memory Allocation and Scheduler Support"
1018 select GENERIC_ARCH_NUMA
1019 select ACPI_NUMA if ACPI
1022 Enable NUMA (Non-Uniform Memory Access) support.
1024 The kernel will try to allocate memory used by a CPU on the
1025 local memory of the CPU and add some more
1026 NUMA awareness to the kernel.
1029 int "Maximum NUMA Nodes (as a power of 2)"
1034 Specify the maximum number of NUMA Nodes available on the target
1035 system. Increases memory reserved to accommodate various tables.
1037 config USE_PERCPU_NUMA_NODE_ID
1041 config HAVE_SETUP_PER_CPU_AREA
1045 config NEED_PER_CPU_EMBED_FIRST_CHUNK
1049 source "kernel/Kconfig.hz"
1051 config ARCH_SPARSEMEM_ENABLE
1053 select SPARSEMEM_VMEMMAP_ENABLE
1054 select SPARSEMEM_VMEMMAP
1056 config HW_PERF_EVENTS
1060 config ARCH_HAS_FILTER_PGPROT
1063 # Supported by clang >= 7.0
1064 config CC_HAVE_SHADOW_CALL_STACK
1065 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1068 bool "Enable paravirtualization code"
1070 This changes the kernel so it can modify itself when it is run
1071 under a hypervisor, potentially improving performance significantly
1072 over full virtualization.
1074 config PARAVIRT_TIME_ACCOUNTING
1075 bool "Paravirtual steal time accounting"
1078 Select this option to enable fine granularity task steal time
1079 accounting. Time spent executing other tasks in parallel with
1080 the current vCPU is discounted from the vCPU power. To account for
1081 that, there can be a small performance impact.
1083 If in doubt, say N here.
1086 depends on PM_SLEEP_SMP
1088 bool "kexec system call"
1090 kexec is a system call that implements the ability to shutdown your
1091 current kernel, and to start another kernel. It is like a reboot
1092 but it is independent of the system firmware. And like a reboot
1093 you can start any kernel with it, not just Linux.
1096 bool "kexec file based system call"
1098 select HAVE_IMA_KEXEC if IMA
1100 This is new version of kexec system call. This system call is
1101 file based and takes file descriptors as system call argument
1102 for kernel and initramfs as opposed to list of segments as
1103 accepted by previous system call.
1106 bool "Verify kernel signature during kexec_file_load() syscall"
1107 depends on KEXEC_FILE
1109 Select this option to verify a signature with loaded kernel
1110 image. If configured, any attempt of loading a image without
1111 valid signature will fail.
1113 In addition to that option, you need to enable signature
1114 verification for the corresponding kernel image type being
1115 loaded in order for this to work.
1117 config KEXEC_IMAGE_VERIFY_SIG
1118 bool "Enable Image signature verification support"
1120 depends on KEXEC_SIG
1121 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1123 Enable Image signature verification support.
1125 comment "Support for PE file signature verification disabled"
1126 depends on KEXEC_SIG
1127 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1130 bool "Build kdump crash kernel"
1132 Generate crash dump after being started by kexec. This should
1133 be normally only set in special crash dump kernels which are
1134 loaded in the main kernel with kexec-tools into a specially
1135 reserved region and then later executed after a crash by
1138 For more details see Documentation/admin-guide/kdump/kdump.rst
1142 depends on HIBERNATION
1149 bool "Xen guest support on ARM64"
1150 depends on ARM64 && OF
1154 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1156 config FORCE_MAX_ZONEORDER
1158 default "14" if ARM64_64K_PAGES
1159 default "12" if ARM64_16K_PAGES
1162 The kernel memory allocator divides physically contiguous memory
1163 blocks into "zones", where each zone is a power of two number of
1164 pages. This option selects the largest power of two that the kernel
1165 keeps in the memory allocator. If you need to allocate very large
1166 blocks of physically contiguous memory, then you may need to
1167 increase this value.
1169 This config option is actually maximum order plus one. For example,
1170 a value of 11 means that the largest free memory block is 2^10 pages.
1172 We make sure that we can allocate upto a HugePage size for each configuration.
1174 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1176 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1177 4M allocations matching the default size used by generic code.
1179 config UNMAP_KERNEL_AT_EL0
1180 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1183 Speculation attacks against some high-performance processors can
1184 be used to bypass MMU permission checks and leak kernel data to
1185 userspace. This can be defended against by unmapping the kernel
1186 when running in userspace, mapping it back in on exception entry
1187 via a trampoline page in the vector table.
1191 config RODATA_FULL_DEFAULT_ENABLED
1192 bool "Apply r/o permissions of VM areas also to their linear aliases"
1195 Apply read-only attributes of VM areas to the linear alias of
1196 the backing pages as well. This prevents code or read-only data
1197 from being modified (inadvertently or intentionally) via another
1198 mapping of the same memory page. This additional enhancement can
1199 be turned off at runtime by passing rodata=[off|on] (and turned on
1200 with rodata=full if this option is set to 'n')
1202 This requires the linear region to be mapped down to pages,
1203 which may adversely affect performance in some cases.
1205 config ARM64_SW_TTBR0_PAN
1206 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1208 Enabling this option prevents the kernel from accessing
1209 user-space memory directly by pointing TTBR0_EL1 to a reserved
1210 zeroed area and reserved ASID. The user access routines
1211 restore the valid TTBR0_EL1 temporarily.
1213 config ARM64_TAGGED_ADDR_ABI
1214 bool "Enable the tagged user addresses syscall ABI"
1217 When this option is enabled, user applications can opt in to a
1218 relaxed ABI via prctl() allowing tagged addresses to be passed
1219 to system calls as pointer arguments. For details, see
1220 Documentation/arm64/tagged-address-abi.rst.
1223 bool "Kernel support for 32-bit EL0"
1224 depends on ARM64_4K_PAGES || EXPERT
1226 select OLD_SIGSUSPEND3
1227 select COMPAT_OLD_SIGACTION
1229 This option enables support for a 32-bit EL0 running under a 64-bit
1230 kernel at EL1. AArch32-specific components such as system calls,
1231 the user helper functions, VFP support and the ptrace interface are
1232 handled appropriately by the kernel.
1234 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1235 that you will only be able to execute AArch32 binaries that were compiled
1236 with page size aligned segments.
1238 If you want to execute 32-bit userspace applications, say Y.
1242 config KUSER_HELPERS
1243 bool "Enable kuser helpers page for 32-bit applications"
1246 Warning: disabling this option may break 32-bit user programs.
1248 Provide kuser helpers to compat tasks. The kernel provides
1249 helper code to userspace in read only form at a fixed location
1250 to allow userspace to be independent of the CPU type fitted to
1251 the system. This permits binaries to be run on ARMv4 through
1252 to ARMv8 without modification.
1254 See Documentation/arm/kernel_user_helpers.rst for details.
1256 However, the fixed address nature of these helpers can be used
1257 by ROP (return orientated programming) authors when creating
1260 If all of the binaries and libraries which run on your platform
1261 are built specifically for your platform, and make no use of
1262 these helpers, then you can turn this option off to hinder
1263 such exploits. However, in that case, if a binary or library
1264 relying on those helpers is run, it will not function correctly.
1266 Say N here only if you are absolutely certain that you do not
1267 need these helpers; otherwise, the safe option is to say Y.
1270 bool "Enable vDSO for 32-bit applications"
1271 depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1272 select GENERIC_COMPAT_VDSO
1275 Place in the process address space of 32-bit applications an
1276 ELF shared object providing fast implementations of gettimeofday
1279 You must have a 32-bit build of glibc 2.22 or later for programs
1280 to seamlessly take advantage of this.
1282 config THUMB2_COMPAT_VDSO
1283 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1284 depends on COMPAT_VDSO
1287 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1288 otherwise with '-marm'.
1290 menuconfig ARMV8_DEPRECATED
1291 bool "Emulate deprecated/obsolete ARMv8 instructions"
1294 Legacy software support may require certain instructions
1295 that have been deprecated or obsoleted in the architecture.
1297 Enable this config to enable selective emulation of these
1304 config SWP_EMULATION
1305 bool "Emulate SWP/SWPB instructions"
1307 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1308 they are always undefined. Say Y here to enable software
1309 emulation of these instructions for userspace using LDXR/STXR.
1310 This feature can be controlled at runtime with the abi.swp
1311 sysctl which is disabled by default.
1313 In some older versions of glibc [<=2.8] SWP is used during futex
1314 trylock() operations with the assumption that the code will not
1315 be preempted. This invalid assumption may be more likely to fail
1316 with SWP emulation enabled, leading to deadlock of the user
1319 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1320 on an external transaction monitoring block called a global
1321 monitor to maintain update atomicity. If your system does not
1322 implement a global monitor, this option can cause programs that
1323 perform SWP operations to uncached memory to deadlock.
1327 config CP15_BARRIER_EMULATION
1328 bool "Emulate CP15 Barrier instructions"
1330 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1331 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1332 strongly recommended to use the ISB, DSB, and DMB
1333 instructions instead.
1335 Say Y here to enable software emulation of these
1336 instructions for AArch32 userspace code. When this option is
1337 enabled, CP15 barrier usage is traced which can help
1338 identify software that needs updating. This feature can be
1339 controlled at runtime with the abi.cp15_barrier sysctl.
1343 config SETEND_EMULATION
1344 bool "Emulate SETEND instruction"
1346 The SETEND instruction alters the data-endianness of the
1347 AArch32 EL0, and is deprecated in ARMv8.
1349 Say Y here to enable software emulation of the instruction
1350 for AArch32 userspace code. This feature can be controlled
1351 at runtime with the abi.setend sysctl.
1353 Note: All the cpus on the system must have mixed endian support at EL0
1354 for this feature to be enabled. If a new CPU - which doesn't support mixed
1355 endian - is hotplugged in after this feature has been enabled, there could
1356 be unexpected results in the applications.
1363 menu "ARMv8.1 architectural features"
1365 config ARM64_HW_AFDBM
1366 bool "Support for hardware updates of the Access and Dirty page flags"
1369 The ARMv8.1 architecture extensions introduce support for
1370 hardware updates of the access and dirty information in page
1371 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1372 capable processors, accesses to pages with PTE_AF cleared will
1373 set this bit instead of raising an access flag fault.
1374 Similarly, writes to read-only pages with the DBM bit set will
1375 clear the read-only bit (AP[2]) instead of raising a
1378 Kernels built with this configuration option enabled continue
1379 to work on pre-ARMv8.1 hardware and the performance impact is
1380 minimal. If unsure, say Y.
1383 bool "Enable support for Privileged Access Never (PAN)"
1386 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1387 prevents the kernel or hypervisor from accessing user-space (EL0)
1390 Choosing this option will cause any unprotected (not using
1391 copy_to_user et al) memory access to fail with a permission fault.
1393 The feature is detected at runtime, and will remain as a 'nop'
1394 instruction if the cpu does not implement the feature.
1397 def_bool $(as-instr,.arch_extension rcpc)
1399 config AS_HAS_LSE_ATOMICS
1400 def_bool $(as-instr,.arch_extension lse)
1402 config ARM64_LSE_ATOMICS
1404 default ARM64_USE_LSE_ATOMICS
1405 depends on AS_HAS_LSE_ATOMICS
1407 config ARM64_USE_LSE_ATOMICS
1408 bool "Atomic instructions"
1409 depends on JUMP_LABEL
1412 As part of the Large System Extensions, ARMv8.1 introduces new
1413 atomic instructions that are designed specifically to scale in
1416 Say Y here to make use of these instructions for the in-kernel
1417 atomic routines. This incurs a small overhead on CPUs that do
1418 not support these instructions and requires the kernel to be
1419 built with binutils >= 2.25 in order for the new instructions
1424 menu "ARMv8.2 architectural features"
1427 bool "Enable support for persistent memory"
1428 select ARCH_HAS_PMEM_API
1429 select ARCH_HAS_UACCESS_FLUSHCACHE
1431 Say Y to enable support for the persistent memory API based on the
1432 ARMv8.2 DCPoP feature.
1434 The feature is detected at runtime, and the kernel will use DC CVAC
1435 operations if DC CVAP is not supported (following the behaviour of
1436 DC CVAP itself if the system does not define a point of persistence).
1438 config ARM64_RAS_EXTN
1439 bool "Enable support for RAS CPU Extensions"
1442 CPUs that support the Reliability, Availability and Serviceability
1443 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1444 errors, classify them and report them to software.
1446 On CPUs with these extensions system software can use additional
1447 barriers to determine if faults are pending and read the
1448 classification from a new set of registers.
1450 Selecting this feature will allow the kernel to use these barriers
1451 and access the new registers if the system supports the extension.
1452 Platform RAS features may additionally depend on firmware support.
1455 bool "Enable support for Common Not Private (CNP) translations"
1457 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1459 Common Not Private (CNP) allows translation table entries to
1460 be shared between different PEs in the same inner shareable
1461 domain, so the hardware can use this fact to optimise the
1462 caching of such entries in the TLB.
1464 Selecting this option allows the CNP feature to be detected
1465 at runtime, and does not affect PEs that do not implement
1470 menu "ARMv8.3 architectural features"
1472 config ARM64_PTR_AUTH
1473 bool "Enable support for pointer authentication"
1476 Pointer authentication (part of the ARMv8.3 Extensions) provides
1477 instructions for signing and authenticating pointers against secret
1478 keys, which can be used to mitigate Return Oriented Programming (ROP)
1481 This option enables these instructions at EL0 (i.e. for userspace).
1482 Choosing this option will cause the kernel to initialise secret keys
1483 for each process at exec() time, with these keys being
1484 context-switched along with the process.
1486 The feature is detected at runtime. If the feature is not present in
1487 hardware it will not be advertised to userspace/KVM guest nor will it
1490 If the feature is present on the boot CPU but not on a late CPU, then
1491 the late CPU will be parked. Also, if the boot CPU does not have
1492 address auth and the late CPU has then the late CPU will still boot
1493 but with the feature disabled. On such a system, this option should
1496 config ARM64_PTR_AUTH_KERNEL
1497 bool "Use pointer authentication for kernel"
1499 depends on ARM64_PTR_AUTH
1500 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1501 # Modern compilers insert a .note.gnu.property section note for PAC
1502 # which is only understood by binutils starting with version 2.33.1.
1503 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1504 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1505 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1507 If the compiler supports the -mbranch-protection or
1508 -msign-return-address flag (e.g. GCC 7 or later), then this option
1509 will cause the kernel itself to be compiled with return address
1510 protection. In this case, and if the target hardware is known to
1511 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1512 disabled with minimal loss of protection.
1514 This feature works with FUNCTION_GRAPH_TRACER option only if
1515 DYNAMIC_FTRACE_WITH_REGS is enabled.
1517 config CC_HAS_BRANCH_PROT_PAC_RET
1518 # GCC 9 or later, clang 8 or later
1519 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1521 config CC_HAS_SIGN_RETURN_ADDRESS
1523 def_bool $(cc-option,-msign-return-address=all)
1526 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1528 config AS_HAS_CFI_NEGATE_RA_STATE
1529 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1533 menu "ARMv8.4 architectural features"
1535 config ARM64_AMU_EXTN
1536 bool "Enable support for the Activity Monitors Unit CPU extension"
1539 The activity monitors extension is an optional extension introduced
1540 by the ARMv8.4 CPU architecture. This enables support for version 1
1541 of the activity monitors architecture, AMUv1.
1543 To enable the use of this extension on CPUs that implement it, say Y.
1545 Note that for architectural reasons, firmware _must_ implement AMU
1546 support when running on CPUs that present the activity monitors
1547 extension. The required support is present in:
1548 * Version 1.5 and later of the ARM Trusted Firmware
1550 For kernels that have this configuration enabled but boot with broken
1551 firmware, you may need to say N here until the firmware is fixed.
1552 Otherwise you may experience firmware panics or lockups when
1553 accessing the counter registers. Even if you are not observing these
1554 symptoms, the values returned by the register reads might not
1555 correctly reflect reality. Most commonly, the value read will be 0,
1556 indicating that the counter is not enabled.
1558 config AS_HAS_ARMV8_4
1559 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1561 config ARM64_TLB_RANGE
1562 bool "Enable support for tlbi range feature"
1564 depends on AS_HAS_ARMV8_4
1566 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1567 range of input addresses.
1569 The feature introduces new assembly instructions, and they were
1570 support when binutils >= 2.30.
1574 menu "ARMv8.5 architectural features"
1576 config AS_HAS_ARMV8_5
1577 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1580 bool "Branch Target Identification support"
1583 Branch Target Identification (part of the ARMv8.5 Extensions)
1584 provides a mechanism to limit the set of locations to which computed
1585 branch instructions such as BR or BLR can jump.
1587 To make use of BTI on CPUs that support it, say Y.
1589 BTI is intended to provide complementary protection to other control
1590 flow integrity protection mechanisms, such as the Pointer
1591 authentication mechanism provided as part of the ARMv8.3 Extensions.
1592 For this reason, it does not make sense to enable this option without
1593 also enabling support for pointer authentication. Thus, when
1594 enabling this option you should also select ARM64_PTR_AUTH=y.
1596 Userspace binaries must also be specifically compiled to make use of
1597 this mechanism. If you say N here or the hardware does not support
1598 BTI, such binaries can still run, but you get no additional
1599 enforcement of branch destinations.
1601 config ARM64_BTI_KERNEL
1602 bool "Use Branch Target Identification for kernel"
1604 depends on ARM64_BTI
1605 depends on ARM64_PTR_AUTH_KERNEL
1606 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1607 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1608 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1609 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1610 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
1611 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1613 Build the kernel with Branch Target Identification annotations
1614 and enable enforcement of this for kernel code. When this option
1615 is enabled and the system supports BTI all kernel code including
1616 modular code must have BTI enabled.
1618 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1619 # GCC 9 or later, clang 8 or later
1620 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1623 bool "Enable support for E0PD"
1626 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1627 that EL0 accesses made via TTBR1 always fault in constant time,
1628 providing similar benefits to KASLR as those provided by KPTI, but
1629 with lower overhead and without disrupting legitimate access to
1630 kernel memory such as SPE.
1632 This option enables E0PD for TTBR1 where available.
1635 bool "Enable support for random number generation"
1638 Random number generation (part of the ARMv8.5 Extensions)
1639 provides a high bandwidth, cryptographically secure
1640 hardware random number generator.
1642 config ARM64_AS_HAS_MTE
1643 # Initial support for MTE went in binutils 2.32.0, checked with
1644 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1645 # as a late addition to the final architecture spec (LDGM/STGM)
1646 # is only supported in the newer 2.32.x and 2.33 binutils
1647 # versions, hence the extra "stgm" instruction check below.
1648 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1651 bool "Memory Tagging Extension support"
1653 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1654 depends on AS_HAS_ARMV8_5
1655 depends on AS_HAS_LSE_ATOMICS
1656 # Required for tag checking in the uaccess routines
1657 depends on ARM64_PAN
1658 select ARCH_USES_HIGH_VMA_FLAGS
1660 Memory Tagging (part of the ARMv8.5 Extensions) provides
1661 architectural support for run-time, always-on detection of
1662 various classes of memory error to aid with software debugging
1663 to eliminate vulnerabilities arising from memory-unsafe
1666 This option enables the support for the Memory Tagging
1667 Extension at EL0 (i.e. for userspace).
1669 Selecting this option allows the feature to be detected at
1670 runtime. Any secondary CPU not implementing this feature will
1671 not be allowed a late bring-up.
1673 Userspace binaries that want to use this feature must
1674 explicitly opt in. The mechanism for the userspace is
1677 Documentation/arm64/memory-tagging-extension.rst.
1681 menu "ARMv8.7 architectural features"
1684 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
1686 depends on ARM64_PAN
1688 Enhanced Privileged Access Never (EPAN) allows Privileged
1689 Access Never to be used with Execute-only mappings.
1691 The feature is detected at runtime, and will remain disabled
1692 if the cpu does not implement the feature.
1696 bool "ARM Scalable Vector Extension support"
1699 The Scalable Vector Extension (SVE) is an extension to the AArch64
1700 execution state which complements and extends the SIMD functionality
1701 of the base architecture to support much larger vectors and to enable
1702 additional vectorisation opportunities.
1704 To enable use of this extension on CPUs that implement it, say Y.
1706 On CPUs that support the SVE2 extensions, this option will enable
1709 Note that for architectural reasons, firmware _must_ implement SVE
1710 support when running on SVE capable hardware. The required support
1713 * version 1.5 and later of the ARM Trusted Firmware
1714 * the AArch64 boot wrapper since commit 5e1261e08abf
1715 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1717 For other firmware implementations, consult the firmware documentation
1720 If you need the kernel to boot on SVE-capable hardware with broken
1721 firmware, you may need to say N here until you get your firmware
1722 fixed. Otherwise, you may experience firmware panics or lockups when
1723 booting the kernel. If unsure and you are not observing these
1724 symptoms, you should assume that it is safe to say Y.
1726 config ARM64_MODULE_PLTS
1727 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1729 select HAVE_MOD_ARCH_SPECIFIC
1731 Allocate PLTs when loading modules so that jumps and calls whose
1732 targets are too far away for their relative offsets to be encoded
1733 in the instructions themselves can be bounced via veneers in the
1734 module's PLT. This allows modules to be allocated in the generic
1735 vmalloc area after the dedicated module memory area has been
1738 When running with address space randomization (KASLR), the module
1739 region itself may be too far away for ordinary relative jumps and
1740 calls, and so in that case, module PLTs are required and cannot be
1743 Specific errata workaround(s) might also force module PLTs to be
1744 enabled (ARM64_ERRATUM_843419).
1746 config ARM64_PSEUDO_NMI
1747 bool "Support for NMI-like interrupts"
1750 Adds support for mimicking Non-Maskable Interrupts through the use of
1751 GIC interrupt priority. This support requires version 3 or later of
1754 This high priority configuration for interrupts needs to be
1755 explicitly enabled by setting the kernel parameter
1756 "irqchip.gicv3_pseudo_nmi" to 1.
1761 config ARM64_DEBUG_PRIORITY_MASKING
1762 bool "Debug interrupt priority masking"
1764 This adds runtime checks to functions enabling/disabling
1765 interrupts when using priority masking. The additional checks verify
1766 the validity of ICC_PMR_EL1 when calling concerned functions.
1772 bool "Build a relocatable kernel image" if EXPERT
1773 select ARCH_HAS_RELR
1776 This builds the kernel as a Position Independent Executable (PIE),
1777 which retains all relocation metadata required to relocate the
1778 kernel binary at runtime to a different virtual address than the
1779 address it was linked at.
1780 Since AArch64 uses the RELA relocation format, this requires a
1781 relocation pass at runtime even if the kernel is loaded at the
1782 same address it was linked at.
1784 config RANDOMIZE_BASE
1785 bool "Randomize the address of the kernel image"
1786 select ARM64_MODULE_PLTS if MODULES
1789 Randomizes the virtual address at which the kernel image is
1790 loaded, as a security feature that deters exploit attempts
1791 relying on knowledge of the location of kernel internals.
1793 It is the bootloader's job to provide entropy, by passing a
1794 random u64 value in /chosen/kaslr-seed at kernel entry.
1796 When booting via the UEFI stub, it will invoke the firmware's
1797 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1798 to the kernel proper. In addition, it will randomise the physical
1799 location of the kernel Image as well.
1803 config RANDOMIZE_MODULE_REGION_FULL
1804 bool "Randomize the module region over a 2 GB range"
1805 depends on RANDOMIZE_BASE
1808 Randomizes the location of the module region inside a 2 GB window
1809 covering the core kernel. This way, it is less likely for modules
1810 to leak information about the location of core kernel data structures
1811 but it does imply that function calls between modules and the core
1812 kernel will need to be resolved via veneers in the module PLT.
1814 When this option is not set, the module region will be randomized over
1815 a limited range that contains the [_stext, _etext] interval of the
1816 core kernel, so branch relocations are almost always in range unless
1817 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this
1818 particular case of region exhaustion, modules might be able to fall
1819 back to a larger 2GB area.
1821 config CC_HAVE_STACKPROTECTOR_SYSREG
1822 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1824 config STACKPROTECTOR_PER_TASK
1826 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1832 config ARM64_ACPI_PARKING_PROTOCOL
1833 bool "Enable support for the ARM64 ACPI parking protocol"
1836 Enable support for the ARM64 ACPI parking protocol. If disabled
1837 the kernel will not allow booting through the ARM64 ACPI parking
1838 protocol even if the corresponding data is present in the ACPI
1842 string "Default kernel command string"
1845 Provide a set of default command-line options at build time by
1846 entering them here. As a minimum, you should specify the the
1847 root device (e.g. root=/dev/nfs).
1850 prompt "Kernel command line type" if CMDLINE != ""
1851 default CMDLINE_FROM_BOOTLOADER
1853 Choose how the kernel will handle the provided default kernel
1854 command line string.
1856 config CMDLINE_FROM_BOOTLOADER
1857 bool "Use bootloader kernel arguments if available"
1859 Uses the command-line options passed by the boot loader. If
1860 the boot loader doesn't provide any, the default kernel command
1861 string provided in CMDLINE will be used.
1863 config CMDLINE_FORCE
1864 bool "Always use the default kernel command string"
1866 Always use the default kernel command string, even if the boot
1867 loader passes other arguments to the kernel.
1868 This is useful if you cannot or don't want to change the
1869 command-line options your boot loader passes to the kernel.
1877 bool "UEFI runtime support"
1878 depends on OF && !CPU_BIG_ENDIAN
1879 depends on KERNEL_MODE_NEON
1880 select ARCH_SUPPORTS_ACPI
1883 select EFI_PARAMS_FROM_FDT
1884 select EFI_RUNTIME_WRAPPERS
1886 select EFI_GENERIC_STUB
1887 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
1890 This option provides support for runtime services provided
1891 by UEFI firmware (such as non-volatile variables, realtime
1892 clock, and platform reset). A UEFI stub is also provided to
1893 allow the kernel to be booted as an EFI application. This
1894 is only useful on systems that have UEFI firmware.
1897 bool "Enable support for SMBIOS (DMI) tables"
1901 This enables SMBIOS/DMI feature for systems.
1903 This option is only useful on systems that have UEFI firmware.
1904 However, even with this option, the resultant kernel should
1905 continue to boot on existing non-UEFI platforms.
1909 config SYSVIPC_COMPAT
1911 depends on COMPAT && SYSVIPC
1913 menu "Power management options"
1915 source "kernel/power/Kconfig"
1917 config ARCH_HIBERNATION_POSSIBLE
1921 config ARCH_HIBERNATION_HEADER
1923 depends on HIBERNATION
1925 config ARCH_SUSPEND_POSSIBLE
1930 menu "CPU Power Management"
1932 source "drivers/cpuidle/Kconfig"
1934 source "drivers/cpufreq/Kconfig"
1938 source "drivers/firmware/Kconfig"
1940 source "drivers/acpi/Kconfig"
1942 source "arch/arm64/kvm/Kconfig"
1945 source "arch/arm64/crypto/Kconfig"