1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_WX
13 select ARCH_BINFMT_ELF_STATE
14 select ARCH_HAS_DEBUG_VIRTUAL
15 select ARCH_HAS_DEBUG_VM_PGTABLE
16 select ARCH_HAS_DMA_PREP_COHERENT
17 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
18 select ARCH_HAS_FAST_MULTIPLIER
19 select ARCH_HAS_FORTIFY_SOURCE
20 select ARCH_HAS_GCOV_PROFILE_ALL
21 select ARCH_HAS_GIGANTIC_PAGE
23 select ARCH_HAS_KEEPINITRD
24 select ARCH_HAS_MEMBARRIER_SYNC_CORE
25 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
26 select ARCH_HAS_PTE_DEVMAP
27 select ARCH_HAS_PTE_SPECIAL
28 select ARCH_HAS_SETUP_DMA_OPS
29 select ARCH_HAS_SET_DIRECT_MAP
30 select ARCH_HAS_SET_MEMORY
32 select ARCH_HAS_STRICT_KERNEL_RWX
33 select ARCH_HAS_STRICT_MODULE_RWX
34 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
35 select ARCH_HAS_SYNC_DMA_FOR_CPU
36 select ARCH_HAS_SYSCALL_WRAPPER
37 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
38 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
39 select ARCH_HAVE_ELF_PROT
40 select ARCH_HAVE_NMI_SAFE_CMPXCHG
41 select ARCH_INLINE_READ_LOCK if !PREEMPTION
42 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
43 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
44 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
45 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
46 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
47 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
48 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
49 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
50 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
51 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
52 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
53 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
54 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
55 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
56 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
57 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
58 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
59 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
60 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
61 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
62 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
63 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
64 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
65 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
66 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
67 select ARCH_KEEP_MEMBLOCK
68 select ARCH_USE_CMPXCHG_LOCKREF
69 select ARCH_USE_GNU_PROPERTY
70 select ARCH_USE_QUEUED_RWLOCKS
71 select ARCH_USE_QUEUED_SPINLOCKS
72 select ARCH_USE_SYM_ANNOTATIONS
73 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
74 select ARCH_SUPPORTS_MEMORY_FAILURE
75 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
76 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
77 select ARCH_SUPPORTS_LTO_CLANG_THIN
78 select ARCH_SUPPORTS_ATOMIC_RMW
79 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG)
80 select ARCH_SUPPORTS_NUMA_BALANCING
81 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
82 select ARCH_WANT_DEFAULT_BPF_JIT
83 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
84 select ARCH_WANT_FRAME_POINTERS
85 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
86 select ARCH_WANT_LD_ORPHAN_WARN
87 select ARCH_HAS_UBSAN_SANITIZE_ALL
91 select AUDIT_ARCH_COMPAT_GENERIC
92 select ARM_GIC_V2M if PCI
94 select ARM_GIC_V3_ITS if PCI
96 select BUILDTIME_TABLE_SORT
97 select CLONE_BACKWARDS
99 select CPU_PM if (SUSPEND || CPU_IDLE)
101 select DCACHE_WORD_ACCESS
102 select DMA_DIRECT_REMAP
105 select GENERIC_ALLOCATOR
106 select GENERIC_ARCH_TOPOLOGY
107 select GENERIC_CLOCKEVENTS_BROADCAST
108 select GENERIC_CPU_AUTOPROBE
109 select GENERIC_CPU_VULNERABILITIES
110 select GENERIC_EARLY_IOREMAP
111 select GENERIC_IDLE_POLL_SETUP
112 select GENERIC_IRQ_IPI
113 select GENERIC_IRQ_MULTI_HANDLER
114 select GENERIC_IRQ_PROBE
115 select GENERIC_IRQ_SHOW
116 select GENERIC_IRQ_SHOW_LEVEL
117 select GENERIC_LIB_DEVMEM_IS_ALLOWED
118 select GENERIC_PCI_IOMAP
119 select GENERIC_PTDUMP
120 select GENERIC_SCHED_CLOCK
121 select GENERIC_SMP_IDLE_THREAD
122 select GENERIC_STRNCPY_FROM_USER
123 select GENERIC_STRNLEN_USER
124 select GENERIC_TIME_VSYSCALL
125 select GENERIC_GETTIMEOFDAY
126 select GENERIC_VDSO_TIME_NS
127 select HANDLE_DOMAIN_IRQ
128 select HARDIRQS_SW_RESEND
132 select HAVE_ACPI_APEI if (ACPI && EFI)
133 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
134 select HAVE_ARCH_AUDITSYSCALL
135 select HAVE_ARCH_BITREVERSE
136 select HAVE_ARCH_COMPILER_H
137 select HAVE_ARCH_HUGE_VMAP
138 select HAVE_ARCH_JUMP_LABEL
139 select HAVE_ARCH_JUMP_LABEL_RELATIVE
140 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
141 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
142 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
143 select HAVE_ARCH_KGDB
144 select HAVE_ARCH_MMAP_RND_BITS
145 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
146 select HAVE_ARCH_PFN_VALID
147 select HAVE_ARCH_PREL32_RELOCATIONS
148 select HAVE_ARCH_SECCOMP_FILTER
149 select HAVE_ARCH_STACKLEAK
150 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
151 select HAVE_ARCH_TRACEHOOK
152 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
153 select HAVE_ARCH_VMAP_STACK
154 select HAVE_ARM_SMCCC
155 select HAVE_ASM_MODVERSIONS
157 select HAVE_C_RECORDMCOUNT
158 select HAVE_CMPXCHG_DOUBLE
159 select HAVE_CMPXCHG_LOCAL
160 select HAVE_CONTEXT_TRACKING
161 select HAVE_DEBUG_BUGVERBOSE
162 select HAVE_DEBUG_KMEMLEAK
163 select HAVE_DMA_CONTIGUOUS
164 select HAVE_DYNAMIC_FTRACE
165 select HAVE_DYNAMIC_FTRACE_WITH_REGS \
166 if $(cc-option,-fpatchable-function-entry=2)
167 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
168 if DYNAMIC_FTRACE_WITH_REGS
169 select HAVE_EFFICIENT_UNALIGNED_ACCESS
171 select HAVE_FTRACE_MCOUNT_RECORD
172 select HAVE_FUNCTION_TRACER
173 select HAVE_FUNCTION_ERROR_INJECTION
174 select HAVE_FUNCTION_GRAPH_TRACER
175 select HAVE_GCC_PLUGINS
176 select HAVE_HW_BREAKPOINT if PERF_EVENTS
177 select HAVE_IRQ_TIME_ACCOUNTING
179 select HAVE_PATA_PLATFORM
180 select HAVE_PERF_EVENTS
181 select HAVE_PERF_REGS
182 select HAVE_PERF_USER_STACK_DUMP
183 select HAVE_REGS_AND_STACK_ACCESS_API
184 select HAVE_FUNCTION_ARG_ACCESS_API
185 select HAVE_FUTEX_CMPXCHG if FUTEX
186 select MMU_GATHER_RCU_TABLE_FREE
188 select HAVE_STACKPROTECTOR
189 select HAVE_SYSCALL_TRACEPOINTS
191 select HAVE_KRETPROBES
192 select HAVE_GENERIC_VDSO
193 select IOMMU_DMA if IOMMU_SUPPORT
195 select IRQ_FORCED_THREADING
196 select MODULES_USE_ELF_RELA
197 select NEED_DMA_MAP_STATE
198 select NEED_SG_DMA_LENGTH
200 select OF_EARLY_FLATTREE
201 select PCI_DOMAINS_GENERIC if PCI
202 select PCI_ECAM if (ACPI && PCI)
203 select PCI_SYSCALL if PCI
208 select SYSCTL_EXCEPTION_TRACE
209 select THREAD_INFO_IN_TASK
211 ARM 64-bit (AArch64) Linux support.
219 config ARM64_PAGE_SHIFT
221 default 16 if ARM64_64K_PAGES
222 default 14 if ARM64_16K_PAGES
225 config ARM64_CONT_PTE_SHIFT
227 default 5 if ARM64_64K_PAGES
228 default 7 if ARM64_16K_PAGES
231 config ARM64_CONT_PMD_SHIFT
233 default 5 if ARM64_64K_PAGES
234 default 5 if ARM64_16K_PAGES
237 config ARCH_MMAP_RND_BITS_MIN
238 default 14 if ARM64_64K_PAGES
239 default 16 if ARM64_16K_PAGES
242 # max bits determined by the following formula:
243 # VA_BITS - PAGE_SHIFT - 3
244 config ARCH_MMAP_RND_BITS_MAX
245 default 19 if ARM64_VA_BITS=36
246 default 24 if ARM64_VA_BITS=39
247 default 27 if ARM64_VA_BITS=42
248 default 30 if ARM64_VA_BITS=47
249 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
250 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
251 default 33 if ARM64_VA_BITS=48
252 default 14 if ARM64_64K_PAGES
253 default 16 if ARM64_16K_PAGES
256 config ARCH_MMAP_RND_COMPAT_BITS_MIN
257 default 7 if ARM64_64K_PAGES
258 default 9 if ARM64_16K_PAGES
261 config ARCH_MMAP_RND_COMPAT_BITS_MAX
267 config STACKTRACE_SUPPORT
270 config ILLEGAL_POINTER_VALUE
272 default 0xdead000000000000
274 config LOCKDEP_SUPPORT
277 config TRACE_IRQFLAGS_SUPPORT
284 config GENERIC_BUG_RELATIVE_POINTERS
286 depends on GENERIC_BUG
288 config GENERIC_HWEIGHT
294 config GENERIC_CALIBRATE_DELAY
298 bool "Support DMA zone" if EXPERT
302 bool "Support DMA32 zone" if EXPERT
305 config ARCH_ENABLE_MEMORY_HOTPLUG
308 config ARCH_ENABLE_MEMORY_HOTREMOVE
314 config KERNEL_MODE_NEON
317 config FIX_EARLYCON_MEM
320 config PGTABLE_LEVELS
322 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
323 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
324 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
325 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
326 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
327 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
329 config ARCH_SUPPORTS_UPROBES
332 config ARCH_PROC_KCORE_TEXT
335 config BROKEN_GAS_INST
336 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
338 config KASAN_SHADOW_OFFSET
340 depends on KASAN_GENERIC || KASAN_SW_TAGS
341 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
342 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
343 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
344 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
345 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
346 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
347 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
348 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
349 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
350 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
351 default 0xffffffffffffffff
353 source "arch/arm64/Kconfig.platforms"
355 menu "Kernel Features"
357 menu "ARM errata workarounds via the alternatives framework"
359 config ARM64_WORKAROUND_CLEAN_CACHE
362 config ARM64_ERRATUM_826319
363 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
365 select ARM64_WORKAROUND_CLEAN_CACHE
367 This option adds an alternative code sequence to work around ARM
368 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
369 AXI master interface and an L2 cache.
371 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
372 and is unable to accept a certain write via this interface, it will
373 not progress on read data presented on the read data channel and the
376 The workaround promotes data cache clean instructions to
377 data cache clean-and-invalidate.
378 Please note that this does not necessarily enable the workaround,
379 as it depends on the alternative framework, which will only patch
380 the kernel if an affected CPU is detected.
384 config ARM64_ERRATUM_827319
385 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
387 select ARM64_WORKAROUND_CLEAN_CACHE
389 This option adds an alternative code sequence to work around ARM
390 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
391 master interface and an L2 cache.
393 Under certain conditions this erratum can cause a clean line eviction
394 to occur at the same time as another transaction to the same address
395 on the AMBA 5 CHI interface, which can cause data corruption if the
396 interconnect reorders the two transactions.
398 The workaround promotes data cache clean instructions to
399 data cache clean-and-invalidate.
400 Please note that this does not necessarily enable the workaround,
401 as it depends on the alternative framework, which will only patch
402 the kernel if an affected CPU is detected.
406 config ARM64_ERRATUM_824069
407 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
409 select ARM64_WORKAROUND_CLEAN_CACHE
411 This option adds an alternative code sequence to work around ARM
412 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
413 to a coherent interconnect.
415 If a Cortex-A53 processor is executing a store or prefetch for
416 write instruction at the same time as a processor in another
417 cluster is executing a cache maintenance operation to the same
418 address, then this erratum might cause a clean cache line to be
419 incorrectly marked as dirty.
421 The workaround promotes data cache clean instructions to
422 data cache clean-and-invalidate.
423 Please note that this option does not necessarily enable the
424 workaround, as it depends on the alternative framework, which will
425 only patch the kernel if an affected CPU is detected.
429 config ARM64_ERRATUM_819472
430 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
432 select ARM64_WORKAROUND_CLEAN_CACHE
434 This option adds an alternative code sequence to work around ARM
435 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
436 present when it is connected to a coherent interconnect.
438 If the processor is executing a load and store exclusive sequence at
439 the same time as a processor in another cluster is executing a cache
440 maintenance operation to the same address, then this erratum might
441 cause data corruption.
443 The workaround promotes data cache clean instructions to
444 data cache clean-and-invalidate.
445 Please note that this does not necessarily enable the workaround,
446 as it depends on the alternative framework, which will only patch
447 the kernel if an affected CPU is detected.
451 config ARM64_ERRATUM_832075
452 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
455 This option adds an alternative code sequence to work around ARM
456 erratum 832075 on Cortex-A57 parts up to r1p2.
458 Affected Cortex-A57 parts might deadlock when exclusive load/store
459 instructions to Write-Back memory are mixed with Device loads.
461 The workaround is to promote device loads to use Load-Acquire
463 Please note that this does not necessarily enable the workaround,
464 as it depends on the alternative framework, which will only patch
465 the kernel if an affected CPU is detected.
469 config ARM64_ERRATUM_834220
470 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
474 This option adds an alternative code sequence to work around ARM
475 erratum 834220 on Cortex-A57 parts up to r1p2.
477 Affected Cortex-A57 parts might report a Stage 2 translation
478 fault as the result of a Stage 1 fault for load crossing a
479 page boundary when there is a permission or device memory
480 alignment fault at Stage 1 and a translation fault at Stage 2.
482 The workaround is to verify that the Stage 1 translation
483 doesn't generate a fault before handling the Stage 2 fault.
484 Please note that this does not necessarily enable the workaround,
485 as it depends on the alternative framework, which will only patch
486 the kernel if an affected CPU is detected.
490 config ARM64_ERRATUM_845719
491 bool "Cortex-A53: 845719: a load might read incorrect data"
495 This option adds an alternative code sequence to work around ARM
496 erratum 845719 on Cortex-A53 parts up to r0p4.
498 When running a compat (AArch32) userspace on an affected Cortex-A53
499 part, a load at EL0 from a virtual address that matches the bottom 32
500 bits of the virtual address used by a recent load at (AArch64) EL1
501 might return incorrect data.
503 The workaround is to write the contextidr_el1 register on exception
504 return to a 32-bit task.
505 Please note that this does not necessarily enable the workaround,
506 as it depends on the alternative framework, which will only patch
507 the kernel if an affected CPU is detected.
511 config ARM64_ERRATUM_843419
512 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
514 select ARM64_MODULE_PLTS if MODULES
516 This option links the kernel with '--fix-cortex-a53-843419' and
517 enables PLT support to replace certain ADRP instructions, which can
518 cause subsequent memory accesses to use an incorrect address on
519 Cortex-A53 parts up to r0p4.
523 config ARM64_ERRATUM_1024718
524 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
527 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
529 Affected Cortex-A55 cores (all revisions) could cause incorrect
530 update of the hardware dirty bit when the DBM/AP bits are updated
531 without a break-before-make. The workaround is to disable the usage
532 of hardware DBM locally on the affected cores. CPUs not affected by
533 this erratum will continue to use the feature.
537 config ARM64_ERRATUM_1418040
538 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
542 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
543 errata 1188873 and 1418040.
545 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
546 cause register corruption when accessing the timer registers
547 from AArch32 userspace.
551 config ARM64_WORKAROUND_SPECULATIVE_AT
554 config ARM64_ERRATUM_1165522
555 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
557 select ARM64_WORKAROUND_SPECULATIVE_AT
559 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
561 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
562 corrupted TLBs by speculating an AT instruction during a guest
567 config ARM64_ERRATUM_1319367
568 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
570 select ARM64_WORKAROUND_SPECULATIVE_AT
572 This option adds work arounds for ARM Cortex-A57 erratum 1319537
573 and A72 erratum 1319367
575 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
576 speculating an AT instruction during a guest context switch.
580 config ARM64_ERRATUM_1530923
581 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
583 select ARM64_WORKAROUND_SPECULATIVE_AT
585 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
587 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
588 corrupted TLBs by speculating an AT instruction during a guest
593 config ARM64_WORKAROUND_REPEAT_TLBI
596 config ARM64_ERRATUM_1286807
597 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
599 select ARM64_WORKAROUND_REPEAT_TLBI
601 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
603 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
604 address for a cacheable mapping of a location is being
605 accessed by a core while another core is remapping the virtual
606 address to a new physical page using the recommended
607 break-before-make sequence, then under very rare circumstances
608 TLBI+DSB completes before a read using the translation being
609 invalidated has been observed by other observers. The
610 workaround repeats the TLBI+DSB operation.
612 config ARM64_ERRATUM_1463225
613 bool "Cortex-A76: Software Step might prevent interrupt recognition"
616 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
618 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
619 of a system call instruction (SVC) can prevent recognition of
620 subsequent interrupts when software stepping is disabled in the
621 exception handler of the system call and either kernel debugging
622 is enabled or VHE is in use.
624 Work around the erratum by triggering a dummy step exception
625 when handling a system call from a task that is being stepped
626 in a VHE configuration of the kernel.
630 config ARM64_ERRATUM_1542419
631 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
634 This option adds a workaround for ARM Neoverse-N1 erratum
637 Affected Neoverse-N1 cores could execute a stale instruction when
638 modified by another CPU. The workaround depends on a firmware
641 Workaround the issue by hiding the DIC feature from EL0. This
642 forces user-space to perform cache maintenance.
646 config ARM64_ERRATUM_1508412
647 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
650 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
652 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
653 of a store-exclusive or read of PAR_EL1 and a load with device or
654 non-cacheable memory attributes. The workaround depends on a firmware
657 KVM guests must also have the workaround implemented or they can
660 Work around the issue by inserting DMB SY barriers around PAR_EL1
661 register reads and warning KVM users. The DMB barrier is sufficient
662 to prevent a speculative PAR_EL1 read.
666 config CAVIUM_ERRATUM_22375
667 bool "Cavium erratum 22375, 24313"
670 Enable workaround for errata 22375 and 24313.
672 This implements two gicv3-its errata workarounds for ThunderX. Both
673 with a small impact affecting only ITS table allocation.
675 erratum 22375: only alloc 8MB table size
676 erratum 24313: ignore memory access type
678 The fixes are in ITS initialization and basically ignore memory access
679 type and table size provided by the TYPER and BASER registers.
683 config CAVIUM_ERRATUM_23144
684 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
688 ITS SYNC command hang for cross node io and collections/cpu mapping.
692 config CAVIUM_ERRATUM_23154
693 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
696 The gicv3 of ThunderX requires a modified version for
697 reading the IAR status to ensure data synchronization
698 (access to icc_iar1_el1 is not sync'ed before and after).
702 config CAVIUM_ERRATUM_27456
703 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
706 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
707 instructions may cause the icache to become corrupted if it
708 contains data for a non-current ASID. The fix is to
709 invalidate the icache when changing the mm context.
713 config CAVIUM_ERRATUM_30115
714 bool "Cavium erratum 30115: Guest may disable interrupts in host"
717 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
718 1.2, and T83 Pass 1.0, KVM guest execution may disable
719 interrupts in host. Trapping both GICv3 group-0 and group-1
720 accesses sidesteps the issue.
724 config CAVIUM_TX2_ERRATUM_219
725 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
728 On Cavium ThunderX2, a load, store or prefetch instruction between a
729 TTBR update and the corresponding context synchronizing operation can
730 cause a spurious Data Abort to be delivered to any hardware thread in
733 Work around the issue by avoiding the problematic code sequence and
734 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
735 trap handler performs the corresponding register access, skips the
736 instruction and ensures context synchronization by virtue of the
741 config FUJITSU_ERRATUM_010001
742 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
745 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
746 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
747 accesses may cause undefined fault (Data abort, DFSC=0b111111).
748 This fault occurs under a specific hardware condition when a
749 load/store instruction performs an address translation using:
750 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
751 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
752 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
753 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
755 The workaround is to ensure these bits are clear in TCR_ELx.
756 The workaround only affects the Fujitsu-A64FX.
760 config HISILICON_ERRATUM_161600802
761 bool "Hip07 161600802: Erroneous redistributor VLPI base"
764 The HiSilicon Hip07 SoC uses the wrong redistributor base
765 when issued ITS commands such as VMOVP and VMAPP, and requires
766 a 128kB offset to be applied to the target address in this commands.
770 config QCOM_FALKOR_ERRATUM_1003
771 bool "Falkor E1003: Incorrect translation due to ASID change"
774 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
775 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
776 in TTBR1_EL1, this situation only occurs in the entry trampoline and
777 then only for entries in the walk cache, since the leaf translation
778 is unchanged. Work around the erratum by invalidating the walk cache
779 entries for the trampoline before entering the kernel proper.
781 config QCOM_FALKOR_ERRATUM_1009
782 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
784 select ARM64_WORKAROUND_REPEAT_TLBI
786 On Falkor v1, the CPU may prematurely complete a DSB following a
787 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
788 one more time to fix the issue.
792 config QCOM_QDF2400_ERRATUM_0065
793 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
796 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
797 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
798 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
802 config QCOM_FALKOR_ERRATUM_E1041
803 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
806 Falkor CPU may speculatively fetch instructions from an improper
807 memory location when MMU translation is changed from SCTLR_ELn[M]=1
808 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
812 config SOCIONEXT_SYNQUACER_PREITS
813 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
816 Socionext Synquacer SoCs implement a separate h/w block to generate
817 MSI doorbell writes with non-zero values for the device ID.
826 default ARM64_4K_PAGES
828 Page size (translation granule) configuration.
830 config ARM64_4K_PAGES
833 This feature enables 4KB pages support.
835 config ARM64_16K_PAGES
838 The system will use 16KB pages support. AArch32 emulation
839 requires applications compiled with 16K (or a multiple of 16K)
842 config ARM64_64K_PAGES
845 This feature enables 64KB pages support (4KB by default)
846 allowing only two levels of page tables and faster TLB
847 look-up. AArch32 emulation requires applications compiled
848 with 64K aligned segments.
853 prompt "Virtual address space size"
854 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
855 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
856 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
858 Allows choosing one of multiple possible virtual address
859 space sizes. The level of translation table is determined by
860 a combination of page size and virtual address space size.
862 config ARM64_VA_BITS_36
863 bool "36-bit" if EXPERT
864 depends on ARM64_16K_PAGES
866 config ARM64_VA_BITS_39
868 depends on ARM64_4K_PAGES
870 config ARM64_VA_BITS_42
872 depends on ARM64_64K_PAGES
874 config ARM64_VA_BITS_47
876 depends on ARM64_16K_PAGES
878 config ARM64_VA_BITS_48
881 config ARM64_VA_BITS_52
883 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
885 Enable 52-bit virtual addressing for userspace when explicitly
886 requested via a hint to mmap(). The kernel will also use 52-bit
887 virtual addresses for its own mappings (provided HW support for
888 this feature is available, otherwise it reverts to 48-bit).
890 NOTE: Enabling 52-bit virtual addressing in conjunction with
891 ARMv8.3 Pointer Authentication will result in the PAC being
892 reduced from 7 bits to 3 bits, which may have a significant
893 impact on its susceptibility to brute-force attacks.
895 If unsure, select 48-bit virtual addressing instead.
899 config ARM64_FORCE_52BIT
900 bool "Force 52-bit virtual addresses for userspace"
901 depends on ARM64_VA_BITS_52 && EXPERT
903 For systems with 52-bit userspace VAs enabled, the kernel will attempt
904 to maintain compatibility with older software by providing 48-bit VAs
905 unless a hint is supplied to mmap.
907 This configuration option disables the 48-bit compatibility logic, and
908 forces all userspace addresses to be 52-bit on HW that supports it. One
909 should only enable this configuration option for stress testing userspace
910 memory management code. If unsure say N here.
914 default 36 if ARM64_VA_BITS_36
915 default 39 if ARM64_VA_BITS_39
916 default 42 if ARM64_VA_BITS_42
917 default 47 if ARM64_VA_BITS_47
918 default 48 if ARM64_VA_BITS_48
919 default 52 if ARM64_VA_BITS_52
922 prompt "Physical address space size"
923 default ARM64_PA_BITS_48
925 Choose the maximum physical address range that the kernel will
928 config ARM64_PA_BITS_48
931 config ARM64_PA_BITS_52
932 bool "52-bit (ARMv8.2)"
933 depends on ARM64_64K_PAGES
934 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
936 Enable support for a 52-bit physical address space, introduced as
937 part of the ARMv8.2-LPA extension.
939 With this enabled, the kernel will also continue to work on CPUs that
940 do not support ARMv8.2-LPA, but with some added memory overhead (and
941 minor performance overhead).
947 default 48 if ARM64_PA_BITS_48
948 default 52 if ARM64_PA_BITS_52
952 default CPU_LITTLE_ENDIAN
954 Select the endianness of data accesses performed by the CPU. Userspace
955 applications will need to be compiled and linked for the endianness
956 that is selected here.
958 config CPU_BIG_ENDIAN
959 bool "Build big-endian kernel"
960 depends on !LD_IS_LLD || LLD_VERSION >= 130000
962 Say Y if you plan on running a kernel with a big-endian userspace.
964 config CPU_LITTLE_ENDIAN
965 bool "Build little-endian kernel"
967 Say Y if you plan on running a kernel with a little-endian userspace.
968 This is usually the case for distributions targeting arm64.
973 bool "Multi-core scheduler support"
975 Multi-core scheduler support improves the CPU scheduler's decision
976 making when dealing with multi-core CPU chips at a cost of slightly
977 increased overhead in some places. If unsure say N here.
980 bool "SMT scheduler support"
982 Improves the CPU scheduler's decision making when dealing with
983 MultiThreading at a cost of slightly increased overhead in some
984 places. If unsure say N here.
987 int "Maximum number of CPUs (2-4096)"
992 bool "Support for hot-pluggable CPUs"
993 select GENERIC_IRQ_MIGRATION
995 Say Y here to experiment with turning CPUs off and on. CPUs
996 can be controlled through /sys/devices/system/cpu.
998 # Common NUMA Features
1000 bool "NUMA Memory Allocation and Scheduler Support"
1001 select ACPI_NUMA if ACPI
1004 Enable NUMA (Non-Uniform Memory Access) support.
1006 The kernel will try to allocate memory used by a CPU on the
1007 local memory of the CPU and add some more
1008 NUMA awareness to the kernel.
1011 int "Maximum NUMA Nodes (as a power of 2)"
1014 depends on NEED_MULTIPLE_NODES
1016 Specify the maximum number of NUMA Nodes available on the target
1017 system. Increases memory reserved to accommodate various tables.
1019 config USE_PERCPU_NUMA_NODE_ID
1023 config HAVE_SETUP_PER_CPU_AREA
1027 config NEED_PER_CPU_EMBED_FIRST_CHUNK
1031 config HOLES_IN_ZONE
1034 source "kernel/Kconfig.hz"
1036 config ARCH_SPARSEMEM_ENABLE
1038 select SPARSEMEM_VMEMMAP_ENABLE
1040 config ARCH_SPARSEMEM_DEFAULT
1041 def_bool ARCH_SPARSEMEM_ENABLE
1043 config ARCH_SELECT_MEMORY_MODEL
1044 def_bool ARCH_SPARSEMEM_ENABLE
1046 config ARCH_FLATMEM_ENABLE
1049 config HW_PERF_EVENTS
1053 config SYS_SUPPORTS_HUGETLBFS
1056 config ARCH_WANT_HUGE_PMD_SHARE
1058 config ARCH_HAS_CACHE_LINE_SIZE
1061 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
1062 def_bool y if PGTABLE_LEVELS > 2
1064 # Supported by clang >= 7.0
1065 config CC_HAVE_SHADOW_CALL_STACK
1066 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1069 bool "Enable paravirtualization code"
1071 This changes the kernel so it can modify itself when it is run
1072 under a hypervisor, potentially improving performance significantly
1073 over full virtualization.
1075 config PARAVIRT_TIME_ACCOUNTING
1076 bool "Paravirtual steal time accounting"
1079 Select this option to enable fine granularity task steal time
1080 accounting. Time spent executing other tasks in parallel with
1081 the current vCPU is discounted from the vCPU power. To account for
1082 that, there can be a small performance impact.
1084 If in doubt, say N here.
1087 depends on PM_SLEEP_SMP
1089 bool "kexec system call"
1091 kexec is a system call that implements the ability to shutdown your
1092 current kernel, and to start another kernel. It is like a reboot
1093 but it is independent of the system firmware. And like a reboot
1094 you can start any kernel with it, not just Linux.
1097 bool "kexec file based system call"
1100 This is new version of kexec system call. This system call is
1101 file based and takes file descriptors as system call argument
1102 for kernel and initramfs as opposed to list of segments as
1103 accepted by previous system call.
1106 bool "Verify kernel signature during kexec_file_load() syscall"
1107 depends on KEXEC_FILE
1109 Select this option to verify a signature with loaded kernel
1110 image. If configured, any attempt of loading a image without
1111 valid signature will fail.
1113 In addition to that option, you need to enable signature
1114 verification for the corresponding kernel image type being
1115 loaded in order for this to work.
1117 config KEXEC_IMAGE_VERIFY_SIG
1118 bool "Enable Image signature verification support"
1120 depends on KEXEC_SIG
1121 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1123 Enable Image signature verification support.
1125 comment "Support for PE file signature verification disabled"
1126 depends on KEXEC_SIG
1127 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1130 bool "Build kdump crash kernel"
1132 Generate crash dump after being started by kexec. This should
1133 be normally only set in special crash dump kernels which are
1134 loaded in the main kernel with kexec-tools into a specially
1135 reserved region and then later executed after a crash by
1138 For more details see Documentation/admin-guide/kdump/kdump.rst
1142 depends on HIBERNATION
1149 bool "Xen guest support on ARM64"
1150 depends on ARM64 && OF
1154 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1156 config FORCE_MAX_ZONEORDER
1158 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1159 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1162 The kernel memory allocator divides physically contiguous memory
1163 blocks into "zones", where each zone is a power of two number of
1164 pages. This option selects the largest power of two that the kernel
1165 keeps in the memory allocator. If you need to allocate very large
1166 blocks of physically contiguous memory, then you may need to
1167 increase this value.
1169 This config option is actually maximum order plus one. For example,
1170 a value of 11 means that the largest free memory block is 2^10 pages.
1172 We make sure that we can allocate upto a HugePage size for each configuration.
1174 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1176 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1177 4M allocations matching the default size used by generic code.
1179 config UNMAP_KERNEL_AT_EL0
1180 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1183 Speculation attacks against some high-performance processors can
1184 be used to bypass MMU permission checks and leak kernel data to
1185 userspace. This can be defended against by unmapping the kernel
1186 when running in userspace, mapping it back in on exception entry
1187 via a trampoline page in the vector table.
1191 config RODATA_FULL_DEFAULT_ENABLED
1192 bool "Apply r/o permissions of VM areas also to their linear aliases"
1195 Apply read-only attributes of VM areas to the linear alias of
1196 the backing pages as well. This prevents code or read-only data
1197 from being modified (inadvertently or intentionally) via another
1198 mapping of the same memory page. This additional enhancement can
1199 be turned off at runtime by passing rodata=[off|on] (and turned on
1200 with rodata=full if this option is set to 'n')
1202 This requires the linear region to be mapped down to pages,
1203 which may adversely affect performance in some cases.
1205 config ARM64_SW_TTBR0_PAN
1206 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1208 Enabling this option prevents the kernel from accessing
1209 user-space memory directly by pointing TTBR0_EL1 to a reserved
1210 zeroed area and reserved ASID. The user access routines
1211 restore the valid TTBR0_EL1 temporarily.
1213 config ARM64_TAGGED_ADDR_ABI
1214 bool "Enable the tagged user addresses syscall ABI"
1217 When this option is enabled, user applications can opt in to a
1218 relaxed ABI via prctl() allowing tagged addresses to be passed
1219 to system calls as pointer arguments. For details, see
1220 Documentation/arm64/tagged-address-abi.rst.
1223 bool "Kernel support for 32-bit EL0"
1224 depends on ARM64_4K_PAGES || EXPERT
1226 select OLD_SIGSUSPEND3
1227 select COMPAT_OLD_SIGACTION
1229 This option enables support for a 32-bit EL0 running under a 64-bit
1230 kernel at EL1. AArch32-specific components such as system calls,
1231 the user helper functions, VFP support and the ptrace interface are
1232 handled appropriately by the kernel.
1234 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1235 that you will only be able to execute AArch32 binaries that were compiled
1236 with page size aligned segments.
1238 If you want to execute 32-bit userspace applications, say Y.
1242 config KUSER_HELPERS
1243 bool "Enable kuser helpers page for 32-bit applications"
1246 Warning: disabling this option may break 32-bit user programs.
1248 Provide kuser helpers to compat tasks. The kernel provides
1249 helper code to userspace in read only form at a fixed location
1250 to allow userspace to be independent of the CPU type fitted to
1251 the system. This permits binaries to be run on ARMv4 through
1252 to ARMv8 without modification.
1254 See Documentation/arm/kernel_user_helpers.rst for details.
1256 However, the fixed address nature of these helpers can be used
1257 by ROP (return orientated programming) authors when creating
1260 If all of the binaries and libraries which run on your platform
1261 are built specifically for your platform, and make no use of
1262 these helpers, then you can turn this option off to hinder
1263 such exploits. However, in that case, if a binary or library
1264 relying on those helpers is run, it will not function correctly.
1266 Say N here only if you are absolutely certain that you do not
1267 need these helpers; otherwise, the safe option is to say Y.
1270 bool "Enable vDSO for 32-bit applications"
1271 depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1272 select GENERIC_COMPAT_VDSO
1275 Place in the process address space of 32-bit applications an
1276 ELF shared object providing fast implementations of gettimeofday
1279 You must have a 32-bit build of glibc 2.22 or later for programs
1280 to seamlessly take advantage of this.
1282 config THUMB2_COMPAT_VDSO
1283 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1284 depends on COMPAT_VDSO
1287 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1288 otherwise with '-marm'.
1290 menuconfig ARMV8_DEPRECATED
1291 bool "Emulate deprecated/obsolete ARMv8 instructions"
1294 Legacy software support may require certain instructions
1295 that have been deprecated or obsoleted in the architecture.
1297 Enable this config to enable selective emulation of these
1304 config SWP_EMULATION
1305 bool "Emulate SWP/SWPB instructions"
1307 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1308 they are always undefined. Say Y here to enable software
1309 emulation of these instructions for userspace using LDXR/STXR.
1310 This feature can be controlled at runtime with the abi.swp
1311 sysctl which is disabled by default.
1313 In some older versions of glibc [<=2.8] SWP is used during futex
1314 trylock() operations with the assumption that the code will not
1315 be preempted. This invalid assumption may be more likely to fail
1316 with SWP emulation enabled, leading to deadlock of the user
1319 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1320 on an external transaction monitoring block called a global
1321 monitor to maintain update atomicity. If your system does not
1322 implement a global monitor, this option can cause programs that
1323 perform SWP operations to uncached memory to deadlock.
1327 config CP15_BARRIER_EMULATION
1328 bool "Emulate CP15 Barrier instructions"
1330 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1331 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1332 strongly recommended to use the ISB, DSB, and DMB
1333 instructions instead.
1335 Say Y here to enable software emulation of these
1336 instructions for AArch32 userspace code. When this option is
1337 enabled, CP15 barrier usage is traced which can help
1338 identify software that needs updating. This feature can be
1339 controlled at runtime with the abi.cp15_barrier sysctl.
1343 config SETEND_EMULATION
1344 bool "Emulate SETEND instruction"
1346 The SETEND instruction alters the data-endianness of the
1347 AArch32 EL0, and is deprecated in ARMv8.
1349 Say Y here to enable software emulation of the instruction
1350 for AArch32 userspace code. This feature can be controlled
1351 at runtime with the abi.setend sysctl.
1353 Note: All the cpus on the system must have mixed endian support at EL0
1354 for this feature to be enabled. If a new CPU - which doesn't support mixed
1355 endian - is hotplugged in after this feature has been enabled, there could
1356 be unexpected results in the applications.
1363 menu "ARMv8.1 architectural features"
1365 config ARM64_HW_AFDBM
1366 bool "Support for hardware updates of the Access and Dirty page flags"
1369 The ARMv8.1 architecture extensions introduce support for
1370 hardware updates of the access and dirty information in page
1371 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1372 capable processors, accesses to pages with PTE_AF cleared will
1373 set this bit instead of raising an access flag fault.
1374 Similarly, writes to read-only pages with the DBM bit set will
1375 clear the read-only bit (AP[2]) instead of raising a
1378 Kernels built with this configuration option enabled continue
1379 to work on pre-ARMv8.1 hardware and the performance impact is
1380 minimal. If unsure, say Y.
1383 bool "Enable support for Privileged Access Never (PAN)"
1386 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1387 prevents the kernel or hypervisor from accessing user-space (EL0)
1390 Choosing this option will cause any unprotected (not using
1391 copy_to_user et al) memory access to fail with a permission fault.
1393 The feature is detected at runtime, and will remain as a 'nop'
1394 instruction if the cpu does not implement the feature.
1397 def_bool $(as-instr,.arch_extension rcpc)
1399 config ARM64_LSE_ATOMICS
1401 default ARM64_USE_LSE_ATOMICS
1402 depends on $(as-instr,.arch_extension lse)
1404 config ARM64_USE_LSE_ATOMICS
1405 bool "Atomic instructions"
1406 depends on JUMP_LABEL
1409 As part of the Large System Extensions, ARMv8.1 introduces new
1410 atomic instructions that are designed specifically to scale in
1413 Say Y here to make use of these instructions for the in-kernel
1414 atomic routines. This incurs a small overhead on CPUs that do
1415 not support these instructions and requires the kernel to be
1416 built with binutils >= 2.25 in order for the new instructions
1420 bool "Enable support for Virtualization Host Extensions (VHE)"
1423 Virtualization Host Extensions (VHE) allow the kernel to run
1424 directly at EL2 (instead of EL1) on processors that support
1425 it. This leads to better performance for KVM, as they reduce
1426 the cost of the world switch.
1428 Selecting this option allows the VHE feature to be detected
1429 at runtime, and does not affect processors that do not
1430 implement this feature.
1434 menu "ARMv8.2 architectural features"
1437 bool "Enable support for persistent memory"
1438 select ARCH_HAS_PMEM_API
1439 select ARCH_HAS_UACCESS_FLUSHCACHE
1441 Say Y to enable support for the persistent memory API based on the
1442 ARMv8.2 DCPoP feature.
1444 The feature is detected at runtime, and the kernel will use DC CVAC
1445 operations if DC CVAP is not supported (following the behaviour of
1446 DC CVAP itself if the system does not define a point of persistence).
1448 config ARM64_RAS_EXTN
1449 bool "Enable support for RAS CPU Extensions"
1452 CPUs that support the Reliability, Availability and Serviceability
1453 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1454 errors, classify them and report them to software.
1456 On CPUs with these extensions system software can use additional
1457 barriers to determine if faults are pending and read the
1458 classification from a new set of registers.
1460 Selecting this feature will allow the kernel to use these barriers
1461 and access the new registers if the system supports the extension.
1462 Platform RAS features may additionally depend on firmware support.
1465 bool "Enable support for Common Not Private (CNP) translations"
1467 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1469 Common Not Private (CNP) allows translation table entries to
1470 be shared between different PEs in the same inner shareable
1471 domain, so the hardware can use this fact to optimise the
1472 caching of such entries in the TLB.
1474 Selecting this option allows the CNP feature to be detected
1475 at runtime, and does not affect PEs that do not implement
1480 menu "ARMv8.3 architectural features"
1482 config ARM64_PTR_AUTH
1483 bool "Enable support for pointer authentication"
1485 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1486 # Modern compilers insert a .note.gnu.property section note for PAC
1487 # which is only understood by binutils starting with version 2.33.1.
1488 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1489 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1490 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1492 Pointer authentication (part of the ARMv8.3 Extensions) provides
1493 instructions for signing and authenticating pointers against secret
1494 keys, which can be used to mitigate Return Oriented Programming (ROP)
1497 This option enables these instructions at EL0 (i.e. for userspace).
1498 Choosing this option will cause the kernel to initialise secret keys
1499 for each process at exec() time, with these keys being
1500 context-switched along with the process.
1502 If the compiler supports the -mbranch-protection or
1503 -msign-return-address flag (e.g. GCC 7 or later), then this option
1504 will also cause the kernel itself to be compiled with return address
1505 protection. In this case, and if the target hardware is known to
1506 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1507 disabled with minimal loss of protection.
1509 The feature is detected at runtime. If the feature is not present in
1510 hardware it will not be advertised to userspace/KVM guest nor will it
1513 If the feature is present on the boot CPU but not on a late CPU, then
1514 the late CPU will be parked. Also, if the boot CPU does not have
1515 address auth and the late CPU has then the late CPU will still boot
1516 but with the feature disabled. On such a system, this option should
1519 This feature works with FUNCTION_GRAPH_TRACER option only if
1520 DYNAMIC_FTRACE_WITH_REGS is enabled.
1522 config CC_HAS_BRANCH_PROT_PAC_RET
1523 # GCC 9 or later, clang 8 or later
1524 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1526 config CC_HAS_SIGN_RETURN_ADDRESS
1528 def_bool $(cc-option,-msign-return-address=all)
1531 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1533 config AS_HAS_CFI_NEGATE_RA_STATE
1534 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1538 menu "ARMv8.4 architectural features"
1540 config ARM64_AMU_EXTN
1541 bool "Enable support for the Activity Monitors Unit CPU extension"
1544 The activity monitors extension is an optional extension introduced
1545 by the ARMv8.4 CPU architecture. This enables support for version 1
1546 of the activity monitors architecture, AMUv1.
1548 To enable the use of this extension on CPUs that implement it, say Y.
1550 Note that for architectural reasons, firmware _must_ implement AMU
1551 support when running on CPUs that present the activity monitors
1552 extension. The required support is present in:
1553 * Version 1.5 and later of the ARM Trusted Firmware
1555 For kernels that have this configuration enabled but boot with broken
1556 firmware, you may need to say N here until the firmware is fixed.
1557 Otherwise you may experience firmware panics or lockups when
1558 accessing the counter registers. Even if you are not observing these
1559 symptoms, the values returned by the register reads might not
1560 correctly reflect reality. Most commonly, the value read will be 0,
1561 indicating that the counter is not enabled.
1563 config AS_HAS_ARMV8_4
1564 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1566 config ARM64_TLB_RANGE
1567 bool "Enable support for tlbi range feature"
1569 depends on AS_HAS_ARMV8_4
1571 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1572 range of input addresses.
1574 The feature introduces new assembly instructions, and they were
1575 support when binutils >= 2.30.
1579 menu "ARMv8.5 architectural features"
1581 config AS_HAS_ARMV8_5
1582 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1585 bool "Branch Target Identification support"
1588 Branch Target Identification (part of the ARMv8.5 Extensions)
1589 provides a mechanism to limit the set of locations to which computed
1590 branch instructions such as BR or BLR can jump.
1592 To make use of BTI on CPUs that support it, say Y.
1594 BTI is intended to provide complementary protection to other control
1595 flow integrity protection mechanisms, such as the Pointer
1596 authentication mechanism provided as part of the ARMv8.3 Extensions.
1597 For this reason, it does not make sense to enable this option without
1598 also enabling support for pointer authentication. Thus, when
1599 enabling this option you should also select ARM64_PTR_AUTH=y.
1601 Userspace binaries must also be specifically compiled to make use of
1602 this mechanism. If you say N here or the hardware does not support
1603 BTI, such binaries can still run, but you get no additional
1604 enforcement of branch destinations.
1606 config ARM64_BTI_KERNEL
1607 bool "Use Branch Target Identification for kernel"
1609 depends on ARM64_BTI
1610 depends on ARM64_PTR_AUTH
1611 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1612 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1613 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1614 depends on !(CC_IS_CLANG && GCOV_KERNEL)
1615 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1617 Build the kernel with Branch Target Identification annotations
1618 and enable enforcement of this for kernel code. When this option
1619 is enabled and the system supports BTI all kernel code including
1620 modular code must have BTI enabled.
1622 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1623 # GCC 9 or later, clang 8 or later
1624 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1627 bool "Enable support for E0PD"
1630 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1631 that EL0 accesses made via TTBR1 always fault in constant time,
1632 providing similar benefits to KASLR as those provided by KPTI, but
1633 with lower overhead and without disrupting legitimate access to
1634 kernel memory such as SPE.
1636 This option enables E0PD for TTBR1 where available.
1639 bool "Enable support for random number generation"
1642 Random number generation (part of the ARMv8.5 Extensions)
1643 provides a high bandwidth, cryptographically secure
1644 hardware random number generator.
1646 config ARM64_AS_HAS_MTE
1647 # Initial support for MTE went in binutils 2.32.0, checked with
1648 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1649 # as a late addition to the final architecture spec (LDGM/STGM)
1650 # is only supported in the newer 2.32.x and 2.33 binutils
1651 # versions, hence the extra "stgm" instruction check below.
1652 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1655 bool "Memory Tagging Extension support"
1657 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1658 depends on AS_HAS_ARMV8_5
1659 # Required for tag checking in the uaccess routines
1660 depends on ARM64_PAN
1661 select ARCH_USES_HIGH_VMA_FLAGS
1663 Memory Tagging (part of the ARMv8.5 Extensions) provides
1664 architectural support for run-time, always-on detection of
1665 various classes of memory error to aid with software debugging
1666 to eliminate vulnerabilities arising from memory-unsafe
1669 This option enables the support for the Memory Tagging
1670 Extension at EL0 (i.e. for userspace).
1672 Selecting this option allows the feature to be detected at
1673 runtime. Any secondary CPU not implementing this feature will
1674 not be allowed a late bring-up.
1676 Userspace binaries that want to use this feature must
1677 explicitly opt in. The mechanism for the userspace is
1680 Documentation/arm64/memory-tagging-extension.rst.
1685 bool "ARM Scalable Vector Extension support"
1687 depends on !KVM || ARM64_VHE
1689 The Scalable Vector Extension (SVE) is an extension to the AArch64
1690 execution state which complements and extends the SIMD functionality
1691 of the base architecture to support much larger vectors and to enable
1692 additional vectorisation opportunities.
1694 To enable use of this extension on CPUs that implement it, say Y.
1696 On CPUs that support the SVE2 extensions, this option will enable
1699 Note that for architectural reasons, firmware _must_ implement SVE
1700 support when running on SVE capable hardware. The required support
1703 * version 1.5 and later of the ARM Trusted Firmware
1704 * the AArch64 boot wrapper since commit 5e1261e08abf
1705 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1707 For other firmware implementations, consult the firmware documentation
1710 If you need the kernel to boot on SVE-capable hardware with broken
1711 firmware, you may need to say N here until you get your firmware
1712 fixed. Otherwise, you may experience firmware panics or lockups when
1713 booting the kernel. If unsure and you are not observing these
1714 symptoms, you should assume that it is safe to say Y.
1716 CPUs that support SVE are architecturally required to support the
1717 Virtualization Host Extensions (VHE), so the kernel makes no
1718 provision for supporting SVE alongside KVM without VHE enabled.
1719 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1720 KVM in the same kernel image.
1722 config ARM64_MODULE_PLTS
1723 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1725 select HAVE_MOD_ARCH_SPECIFIC
1727 Allocate PLTs when loading modules so that jumps and calls whose
1728 targets are too far away for their relative offsets to be encoded
1729 in the instructions themselves can be bounced via veneers in the
1730 module's PLT. This allows modules to be allocated in the generic
1731 vmalloc area after the dedicated module memory area has been
1734 When running with address space randomization (KASLR), the module
1735 region itself may be too far away for ordinary relative jumps and
1736 calls, and so in that case, module PLTs are required and cannot be
1739 Specific errata workaround(s) might also force module PLTs to be
1740 enabled (ARM64_ERRATUM_843419).
1742 config ARM64_PSEUDO_NMI
1743 bool "Support for NMI-like interrupts"
1746 Adds support for mimicking Non-Maskable Interrupts through the use of
1747 GIC interrupt priority. This support requires version 3 or later of
1750 This high priority configuration for interrupts needs to be
1751 explicitly enabled by setting the kernel parameter
1752 "irqchip.gicv3_pseudo_nmi" to 1.
1757 config ARM64_DEBUG_PRIORITY_MASKING
1758 bool "Debug interrupt priority masking"
1760 This adds runtime checks to functions enabling/disabling
1761 interrupts when using priority masking. The additional checks verify
1762 the validity of ICC_PMR_EL1 when calling concerned functions.
1768 bool "Build a relocatable kernel image" if EXPERT
1769 select ARCH_HAS_RELR
1772 This builds the kernel as a Position Independent Executable (PIE),
1773 which retains all relocation metadata required to relocate the
1774 kernel binary at runtime to a different virtual address than the
1775 address it was linked at.
1776 Since AArch64 uses the RELA relocation format, this requires a
1777 relocation pass at runtime even if the kernel is loaded at the
1778 same address it was linked at.
1780 config RANDOMIZE_BASE
1781 bool "Randomize the address of the kernel image"
1782 select ARM64_MODULE_PLTS if MODULES
1785 Randomizes the virtual address at which the kernel image is
1786 loaded, as a security feature that deters exploit attempts
1787 relying on knowledge of the location of kernel internals.
1789 It is the bootloader's job to provide entropy, by passing a
1790 random u64 value in /chosen/kaslr-seed at kernel entry.
1792 When booting via the UEFI stub, it will invoke the firmware's
1793 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1794 to the kernel proper. In addition, it will randomise the physical
1795 location of the kernel Image as well.
1799 config RANDOMIZE_MODULE_REGION_FULL
1800 bool "Randomize the module region over a 4 GB range"
1801 depends on RANDOMIZE_BASE
1804 Randomizes the location of the module region inside a 4 GB window
1805 covering the core kernel. This way, it is less likely for modules
1806 to leak information about the location of core kernel data structures
1807 but it does imply that function calls between modules and the core
1808 kernel will need to be resolved via veneers in the module PLT.
1810 When this option is not set, the module region will be randomized over
1811 a limited range that contains the [_stext, _etext] interval of the
1812 core kernel, so branch relocations are always in range.
1814 config CC_HAVE_STACKPROTECTOR_SYSREG
1815 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1817 config STACKPROTECTOR_PER_TASK
1819 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1825 config ARM64_ACPI_PARKING_PROTOCOL
1826 bool "Enable support for the ARM64 ACPI parking protocol"
1829 Enable support for the ARM64 ACPI parking protocol. If disabled
1830 the kernel will not allow booting through the ARM64 ACPI parking
1831 protocol even if the corresponding data is present in the ACPI
1835 string "Default kernel command string"
1838 Provide a set of default command-line options at build time by
1839 entering them here. As a minimum, you should specify the the
1840 root device (e.g. root=/dev/nfs).
1843 prompt "Kernel command line type" if CMDLINE != ""
1844 default CMDLINE_FROM_BOOTLOADER
1846 Choose how the kernel will handle the provided default kernel
1847 command line string.
1849 config CMDLINE_FROM_BOOTLOADER
1850 bool "Use bootloader kernel arguments if available"
1852 Uses the command-line options passed by the boot loader. If
1853 the boot loader doesn't provide any, the default kernel command
1854 string provided in CMDLINE will be used.
1856 config CMDLINE_EXTEND
1857 bool "Extend bootloader kernel arguments"
1859 The command-line arguments provided by the boot loader will be
1860 appended to the default kernel command string.
1862 config CMDLINE_FORCE
1863 bool "Always use the default kernel command string"
1865 Always use the default kernel command string, even if the boot
1866 loader passes other arguments to the kernel.
1867 This is useful if you cannot or don't want to change the
1868 command-line options your boot loader passes to the kernel.
1876 bool "UEFI runtime support"
1877 depends on OF && !CPU_BIG_ENDIAN
1878 depends on KERNEL_MODE_NEON
1879 select ARCH_SUPPORTS_ACPI
1882 select EFI_PARAMS_FROM_FDT
1883 select EFI_RUNTIME_WRAPPERS
1885 select EFI_GENERIC_STUB
1886 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
1889 This option provides support for runtime services provided
1890 by UEFI firmware (such as non-volatile variables, realtime
1891 clock, and platform reset). A UEFI stub is also provided to
1892 allow the kernel to be booted as an EFI application. This
1893 is only useful on systems that have UEFI firmware.
1896 bool "Enable support for SMBIOS (DMI) tables"
1900 This enables SMBIOS/DMI feature for systems.
1902 This option is only useful on systems that have UEFI firmware.
1903 However, even with this option, the resultant kernel should
1904 continue to boot on existing non-UEFI platforms.
1908 config SYSVIPC_COMPAT
1910 depends on COMPAT && SYSVIPC
1912 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1914 depends on HUGETLB_PAGE && MIGRATION
1916 config ARCH_ENABLE_THP_MIGRATION
1918 depends on TRANSPARENT_HUGEPAGE
1920 menu "Power management options"
1922 source "kernel/power/Kconfig"
1924 config ARCH_HIBERNATION_POSSIBLE
1928 config ARCH_HIBERNATION_HEADER
1930 depends on HIBERNATION
1932 config ARCH_SUSPEND_POSSIBLE
1937 menu "CPU Power Management"
1939 source "drivers/cpuidle/Kconfig"
1941 source "drivers/cpufreq/Kconfig"
1945 source "drivers/firmware/Kconfig"
1947 source "drivers/acpi/Kconfig"
1949 source "arch/arm64/kvm/Kconfig"
1952 source "arch/arm64/crypto/Kconfig"