1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_WX
13 select ARCH_BINFMT_ELF_STATE
14 select ARCH_HAS_DEBUG_VIRTUAL
15 select ARCH_HAS_DEBUG_VM_PGTABLE
16 select ARCH_HAS_DMA_PREP_COHERENT
17 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
18 select ARCH_HAS_FAST_MULTIPLIER
19 select ARCH_HAS_FORTIFY_SOURCE
20 select ARCH_HAS_GCOV_PROFILE_ALL
21 select ARCH_HAS_GIGANTIC_PAGE
23 select ARCH_HAS_KEEPINITRD
24 select ARCH_HAS_MEMBARRIER_SYNC_CORE
25 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
26 select ARCH_HAS_PTE_DEVMAP
27 select ARCH_HAS_PTE_SPECIAL
28 select ARCH_HAS_SETUP_DMA_OPS
29 select ARCH_HAS_SET_DIRECT_MAP
30 select ARCH_HAS_SET_MEMORY
32 select ARCH_HAS_STRICT_KERNEL_RWX
33 select ARCH_HAS_STRICT_MODULE_RWX
34 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
35 select ARCH_HAS_SYNC_DMA_FOR_CPU
36 select ARCH_HAS_SYSCALL_WRAPPER
37 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
38 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
39 select ARCH_HAVE_ELF_PROT
40 select ARCH_HAVE_NMI_SAFE_CMPXCHG
41 select ARCH_INLINE_READ_LOCK if !PREEMPTION
42 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
43 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
44 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
45 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
46 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
47 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
48 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
49 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
50 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
51 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
52 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
53 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
54 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
55 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
56 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
57 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
58 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
59 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
60 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
61 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
62 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
63 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
64 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
65 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
66 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
67 select ARCH_KEEP_MEMBLOCK
68 select ARCH_USE_CMPXCHG_LOCKREF
69 select ARCH_USE_GNU_PROPERTY
70 select ARCH_USE_QUEUED_RWLOCKS
71 select ARCH_USE_QUEUED_SPINLOCKS
72 select ARCH_USE_SYM_ANNOTATIONS
73 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
74 select ARCH_SUPPORTS_MEMORY_FAILURE
75 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
76 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
77 select ARCH_SUPPORTS_LTO_CLANG_THIN
78 select ARCH_SUPPORTS_ATOMIC_RMW
79 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG)
80 select ARCH_SUPPORTS_NUMA_BALANCING
81 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
82 select ARCH_WANT_DEFAULT_BPF_JIT
83 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
84 select ARCH_WANT_FRAME_POINTERS
85 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
86 select ARCH_WANT_LD_ORPHAN_WARN
87 select ARCH_HAS_UBSAN_SANITIZE_ALL
91 select AUDIT_ARCH_COMPAT_GENERIC
92 select ARM_GIC_V2M if PCI
94 select ARM_GIC_V3_ITS if PCI
96 select BUILDTIME_TABLE_SORT
97 select CLONE_BACKWARDS
99 select CPU_PM if (SUSPEND || CPU_IDLE)
101 select DCACHE_WORD_ACCESS
102 select DMA_DIRECT_REMAP
105 select GENERIC_ALLOCATOR
106 select GENERIC_ARCH_TOPOLOGY
107 select GENERIC_CLOCKEVENTS_BROADCAST
108 select GENERIC_CPU_AUTOPROBE
109 select GENERIC_CPU_VULNERABILITIES
110 select GENERIC_EARLY_IOREMAP
111 select GENERIC_IDLE_POLL_SETUP
112 select GENERIC_IRQ_IPI
113 select GENERIC_IRQ_MULTI_HANDLER
114 select GENERIC_IRQ_PROBE
115 select GENERIC_IRQ_SHOW
116 select GENERIC_IRQ_SHOW_LEVEL
117 select GENERIC_LIB_DEVMEM_IS_ALLOWED
118 select GENERIC_PCI_IOMAP
119 select GENERIC_PTDUMP
120 select GENERIC_SCHED_CLOCK
121 select GENERIC_SMP_IDLE_THREAD
122 select GENERIC_STRNCPY_FROM_USER
123 select GENERIC_STRNLEN_USER
124 select GENERIC_TIME_VSYSCALL
125 select GENERIC_GETTIMEOFDAY
126 select GENERIC_VDSO_TIME_NS
127 select HANDLE_DOMAIN_IRQ
128 select HARDIRQS_SW_RESEND
132 select HAVE_ACPI_APEI if (ACPI && EFI)
133 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
134 select HAVE_ARCH_AUDITSYSCALL
135 select HAVE_ARCH_BITREVERSE
136 select HAVE_ARCH_COMPILER_H
137 select HAVE_ARCH_HUGE_VMAP
138 select HAVE_ARCH_JUMP_LABEL
139 select HAVE_ARCH_JUMP_LABEL_RELATIVE
140 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
141 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
142 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
143 select HAVE_ARCH_KFENCE
144 select HAVE_ARCH_KGDB
145 select HAVE_ARCH_MMAP_RND_BITS
146 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
147 select HAVE_ARCH_PFN_VALID
148 select HAVE_ARCH_PREL32_RELOCATIONS
149 select HAVE_ARCH_SECCOMP_FILTER
150 select HAVE_ARCH_STACKLEAK
151 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
152 select HAVE_ARCH_TRACEHOOK
153 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
154 select HAVE_ARCH_VMAP_STACK
155 select HAVE_ARM_SMCCC
156 select HAVE_ASM_MODVERSIONS
158 select HAVE_C_RECORDMCOUNT
159 select HAVE_CMPXCHG_DOUBLE
160 select HAVE_CMPXCHG_LOCAL
161 select HAVE_CONTEXT_TRACKING
162 select HAVE_DEBUG_BUGVERBOSE
163 select HAVE_DEBUG_KMEMLEAK
164 select HAVE_DMA_CONTIGUOUS
165 select HAVE_DYNAMIC_FTRACE
166 select HAVE_DYNAMIC_FTRACE_WITH_REGS \
167 if $(cc-option,-fpatchable-function-entry=2)
168 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
169 if DYNAMIC_FTRACE_WITH_REGS
170 select HAVE_EFFICIENT_UNALIGNED_ACCESS
172 select HAVE_FTRACE_MCOUNT_RECORD
173 select HAVE_FUNCTION_TRACER
174 select HAVE_FUNCTION_ERROR_INJECTION
175 select HAVE_FUNCTION_GRAPH_TRACER
176 select HAVE_GCC_PLUGINS
177 select HAVE_HW_BREAKPOINT if PERF_EVENTS
178 select HAVE_IRQ_TIME_ACCOUNTING
180 select HAVE_PATA_PLATFORM
181 select HAVE_PERF_EVENTS
182 select HAVE_PERF_REGS
183 select HAVE_PERF_USER_STACK_DUMP
184 select HAVE_REGS_AND_STACK_ACCESS_API
185 select HAVE_FUNCTION_ARG_ACCESS_API
186 select HAVE_FUTEX_CMPXCHG if FUTEX
187 select MMU_GATHER_RCU_TABLE_FREE
189 select HAVE_STACKPROTECTOR
190 select HAVE_SYSCALL_TRACEPOINTS
192 select HAVE_KRETPROBES
193 select HAVE_GENERIC_VDSO
194 select IOMMU_DMA if IOMMU_SUPPORT
196 select IRQ_FORCED_THREADING
197 select MODULES_USE_ELF_RELA
198 select NEED_DMA_MAP_STATE
199 select NEED_SG_DMA_LENGTH
201 select OF_EARLY_FLATTREE
202 select PCI_DOMAINS_GENERIC if PCI
203 select PCI_ECAM if (ACPI && PCI)
204 select PCI_SYSCALL if PCI
209 select SYSCTL_EXCEPTION_TRACE
210 select THREAD_INFO_IN_TASK
212 ARM 64-bit (AArch64) Linux support.
220 config ARM64_PAGE_SHIFT
222 default 16 if ARM64_64K_PAGES
223 default 14 if ARM64_16K_PAGES
226 config ARM64_CONT_PTE_SHIFT
228 default 5 if ARM64_64K_PAGES
229 default 7 if ARM64_16K_PAGES
232 config ARM64_CONT_PMD_SHIFT
234 default 5 if ARM64_64K_PAGES
235 default 5 if ARM64_16K_PAGES
238 config ARCH_MMAP_RND_BITS_MIN
239 default 14 if ARM64_64K_PAGES
240 default 16 if ARM64_16K_PAGES
243 # max bits determined by the following formula:
244 # VA_BITS - PAGE_SHIFT - 3
245 config ARCH_MMAP_RND_BITS_MAX
246 default 19 if ARM64_VA_BITS=36
247 default 24 if ARM64_VA_BITS=39
248 default 27 if ARM64_VA_BITS=42
249 default 30 if ARM64_VA_BITS=47
250 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
251 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
252 default 33 if ARM64_VA_BITS=48
253 default 14 if ARM64_64K_PAGES
254 default 16 if ARM64_16K_PAGES
257 config ARCH_MMAP_RND_COMPAT_BITS_MIN
258 default 7 if ARM64_64K_PAGES
259 default 9 if ARM64_16K_PAGES
262 config ARCH_MMAP_RND_COMPAT_BITS_MAX
268 config STACKTRACE_SUPPORT
271 config ILLEGAL_POINTER_VALUE
273 default 0xdead000000000000
275 config LOCKDEP_SUPPORT
278 config TRACE_IRQFLAGS_SUPPORT
285 config GENERIC_BUG_RELATIVE_POINTERS
287 depends on GENERIC_BUG
289 config GENERIC_HWEIGHT
295 config GENERIC_CALIBRATE_DELAY
299 bool "Support DMA zone" if EXPERT
303 bool "Support DMA32 zone" if EXPERT
306 config ARCH_ENABLE_MEMORY_HOTPLUG
309 config ARCH_ENABLE_MEMORY_HOTREMOVE
315 config KERNEL_MODE_NEON
318 config FIX_EARLYCON_MEM
321 config PGTABLE_LEVELS
323 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
324 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
325 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
326 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
327 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
328 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
330 config ARCH_SUPPORTS_UPROBES
333 config ARCH_PROC_KCORE_TEXT
336 config BROKEN_GAS_INST
337 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
339 config KASAN_SHADOW_OFFSET
341 depends on KASAN_GENERIC || KASAN_SW_TAGS
342 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
343 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
344 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
345 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
346 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
347 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
348 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
349 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
350 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
351 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
352 default 0xffffffffffffffff
354 source "arch/arm64/Kconfig.platforms"
356 menu "Kernel Features"
358 menu "ARM errata workarounds via the alternatives framework"
360 config ARM64_WORKAROUND_CLEAN_CACHE
363 config ARM64_ERRATUM_826319
364 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
366 select ARM64_WORKAROUND_CLEAN_CACHE
368 This option adds an alternative code sequence to work around ARM
369 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
370 AXI master interface and an L2 cache.
372 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
373 and is unable to accept a certain write via this interface, it will
374 not progress on read data presented on the read data channel and the
377 The workaround promotes data cache clean instructions to
378 data cache clean-and-invalidate.
379 Please note that this does not necessarily enable the workaround,
380 as it depends on the alternative framework, which will only patch
381 the kernel if an affected CPU is detected.
385 config ARM64_ERRATUM_827319
386 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
388 select ARM64_WORKAROUND_CLEAN_CACHE
390 This option adds an alternative code sequence to work around ARM
391 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
392 master interface and an L2 cache.
394 Under certain conditions this erratum can cause a clean line eviction
395 to occur at the same time as another transaction to the same address
396 on the AMBA 5 CHI interface, which can cause data corruption if the
397 interconnect reorders the two transactions.
399 The workaround promotes data cache clean instructions to
400 data cache clean-and-invalidate.
401 Please note that this does not necessarily enable the workaround,
402 as it depends on the alternative framework, which will only patch
403 the kernel if an affected CPU is detected.
407 config ARM64_ERRATUM_824069
408 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
410 select ARM64_WORKAROUND_CLEAN_CACHE
412 This option adds an alternative code sequence to work around ARM
413 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
414 to a coherent interconnect.
416 If a Cortex-A53 processor is executing a store or prefetch for
417 write instruction at the same time as a processor in another
418 cluster is executing a cache maintenance operation to the same
419 address, then this erratum might cause a clean cache line to be
420 incorrectly marked as dirty.
422 The workaround promotes data cache clean instructions to
423 data cache clean-and-invalidate.
424 Please note that this option does not necessarily enable the
425 workaround, as it depends on the alternative framework, which will
426 only patch the kernel if an affected CPU is detected.
430 config ARM64_ERRATUM_819472
431 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
433 select ARM64_WORKAROUND_CLEAN_CACHE
435 This option adds an alternative code sequence to work around ARM
436 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
437 present when it is connected to a coherent interconnect.
439 If the processor is executing a load and store exclusive sequence at
440 the same time as a processor in another cluster is executing a cache
441 maintenance operation to the same address, then this erratum might
442 cause data corruption.
444 The workaround promotes data cache clean instructions to
445 data cache clean-and-invalidate.
446 Please note that this does not necessarily enable the workaround,
447 as it depends on the alternative framework, which will only patch
448 the kernel if an affected CPU is detected.
452 config ARM64_ERRATUM_832075
453 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
456 This option adds an alternative code sequence to work around ARM
457 erratum 832075 on Cortex-A57 parts up to r1p2.
459 Affected Cortex-A57 parts might deadlock when exclusive load/store
460 instructions to Write-Back memory are mixed with Device loads.
462 The workaround is to promote device loads to use Load-Acquire
464 Please note that this does not necessarily enable the workaround,
465 as it depends on the alternative framework, which will only patch
466 the kernel if an affected CPU is detected.
470 config ARM64_ERRATUM_834220
471 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
475 This option adds an alternative code sequence to work around ARM
476 erratum 834220 on Cortex-A57 parts up to r1p2.
478 Affected Cortex-A57 parts might report a Stage 2 translation
479 fault as the result of a Stage 1 fault for load crossing a
480 page boundary when there is a permission or device memory
481 alignment fault at Stage 1 and a translation fault at Stage 2.
483 The workaround is to verify that the Stage 1 translation
484 doesn't generate a fault before handling the Stage 2 fault.
485 Please note that this does not necessarily enable the workaround,
486 as it depends on the alternative framework, which will only patch
487 the kernel if an affected CPU is detected.
491 config ARM64_ERRATUM_845719
492 bool "Cortex-A53: 845719: a load might read incorrect data"
496 This option adds an alternative code sequence to work around ARM
497 erratum 845719 on Cortex-A53 parts up to r0p4.
499 When running a compat (AArch32) userspace on an affected Cortex-A53
500 part, a load at EL0 from a virtual address that matches the bottom 32
501 bits of the virtual address used by a recent load at (AArch64) EL1
502 might return incorrect data.
504 The workaround is to write the contextidr_el1 register on exception
505 return to a 32-bit task.
506 Please note that this does not necessarily enable the workaround,
507 as it depends on the alternative framework, which will only patch
508 the kernel if an affected CPU is detected.
512 config ARM64_ERRATUM_843419
513 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
515 select ARM64_MODULE_PLTS if MODULES
517 This option links the kernel with '--fix-cortex-a53-843419' and
518 enables PLT support to replace certain ADRP instructions, which can
519 cause subsequent memory accesses to use an incorrect address on
520 Cortex-A53 parts up to r0p4.
524 config ARM64_ERRATUM_1024718
525 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
528 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
530 Affected Cortex-A55 cores (all revisions) could cause incorrect
531 update of the hardware dirty bit when the DBM/AP bits are updated
532 without a break-before-make. The workaround is to disable the usage
533 of hardware DBM locally on the affected cores. CPUs not affected by
534 this erratum will continue to use the feature.
538 config ARM64_ERRATUM_1418040
539 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
543 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
544 errata 1188873 and 1418040.
546 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
547 cause register corruption when accessing the timer registers
548 from AArch32 userspace.
552 config ARM64_WORKAROUND_SPECULATIVE_AT
555 config ARM64_ERRATUM_1165522
556 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
558 select ARM64_WORKAROUND_SPECULATIVE_AT
560 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
562 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
563 corrupted TLBs by speculating an AT instruction during a guest
568 config ARM64_ERRATUM_1319367
569 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
571 select ARM64_WORKAROUND_SPECULATIVE_AT
573 This option adds work arounds for ARM Cortex-A57 erratum 1319537
574 and A72 erratum 1319367
576 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
577 speculating an AT instruction during a guest context switch.
581 config ARM64_ERRATUM_1530923
582 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
584 select ARM64_WORKAROUND_SPECULATIVE_AT
586 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
588 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
589 corrupted TLBs by speculating an AT instruction during a guest
594 config ARM64_WORKAROUND_REPEAT_TLBI
597 config ARM64_ERRATUM_1286807
598 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
600 select ARM64_WORKAROUND_REPEAT_TLBI
602 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
604 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
605 address for a cacheable mapping of a location is being
606 accessed by a core while another core is remapping the virtual
607 address to a new physical page using the recommended
608 break-before-make sequence, then under very rare circumstances
609 TLBI+DSB completes before a read using the translation being
610 invalidated has been observed by other observers. The
611 workaround repeats the TLBI+DSB operation.
613 config ARM64_ERRATUM_1463225
614 bool "Cortex-A76: Software Step might prevent interrupt recognition"
617 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
619 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
620 of a system call instruction (SVC) can prevent recognition of
621 subsequent interrupts when software stepping is disabled in the
622 exception handler of the system call and either kernel debugging
623 is enabled or VHE is in use.
625 Work around the erratum by triggering a dummy step exception
626 when handling a system call from a task that is being stepped
627 in a VHE configuration of the kernel.
631 config ARM64_ERRATUM_1542419
632 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
635 This option adds a workaround for ARM Neoverse-N1 erratum
638 Affected Neoverse-N1 cores could execute a stale instruction when
639 modified by another CPU. The workaround depends on a firmware
642 Workaround the issue by hiding the DIC feature from EL0. This
643 forces user-space to perform cache maintenance.
647 config ARM64_ERRATUM_1508412
648 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
651 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
653 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
654 of a store-exclusive or read of PAR_EL1 and a load with device or
655 non-cacheable memory attributes. The workaround depends on a firmware
658 KVM guests must also have the workaround implemented or they can
661 Work around the issue by inserting DMB SY barriers around PAR_EL1
662 register reads and warning KVM users. The DMB barrier is sufficient
663 to prevent a speculative PAR_EL1 read.
667 config CAVIUM_ERRATUM_22375
668 bool "Cavium erratum 22375, 24313"
671 Enable workaround for errata 22375 and 24313.
673 This implements two gicv3-its errata workarounds for ThunderX. Both
674 with a small impact affecting only ITS table allocation.
676 erratum 22375: only alloc 8MB table size
677 erratum 24313: ignore memory access type
679 The fixes are in ITS initialization and basically ignore memory access
680 type and table size provided by the TYPER and BASER registers.
684 config CAVIUM_ERRATUM_23144
685 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
689 ITS SYNC command hang for cross node io and collections/cpu mapping.
693 config CAVIUM_ERRATUM_23154
694 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
697 The gicv3 of ThunderX requires a modified version for
698 reading the IAR status to ensure data synchronization
699 (access to icc_iar1_el1 is not sync'ed before and after).
703 config CAVIUM_ERRATUM_27456
704 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
707 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
708 instructions may cause the icache to become corrupted if it
709 contains data for a non-current ASID. The fix is to
710 invalidate the icache when changing the mm context.
714 config CAVIUM_ERRATUM_30115
715 bool "Cavium erratum 30115: Guest may disable interrupts in host"
718 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
719 1.2, and T83 Pass 1.0, KVM guest execution may disable
720 interrupts in host. Trapping both GICv3 group-0 and group-1
721 accesses sidesteps the issue.
725 config CAVIUM_TX2_ERRATUM_219
726 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
729 On Cavium ThunderX2, a load, store or prefetch instruction between a
730 TTBR update and the corresponding context synchronizing operation can
731 cause a spurious Data Abort to be delivered to any hardware thread in
734 Work around the issue by avoiding the problematic code sequence and
735 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
736 trap handler performs the corresponding register access, skips the
737 instruction and ensures context synchronization by virtue of the
742 config FUJITSU_ERRATUM_010001
743 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
746 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
747 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
748 accesses may cause undefined fault (Data abort, DFSC=0b111111).
749 This fault occurs under a specific hardware condition when a
750 load/store instruction performs an address translation using:
751 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
752 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
753 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
754 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
756 The workaround is to ensure these bits are clear in TCR_ELx.
757 The workaround only affects the Fujitsu-A64FX.
761 config HISILICON_ERRATUM_161600802
762 bool "Hip07 161600802: Erroneous redistributor VLPI base"
765 The HiSilicon Hip07 SoC uses the wrong redistributor base
766 when issued ITS commands such as VMOVP and VMAPP, and requires
767 a 128kB offset to be applied to the target address in this commands.
771 config QCOM_FALKOR_ERRATUM_1003
772 bool "Falkor E1003: Incorrect translation due to ASID change"
775 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
776 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
777 in TTBR1_EL1, this situation only occurs in the entry trampoline and
778 then only for entries in the walk cache, since the leaf translation
779 is unchanged. Work around the erratum by invalidating the walk cache
780 entries for the trampoline before entering the kernel proper.
782 config QCOM_FALKOR_ERRATUM_1009
783 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
785 select ARM64_WORKAROUND_REPEAT_TLBI
787 On Falkor v1, the CPU may prematurely complete a DSB following a
788 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
789 one more time to fix the issue.
793 config QCOM_QDF2400_ERRATUM_0065
794 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
797 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
798 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
799 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
803 config QCOM_FALKOR_ERRATUM_E1041
804 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
807 Falkor CPU may speculatively fetch instructions from an improper
808 memory location when MMU translation is changed from SCTLR_ELn[M]=1
809 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
813 config NVIDIA_CARMEL_CNP_ERRATUM
814 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
817 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
818 invalidate shared TLB entries installed by a different core, as it would
819 on standard ARM cores.
823 config SOCIONEXT_SYNQUACER_PREITS
824 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
827 Socionext Synquacer SoCs implement a separate h/w block to generate
828 MSI doorbell writes with non-zero values for the device ID.
837 default ARM64_4K_PAGES
839 Page size (translation granule) configuration.
841 config ARM64_4K_PAGES
844 This feature enables 4KB pages support.
846 config ARM64_16K_PAGES
849 The system will use 16KB pages support. AArch32 emulation
850 requires applications compiled with 16K (or a multiple of 16K)
853 config ARM64_64K_PAGES
856 This feature enables 64KB pages support (4KB by default)
857 allowing only two levels of page tables and faster TLB
858 look-up. AArch32 emulation requires applications compiled
859 with 64K aligned segments.
864 prompt "Virtual address space size"
865 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
866 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
867 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
869 Allows choosing one of multiple possible virtual address
870 space sizes. The level of translation table is determined by
871 a combination of page size and virtual address space size.
873 config ARM64_VA_BITS_36
874 bool "36-bit" if EXPERT
875 depends on ARM64_16K_PAGES
877 config ARM64_VA_BITS_39
879 depends on ARM64_4K_PAGES
881 config ARM64_VA_BITS_42
883 depends on ARM64_64K_PAGES
885 config ARM64_VA_BITS_47
887 depends on ARM64_16K_PAGES
889 config ARM64_VA_BITS_48
892 config ARM64_VA_BITS_52
894 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
896 Enable 52-bit virtual addressing for userspace when explicitly
897 requested via a hint to mmap(). The kernel will also use 52-bit
898 virtual addresses for its own mappings (provided HW support for
899 this feature is available, otherwise it reverts to 48-bit).
901 NOTE: Enabling 52-bit virtual addressing in conjunction with
902 ARMv8.3 Pointer Authentication will result in the PAC being
903 reduced from 7 bits to 3 bits, which may have a significant
904 impact on its susceptibility to brute-force attacks.
906 If unsure, select 48-bit virtual addressing instead.
910 config ARM64_FORCE_52BIT
911 bool "Force 52-bit virtual addresses for userspace"
912 depends on ARM64_VA_BITS_52 && EXPERT
914 For systems with 52-bit userspace VAs enabled, the kernel will attempt
915 to maintain compatibility with older software by providing 48-bit VAs
916 unless a hint is supplied to mmap.
918 This configuration option disables the 48-bit compatibility logic, and
919 forces all userspace addresses to be 52-bit on HW that supports it. One
920 should only enable this configuration option for stress testing userspace
921 memory management code. If unsure say N here.
925 default 36 if ARM64_VA_BITS_36
926 default 39 if ARM64_VA_BITS_39
927 default 42 if ARM64_VA_BITS_42
928 default 47 if ARM64_VA_BITS_47
929 default 48 if ARM64_VA_BITS_48
930 default 52 if ARM64_VA_BITS_52
933 prompt "Physical address space size"
934 default ARM64_PA_BITS_48
936 Choose the maximum physical address range that the kernel will
939 config ARM64_PA_BITS_48
942 config ARM64_PA_BITS_52
943 bool "52-bit (ARMv8.2)"
944 depends on ARM64_64K_PAGES
945 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
947 Enable support for a 52-bit physical address space, introduced as
948 part of the ARMv8.2-LPA extension.
950 With this enabled, the kernel will also continue to work on CPUs that
951 do not support ARMv8.2-LPA, but with some added memory overhead (and
952 minor performance overhead).
958 default 48 if ARM64_PA_BITS_48
959 default 52 if ARM64_PA_BITS_52
963 default CPU_LITTLE_ENDIAN
965 Select the endianness of data accesses performed by the CPU. Userspace
966 applications will need to be compiled and linked for the endianness
967 that is selected here.
969 config CPU_BIG_ENDIAN
970 bool "Build big-endian kernel"
971 depends on !LD_IS_LLD || LLD_VERSION >= 130000
973 Say Y if you plan on running a kernel with a big-endian userspace.
975 config CPU_LITTLE_ENDIAN
976 bool "Build little-endian kernel"
978 Say Y if you plan on running a kernel with a little-endian userspace.
979 This is usually the case for distributions targeting arm64.
984 bool "Multi-core scheduler support"
986 Multi-core scheduler support improves the CPU scheduler's decision
987 making when dealing with multi-core CPU chips at a cost of slightly
988 increased overhead in some places. If unsure say N here.
991 bool "SMT scheduler support"
993 Improves the CPU scheduler's decision making when dealing with
994 MultiThreading at a cost of slightly increased overhead in some
995 places. If unsure say N here.
998 int "Maximum number of CPUs (2-4096)"
1003 bool "Support for hot-pluggable CPUs"
1004 select GENERIC_IRQ_MIGRATION
1006 Say Y here to experiment with turning CPUs off and on. CPUs
1007 can be controlled through /sys/devices/system/cpu.
1009 # Common NUMA Features
1011 bool "NUMA Memory Allocation and Scheduler Support"
1012 select GENERIC_ARCH_NUMA
1013 select ACPI_NUMA if ACPI
1016 Enable NUMA (Non-Uniform Memory Access) support.
1018 The kernel will try to allocate memory used by a CPU on the
1019 local memory of the CPU and add some more
1020 NUMA awareness to the kernel.
1023 int "Maximum NUMA Nodes (as a power of 2)"
1026 depends on NEED_MULTIPLE_NODES
1028 Specify the maximum number of NUMA Nodes available on the target
1029 system. Increases memory reserved to accommodate various tables.
1031 config USE_PERCPU_NUMA_NODE_ID
1035 config HAVE_SETUP_PER_CPU_AREA
1039 config NEED_PER_CPU_EMBED_FIRST_CHUNK
1043 config HOLES_IN_ZONE
1046 source "kernel/Kconfig.hz"
1048 config ARCH_SPARSEMEM_ENABLE
1050 select SPARSEMEM_VMEMMAP_ENABLE
1052 config ARCH_SPARSEMEM_DEFAULT
1053 def_bool ARCH_SPARSEMEM_ENABLE
1055 config ARCH_SELECT_MEMORY_MODEL
1056 def_bool ARCH_SPARSEMEM_ENABLE
1058 config ARCH_FLATMEM_ENABLE
1061 config HW_PERF_EVENTS
1065 config SYS_SUPPORTS_HUGETLBFS
1068 config ARCH_HAS_CACHE_LINE_SIZE
1071 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
1072 def_bool y if PGTABLE_LEVELS > 2
1074 # Supported by clang >= 7.0
1075 config CC_HAVE_SHADOW_CALL_STACK
1076 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1079 bool "Enable paravirtualization code"
1081 This changes the kernel so it can modify itself when it is run
1082 under a hypervisor, potentially improving performance significantly
1083 over full virtualization.
1085 config PARAVIRT_TIME_ACCOUNTING
1086 bool "Paravirtual steal time accounting"
1089 Select this option to enable fine granularity task steal time
1090 accounting. Time spent executing other tasks in parallel with
1091 the current vCPU is discounted from the vCPU power. To account for
1092 that, there can be a small performance impact.
1094 If in doubt, say N here.
1097 depends on PM_SLEEP_SMP
1099 bool "kexec system call"
1101 kexec is a system call that implements the ability to shutdown your
1102 current kernel, and to start another kernel. It is like a reboot
1103 but it is independent of the system firmware. And like a reboot
1104 you can start any kernel with it, not just Linux.
1107 bool "kexec file based system call"
1110 This is new version of kexec system call. This system call is
1111 file based and takes file descriptors as system call argument
1112 for kernel and initramfs as opposed to list of segments as
1113 accepted by previous system call.
1116 bool "Verify kernel signature during kexec_file_load() syscall"
1117 depends on KEXEC_FILE
1119 Select this option to verify a signature with loaded kernel
1120 image. If configured, any attempt of loading a image without
1121 valid signature will fail.
1123 In addition to that option, you need to enable signature
1124 verification for the corresponding kernel image type being
1125 loaded in order for this to work.
1127 config KEXEC_IMAGE_VERIFY_SIG
1128 bool "Enable Image signature verification support"
1130 depends on KEXEC_SIG
1131 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1133 Enable Image signature verification support.
1135 comment "Support for PE file signature verification disabled"
1136 depends on KEXEC_SIG
1137 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1140 bool "Build kdump crash kernel"
1142 Generate crash dump after being started by kexec. This should
1143 be normally only set in special crash dump kernels which are
1144 loaded in the main kernel with kexec-tools into a specially
1145 reserved region and then later executed after a crash by
1148 For more details see Documentation/admin-guide/kdump/kdump.rst
1152 depends on HIBERNATION
1159 bool "Xen guest support on ARM64"
1160 depends on ARM64 && OF
1164 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1166 config FORCE_MAX_ZONEORDER
1168 default "14" if ARM64_64K_PAGES
1169 default "12" if ARM64_16K_PAGES
1172 The kernel memory allocator divides physically contiguous memory
1173 blocks into "zones", where each zone is a power of two number of
1174 pages. This option selects the largest power of two that the kernel
1175 keeps in the memory allocator. If you need to allocate very large
1176 blocks of physically contiguous memory, then you may need to
1177 increase this value.
1179 This config option is actually maximum order plus one. For example,
1180 a value of 11 means that the largest free memory block is 2^10 pages.
1182 We make sure that we can allocate upto a HugePage size for each configuration.
1184 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1186 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1187 4M allocations matching the default size used by generic code.
1189 config UNMAP_KERNEL_AT_EL0
1190 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1193 Speculation attacks against some high-performance processors can
1194 be used to bypass MMU permission checks and leak kernel data to
1195 userspace. This can be defended against by unmapping the kernel
1196 when running in userspace, mapping it back in on exception entry
1197 via a trampoline page in the vector table.
1201 config RODATA_FULL_DEFAULT_ENABLED
1202 bool "Apply r/o permissions of VM areas also to their linear aliases"
1205 Apply read-only attributes of VM areas to the linear alias of
1206 the backing pages as well. This prevents code or read-only data
1207 from being modified (inadvertently or intentionally) via another
1208 mapping of the same memory page. This additional enhancement can
1209 be turned off at runtime by passing rodata=[off|on] (and turned on
1210 with rodata=full if this option is set to 'n')
1212 This requires the linear region to be mapped down to pages,
1213 which may adversely affect performance in some cases.
1215 config ARM64_SW_TTBR0_PAN
1216 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1218 Enabling this option prevents the kernel from accessing
1219 user-space memory directly by pointing TTBR0_EL1 to a reserved
1220 zeroed area and reserved ASID. The user access routines
1221 restore the valid TTBR0_EL1 temporarily.
1223 config ARM64_TAGGED_ADDR_ABI
1224 bool "Enable the tagged user addresses syscall ABI"
1227 When this option is enabled, user applications can opt in to a
1228 relaxed ABI via prctl() allowing tagged addresses to be passed
1229 to system calls as pointer arguments. For details, see
1230 Documentation/arm64/tagged-address-abi.rst.
1233 bool "Kernel support for 32-bit EL0"
1234 depends on ARM64_4K_PAGES || EXPERT
1236 select OLD_SIGSUSPEND3
1237 select COMPAT_OLD_SIGACTION
1239 This option enables support for a 32-bit EL0 running under a 64-bit
1240 kernel at EL1. AArch32-specific components such as system calls,
1241 the user helper functions, VFP support and the ptrace interface are
1242 handled appropriately by the kernel.
1244 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1245 that you will only be able to execute AArch32 binaries that were compiled
1246 with page size aligned segments.
1248 If you want to execute 32-bit userspace applications, say Y.
1252 config KUSER_HELPERS
1253 bool "Enable kuser helpers page for 32-bit applications"
1256 Warning: disabling this option may break 32-bit user programs.
1258 Provide kuser helpers to compat tasks. The kernel provides
1259 helper code to userspace in read only form at a fixed location
1260 to allow userspace to be independent of the CPU type fitted to
1261 the system. This permits binaries to be run on ARMv4 through
1262 to ARMv8 without modification.
1264 See Documentation/arm/kernel_user_helpers.rst for details.
1266 However, the fixed address nature of these helpers can be used
1267 by ROP (return orientated programming) authors when creating
1270 If all of the binaries and libraries which run on your platform
1271 are built specifically for your platform, and make no use of
1272 these helpers, then you can turn this option off to hinder
1273 such exploits. However, in that case, if a binary or library
1274 relying on those helpers is run, it will not function correctly.
1276 Say N here only if you are absolutely certain that you do not
1277 need these helpers; otherwise, the safe option is to say Y.
1280 bool "Enable vDSO for 32-bit applications"
1281 depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1282 select GENERIC_COMPAT_VDSO
1285 Place in the process address space of 32-bit applications an
1286 ELF shared object providing fast implementations of gettimeofday
1289 You must have a 32-bit build of glibc 2.22 or later for programs
1290 to seamlessly take advantage of this.
1292 config THUMB2_COMPAT_VDSO
1293 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1294 depends on COMPAT_VDSO
1297 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1298 otherwise with '-marm'.
1300 menuconfig ARMV8_DEPRECATED
1301 bool "Emulate deprecated/obsolete ARMv8 instructions"
1304 Legacy software support may require certain instructions
1305 that have been deprecated or obsoleted in the architecture.
1307 Enable this config to enable selective emulation of these
1314 config SWP_EMULATION
1315 bool "Emulate SWP/SWPB instructions"
1317 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1318 they are always undefined. Say Y here to enable software
1319 emulation of these instructions for userspace using LDXR/STXR.
1320 This feature can be controlled at runtime with the abi.swp
1321 sysctl which is disabled by default.
1323 In some older versions of glibc [<=2.8] SWP is used during futex
1324 trylock() operations with the assumption that the code will not
1325 be preempted. This invalid assumption may be more likely to fail
1326 with SWP emulation enabled, leading to deadlock of the user
1329 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1330 on an external transaction monitoring block called a global
1331 monitor to maintain update atomicity. If your system does not
1332 implement a global monitor, this option can cause programs that
1333 perform SWP operations to uncached memory to deadlock.
1337 config CP15_BARRIER_EMULATION
1338 bool "Emulate CP15 Barrier instructions"
1340 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1341 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1342 strongly recommended to use the ISB, DSB, and DMB
1343 instructions instead.
1345 Say Y here to enable software emulation of these
1346 instructions for AArch32 userspace code. When this option is
1347 enabled, CP15 barrier usage is traced which can help
1348 identify software that needs updating. This feature can be
1349 controlled at runtime with the abi.cp15_barrier sysctl.
1353 config SETEND_EMULATION
1354 bool "Emulate SETEND instruction"
1356 The SETEND instruction alters the data-endianness of the
1357 AArch32 EL0, and is deprecated in ARMv8.
1359 Say Y here to enable software emulation of the instruction
1360 for AArch32 userspace code. This feature can be controlled
1361 at runtime with the abi.setend sysctl.
1363 Note: All the cpus on the system must have mixed endian support at EL0
1364 for this feature to be enabled. If a new CPU - which doesn't support mixed
1365 endian - is hotplugged in after this feature has been enabled, there could
1366 be unexpected results in the applications.
1373 menu "ARMv8.1 architectural features"
1375 config ARM64_HW_AFDBM
1376 bool "Support for hardware updates of the Access and Dirty page flags"
1379 The ARMv8.1 architecture extensions introduce support for
1380 hardware updates of the access and dirty information in page
1381 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1382 capable processors, accesses to pages with PTE_AF cleared will
1383 set this bit instead of raising an access flag fault.
1384 Similarly, writes to read-only pages with the DBM bit set will
1385 clear the read-only bit (AP[2]) instead of raising a
1388 Kernels built with this configuration option enabled continue
1389 to work on pre-ARMv8.1 hardware and the performance impact is
1390 minimal. If unsure, say Y.
1393 bool "Enable support for Privileged Access Never (PAN)"
1396 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1397 prevents the kernel or hypervisor from accessing user-space (EL0)
1400 Choosing this option will cause any unprotected (not using
1401 copy_to_user et al) memory access to fail with a permission fault.
1403 The feature is detected at runtime, and will remain as a 'nop'
1404 instruction if the cpu does not implement the feature.
1407 def_bool $(as-instr,.arch_extension rcpc)
1409 config ARM64_LSE_ATOMICS
1411 default ARM64_USE_LSE_ATOMICS
1412 depends on $(as-instr,.arch_extension lse)
1414 config ARM64_USE_LSE_ATOMICS
1415 bool "Atomic instructions"
1416 depends on JUMP_LABEL
1419 As part of the Large System Extensions, ARMv8.1 introduces new
1420 atomic instructions that are designed specifically to scale in
1423 Say Y here to make use of these instructions for the in-kernel
1424 atomic routines. This incurs a small overhead on CPUs that do
1425 not support these instructions and requires the kernel to be
1426 built with binutils >= 2.25 in order for the new instructions
1430 bool "Enable support for Virtualization Host Extensions (VHE)"
1433 Virtualization Host Extensions (VHE) allow the kernel to run
1434 directly at EL2 (instead of EL1) on processors that support
1435 it. This leads to better performance for KVM, as they reduce
1436 the cost of the world switch.
1438 Selecting this option allows the VHE feature to be detected
1439 at runtime, and does not affect processors that do not
1440 implement this feature.
1444 menu "ARMv8.2 architectural features"
1447 bool "Enable support for persistent memory"
1448 select ARCH_HAS_PMEM_API
1449 select ARCH_HAS_UACCESS_FLUSHCACHE
1451 Say Y to enable support for the persistent memory API based on the
1452 ARMv8.2 DCPoP feature.
1454 The feature is detected at runtime, and the kernel will use DC CVAC
1455 operations if DC CVAP is not supported (following the behaviour of
1456 DC CVAP itself if the system does not define a point of persistence).
1458 config ARM64_RAS_EXTN
1459 bool "Enable support for RAS CPU Extensions"
1462 CPUs that support the Reliability, Availability and Serviceability
1463 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1464 errors, classify them and report them to software.
1466 On CPUs with these extensions system software can use additional
1467 barriers to determine if faults are pending and read the
1468 classification from a new set of registers.
1470 Selecting this feature will allow the kernel to use these barriers
1471 and access the new registers if the system supports the extension.
1472 Platform RAS features may additionally depend on firmware support.
1475 bool "Enable support for Common Not Private (CNP) translations"
1477 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1479 Common Not Private (CNP) allows translation table entries to
1480 be shared between different PEs in the same inner shareable
1481 domain, so the hardware can use this fact to optimise the
1482 caching of such entries in the TLB.
1484 Selecting this option allows the CNP feature to be detected
1485 at runtime, and does not affect PEs that do not implement
1490 menu "ARMv8.3 architectural features"
1492 config ARM64_PTR_AUTH
1493 bool "Enable support for pointer authentication"
1495 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1496 # Modern compilers insert a .note.gnu.property section note for PAC
1497 # which is only understood by binutils starting with version 2.33.1.
1498 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1499 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1500 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1502 Pointer authentication (part of the ARMv8.3 Extensions) provides
1503 instructions for signing and authenticating pointers against secret
1504 keys, which can be used to mitigate Return Oriented Programming (ROP)
1507 This option enables these instructions at EL0 (i.e. for userspace).
1508 Choosing this option will cause the kernel to initialise secret keys
1509 for each process at exec() time, with these keys being
1510 context-switched along with the process.
1512 If the compiler supports the -mbranch-protection or
1513 -msign-return-address flag (e.g. GCC 7 or later), then this option
1514 will also cause the kernel itself to be compiled with return address
1515 protection. In this case, and if the target hardware is known to
1516 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1517 disabled with minimal loss of protection.
1519 The feature is detected at runtime. If the feature is not present in
1520 hardware it will not be advertised to userspace/KVM guest nor will it
1523 If the feature is present on the boot CPU but not on a late CPU, then
1524 the late CPU will be parked. Also, if the boot CPU does not have
1525 address auth and the late CPU has then the late CPU will still boot
1526 but with the feature disabled. On such a system, this option should
1529 This feature works with FUNCTION_GRAPH_TRACER option only if
1530 DYNAMIC_FTRACE_WITH_REGS is enabled.
1532 config CC_HAS_BRANCH_PROT_PAC_RET
1533 # GCC 9 or later, clang 8 or later
1534 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1536 config CC_HAS_SIGN_RETURN_ADDRESS
1538 def_bool $(cc-option,-msign-return-address=all)
1541 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1543 config AS_HAS_CFI_NEGATE_RA_STATE
1544 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1548 menu "ARMv8.4 architectural features"
1550 config ARM64_AMU_EXTN
1551 bool "Enable support for the Activity Monitors Unit CPU extension"
1554 The activity monitors extension is an optional extension introduced
1555 by the ARMv8.4 CPU architecture. This enables support for version 1
1556 of the activity monitors architecture, AMUv1.
1558 To enable the use of this extension on CPUs that implement it, say Y.
1560 Note that for architectural reasons, firmware _must_ implement AMU
1561 support when running on CPUs that present the activity monitors
1562 extension. The required support is present in:
1563 * Version 1.5 and later of the ARM Trusted Firmware
1565 For kernels that have this configuration enabled but boot with broken
1566 firmware, you may need to say N here until the firmware is fixed.
1567 Otherwise you may experience firmware panics or lockups when
1568 accessing the counter registers. Even if you are not observing these
1569 symptoms, the values returned by the register reads might not
1570 correctly reflect reality. Most commonly, the value read will be 0,
1571 indicating that the counter is not enabled.
1573 config AS_HAS_ARMV8_4
1574 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1576 config ARM64_TLB_RANGE
1577 bool "Enable support for tlbi range feature"
1579 depends on AS_HAS_ARMV8_4
1581 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1582 range of input addresses.
1584 The feature introduces new assembly instructions, and they were
1585 support when binutils >= 2.30.
1589 menu "ARMv8.5 architectural features"
1591 config AS_HAS_ARMV8_5
1592 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1595 bool "Branch Target Identification support"
1598 Branch Target Identification (part of the ARMv8.5 Extensions)
1599 provides a mechanism to limit the set of locations to which computed
1600 branch instructions such as BR or BLR can jump.
1602 To make use of BTI on CPUs that support it, say Y.
1604 BTI is intended to provide complementary protection to other control
1605 flow integrity protection mechanisms, such as the Pointer
1606 authentication mechanism provided as part of the ARMv8.3 Extensions.
1607 For this reason, it does not make sense to enable this option without
1608 also enabling support for pointer authentication. Thus, when
1609 enabling this option you should also select ARM64_PTR_AUTH=y.
1611 Userspace binaries must also be specifically compiled to make use of
1612 this mechanism. If you say N here or the hardware does not support
1613 BTI, such binaries can still run, but you get no additional
1614 enforcement of branch destinations.
1616 config ARM64_BTI_KERNEL
1617 bool "Use Branch Target Identification for kernel"
1619 depends on ARM64_BTI
1620 depends on ARM64_PTR_AUTH
1621 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1622 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1623 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1624 depends on !(CC_IS_CLANG && GCOV_KERNEL)
1625 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1627 Build the kernel with Branch Target Identification annotations
1628 and enable enforcement of this for kernel code. When this option
1629 is enabled and the system supports BTI all kernel code including
1630 modular code must have BTI enabled.
1632 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1633 # GCC 9 or later, clang 8 or later
1634 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1637 bool "Enable support for E0PD"
1640 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1641 that EL0 accesses made via TTBR1 always fault in constant time,
1642 providing similar benefits to KASLR as those provided by KPTI, but
1643 with lower overhead and without disrupting legitimate access to
1644 kernel memory such as SPE.
1646 This option enables E0PD for TTBR1 where available.
1649 bool "Enable support for random number generation"
1652 Random number generation (part of the ARMv8.5 Extensions)
1653 provides a high bandwidth, cryptographically secure
1654 hardware random number generator.
1656 config ARM64_AS_HAS_MTE
1657 # Initial support for MTE went in binutils 2.32.0, checked with
1658 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1659 # as a late addition to the final architecture spec (LDGM/STGM)
1660 # is only supported in the newer 2.32.x and 2.33 binutils
1661 # versions, hence the extra "stgm" instruction check below.
1662 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1665 bool "Memory Tagging Extension support"
1667 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1668 depends on AS_HAS_ARMV8_5
1669 # Required for tag checking in the uaccess routines
1670 depends on ARM64_PAN
1671 select ARCH_USES_HIGH_VMA_FLAGS
1673 Memory Tagging (part of the ARMv8.5 Extensions) provides
1674 architectural support for run-time, always-on detection of
1675 various classes of memory error to aid with software debugging
1676 to eliminate vulnerabilities arising from memory-unsafe
1679 This option enables the support for the Memory Tagging
1680 Extension at EL0 (i.e. for userspace).
1682 Selecting this option allows the feature to be detected at
1683 runtime. Any secondary CPU not implementing this feature will
1684 not be allowed a late bring-up.
1686 Userspace binaries that want to use this feature must
1687 explicitly opt in. The mechanism for the userspace is
1690 Documentation/arm64/memory-tagging-extension.rst.
1695 bool "ARM Scalable Vector Extension support"
1697 depends on !KVM || ARM64_VHE
1699 The Scalable Vector Extension (SVE) is an extension to the AArch64
1700 execution state which complements and extends the SIMD functionality
1701 of the base architecture to support much larger vectors and to enable
1702 additional vectorisation opportunities.
1704 To enable use of this extension on CPUs that implement it, say Y.
1706 On CPUs that support the SVE2 extensions, this option will enable
1709 Note that for architectural reasons, firmware _must_ implement SVE
1710 support when running on SVE capable hardware. The required support
1713 * version 1.5 and later of the ARM Trusted Firmware
1714 * the AArch64 boot wrapper since commit 5e1261e08abf
1715 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1717 For other firmware implementations, consult the firmware documentation
1720 If you need the kernel to boot on SVE-capable hardware with broken
1721 firmware, you may need to say N here until you get your firmware
1722 fixed. Otherwise, you may experience firmware panics or lockups when
1723 booting the kernel. If unsure and you are not observing these
1724 symptoms, you should assume that it is safe to say Y.
1726 CPUs that support SVE are architecturally required to support the
1727 Virtualization Host Extensions (VHE), so the kernel makes no
1728 provision for supporting SVE alongside KVM without VHE enabled.
1729 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1730 KVM in the same kernel image.
1732 config ARM64_MODULE_PLTS
1733 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1735 select HAVE_MOD_ARCH_SPECIFIC
1737 Allocate PLTs when loading modules so that jumps and calls whose
1738 targets are too far away for their relative offsets to be encoded
1739 in the instructions themselves can be bounced via veneers in the
1740 module's PLT. This allows modules to be allocated in the generic
1741 vmalloc area after the dedicated module memory area has been
1744 When running with address space randomization (KASLR), the module
1745 region itself may be too far away for ordinary relative jumps and
1746 calls, and so in that case, module PLTs are required and cannot be
1749 Specific errata workaround(s) might also force module PLTs to be
1750 enabled (ARM64_ERRATUM_843419).
1752 config ARM64_PSEUDO_NMI
1753 bool "Support for NMI-like interrupts"
1756 Adds support for mimicking Non-Maskable Interrupts through the use of
1757 GIC interrupt priority. This support requires version 3 or later of
1760 This high priority configuration for interrupts needs to be
1761 explicitly enabled by setting the kernel parameter
1762 "irqchip.gicv3_pseudo_nmi" to 1.
1767 config ARM64_DEBUG_PRIORITY_MASKING
1768 bool "Debug interrupt priority masking"
1770 This adds runtime checks to functions enabling/disabling
1771 interrupts when using priority masking. The additional checks verify
1772 the validity of ICC_PMR_EL1 when calling concerned functions.
1778 bool "Build a relocatable kernel image" if EXPERT
1779 select ARCH_HAS_RELR
1782 This builds the kernel as a Position Independent Executable (PIE),
1783 which retains all relocation metadata required to relocate the
1784 kernel binary at runtime to a different virtual address than the
1785 address it was linked at.
1786 Since AArch64 uses the RELA relocation format, this requires a
1787 relocation pass at runtime even if the kernel is loaded at the
1788 same address it was linked at.
1790 config RANDOMIZE_BASE
1791 bool "Randomize the address of the kernel image"
1792 select ARM64_MODULE_PLTS if MODULES
1795 Randomizes the virtual address at which the kernel image is
1796 loaded, as a security feature that deters exploit attempts
1797 relying on knowledge of the location of kernel internals.
1799 It is the bootloader's job to provide entropy, by passing a
1800 random u64 value in /chosen/kaslr-seed at kernel entry.
1802 When booting via the UEFI stub, it will invoke the firmware's
1803 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1804 to the kernel proper. In addition, it will randomise the physical
1805 location of the kernel Image as well.
1809 config RANDOMIZE_MODULE_REGION_FULL
1810 bool "Randomize the module region over a 4 GB range"
1811 depends on RANDOMIZE_BASE
1814 Randomizes the location of the module region inside a 4 GB window
1815 covering the core kernel. This way, it is less likely for modules
1816 to leak information about the location of core kernel data structures
1817 but it does imply that function calls between modules and the core
1818 kernel will need to be resolved via veneers in the module PLT.
1820 When this option is not set, the module region will be randomized over
1821 a limited range that contains the [_stext, _etext] interval of the
1822 core kernel, so branch relocations are always in range.
1824 config CC_HAVE_STACKPROTECTOR_SYSREG
1825 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1827 config STACKPROTECTOR_PER_TASK
1829 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1835 config ARM64_ACPI_PARKING_PROTOCOL
1836 bool "Enable support for the ARM64 ACPI parking protocol"
1839 Enable support for the ARM64 ACPI parking protocol. If disabled
1840 the kernel will not allow booting through the ARM64 ACPI parking
1841 protocol even if the corresponding data is present in the ACPI
1845 string "Default kernel command string"
1848 Provide a set of default command-line options at build time by
1849 entering them here. As a minimum, you should specify the the
1850 root device (e.g. root=/dev/nfs).
1853 prompt "Kernel command line type" if CMDLINE != ""
1854 default CMDLINE_FROM_BOOTLOADER
1856 Choose how the kernel will handle the provided default kernel
1857 command line string.
1859 config CMDLINE_FROM_BOOTLOADER
1860 bool "Use bootloader kernel arguments if available"
1862 Uses the command-line options passed by the boot loader. If
1863 the boot loader doesn't provide any, the default kernel command
1864 string provided in CMDLINE will be used.
1866 config CMDLINE_FORCE
1867 bool "Always use the default kernel command string"
1869 Always use the default kernel command string, even if the boot
1870 loader passes other arguments to the kernel.
1871 This is useful if you cannot or don't want to change the
1872 command-line options your boot loader passes to the kernel.
1880 bool "UEFI runtime support"
1881 depends on OF && !CPU_BIG_ENDIAN
1882 depends on KERNEL_MODE_NEON
1883 select ARCH_SUPPORTS_ACPI
1886 select EFI_PARAMS_FROM_FDT
1887 select EFI_RUNTIME_WRAPPERS
1889 select EFI_GENERIC_STUB
1890 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
1893 This option provides support for runtime services provided
1894 by UEFI firmware (such as non-volatile variables, realtime
1895 clock, and platform reset). A UEFI stub is also provided to
1896 allow the kernel to be booted as an EFI application. This
1897 is only useful on systems that have UEFI firmware.
1900 bool "Enable support for SMBIOS (DMI) tables"
1904 This enables SMBIOS/DMI feature for systems.
1906 This option is only useful on systems that have UEFI firmware.
1907 However, even with this option, the resultant kernel should
1908 continue to boot on existing non-UEFI platforms.
1912 config SYSVIPC_COMPAT
1914 depends on COMPAT && SYSVIPC
1916 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1918 depends on HUGETLB_PAGE && MIGRATION
1920 config ARCH_ENABLE_THP_MIGRATION
1922 depends on TRANSPARENT_HUGEPAGE
1924 menu "Power management options"
1926 source "kernel/power/Kconfig"
1928 config ARCH_HIBERNATION_POSSIBLE
1932 config ARCH_HIBERNATION_HEADER
1934 depends on HIBERNATION
1936 config ARCH_SUSPEND_POSSIBLE
1941 menu "CPU Power Management"
1943 source "drivers/cpuidle/Kconfig"
1945 source "drivers/cpufreq/Kconfig"
1949 source "drivers/firmware/Kconfig"
1951 source "drivers/acpi/Kconfig"
1953 source "arch/arm64/kvm/Kconfig"
1956 source "arch/arm64/crypto/Kconfig"