1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_WX
13 select ARCH_BINFMT_ELF_STATE
14 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
15 select ARCH_ENABLE_MEMORY_HOTPLUG
16 select ARCH_ENABLE_MEMORY_HOTREMOVE
17 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
18 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
19 select ARCH_HAS_CACHE_LINE_SIZE
20 select ARCH_HAS_DEBUG_VIRTUAL
21 select ARCH_HAS_DEBUG_VM_PGTABLE
22 select ARCH_HAS_DMA_PREP_COHERENT
23 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
24 select ARCH_HAS_FAST_MULTIPLIER
25 select ARCH_HAS_FORTIFY_SOURCE
26 select ARCH_HAS_GCOV_PROFILE_ALL
27 select ARCH_HAS_GIGANTIC_PAGE
29 select ARCH_HAS_KEEPINITRD
30 select ARCH_HAS_MEMBARRIER_SYNC_CORE
31 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
32 select ARCH_HAS_PTE_DEVMAP
33 select ARCH_HAS_PTE_SPECIAL
34 select ARCH_HAS_SETUP_DMA_OPS
35 select ARCH_HAS_SET_DIRECT_MAP
36 select ARCH_HAS_SET_MEMORY
38 select ARCH_HAS_STRICT_KERNEL_RWX
39 select ARCH_HAS_STRICT_MODULE_RWX
40 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
41 select ARCH_HAS_SYNC_DMA_FOR_CPU
42 select ARCH_HAS_SYSCALL_WRAPPER
43 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
44 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
45 select ARCH_HAS_ZONE_DMA_SET if EXPERT
46 select ARCH_HAVE_ELF_PROT
47 select ARCH_HAVE_NMI_SAFE_CMPXCHG
48 select ARCH_INLINE_READ_LOCK if !PREEMPTION
49 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
50 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
51 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
52 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
53 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
54 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
55 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
56 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
57 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
58 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
59 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
60 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
61 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
62 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
63 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
64 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
65 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
66 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
67 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
68 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
69 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
70 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
71 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
72 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
73 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
74 select ARCH_KEEP_MEMBLOCK
75 select ARCH_USE_CMPXCHG_LOCKREF
76 select ARCH_USE_GNU_PROPERTY
77 select ARCH_USE_MEMTEST
78 select ARCH_USE_QUEUED_RWLOCKS
79 select ARCH_USE_QUEUED_SPINLOCKS
80 select ARCH_USE_SYM_ANNOTATIONS
81 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
82 select ARCH_SUPPORTS_HUGETLBFS
83 select ARCH_SUPPORTS_MEMORY_FAILURE
84 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
85 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
86 select ARCH_SUPPORTS_LTO_CLANG_THIN
87 select ARCH_SUPPORTS_CFI_CLANG
88 select ARCH_SUPPORTS_ATOMIC_RMW
89 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG)
90 select ARCH_SUPPORTS_NUMA_BALANCING
91 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
92 select ARCH_WANT_DEFAULT_BPF_JIT
93 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
94 select ARCH_WANT_FRAME_POINTERS
95 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
96 select ARCH_WANT_LD_ORPHAN_WARN
97 select ARCH_WANTS_NO_INSTR
98 select ARCH_HAS_UBSAN_SANITIZE_ALL
100 select ARM_ARCH_TIMER
102 select AUDIT_ARCH_COMPAT_GENERIC
103 select ARM_GIC_V2M if PCI
105 select ARM_GIC_V3_ITS if PCI
107 select BUILDTIME_TABLE_SORT
108 select CLONE_BACKWARDS
110 select CPU_PM if (SUSPEND || CPU_IDLE)
112 select DCACHE_WORD_ACCESS
113 select DMA_DIRECT_REMAP
116 select GENERIC_ALLOCATOR
117 select GENERIC_ARCH_TOPOLOGY
118 select GENERIC_CLOCKEVENTS_BROADCAST
119 select GENERIC_CPU_AUTOPROBE
120 select GENERIC_CPU_VULNERABILITIES
121 select GENERIC_EARLY_IOREMAP
122 select GENERIC_FIND_FIRST_BIT
123 select GENERIC_IDLE_POLL_SETUP
124 select GENERIC_IRQ_IPI
125 select GENERIC_IRQ_PROBE
126 select GENERIC_IRQ_SHOW
127 select GENERIC_IRQ_SHOW_LEVEL
128 select GENERIC_LIB_DEVMEM_IS_ALLOWED
129 select GENERIC_PCI_IOMAP
130 select GENERIC_PTDUMP
131 select GENERIC_SCHED_CLOCK
132 select GENERIC_SMP_IDLE_THREAD
133 select GENERIC_TIME_VSYSCALL
134 select GENERIC_GETTIMEOFDAY
135 select GENERIC_VDSO_TIME_NS
136 select HANDLE_DOMAIN_IRQ
137 select HARDIRQS_SW_RESEND
141 select HAVE_ACPI_APEI if (ACPI && EFI)
142 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
143 select HAVE_ARCH_AUDITSYSCALL
144 select HAVE_ARCH_BITREVERSE
145 select HAVE_ARCH_COMPILER_H
146 select HAVE_ARCH_HUGE_VMAP
147 select HAVE_ARCH_JUMP_LABEL
148 select HAVE_ARCH_JUMP_LABEL_RELATIVE
149 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
150 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
151 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
152 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
153 select HAVE_ARCH_KFENCE
154 select HAVE_ARCH_KGDB
155 select HAVE_ARCH_MMAP_RND_BITS
156 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
157 select HAVE_ARCH_PFN_VALID
158 select HAVE_ARCH_PREL32_RELOCATIONS
159 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
160 select HAVE_ARCH_SECCOMP_FILTER
161 select HAVE_ARCH_STACKLEAK
162 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
163 select HAVE_ARCH_TRACEHOOK
164 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
165 select HAVE_ARCH_VMAP_STACK
166 select HAVE_ARM_SMCCC
167 select HAVE_ASM_MODVERSIONS
169 select HAVE_C_RECORDMCOUNT
170 select HAVE_CMPXCHG_DOUBLE
171 select HAVE_CMPXCHG_LOCAL
172 select HAVE_CONTEXT_TRACKING
173 select HAVE_DEBUG_KMEMLEAK
174 select HAVE_DMA_CONTIGUOUS
175 select HAVE_DYNAMIC_FTRACE
176 select HAVE_DYNAMIC_FTRACE_WITH_REGS \
177 if $(cc-option,-fpatchable-function-entry=2)
178 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
179 if DYNAMIC_FTRACE_WITH_REGS
180 select HAVE_EFFICIENT_UNALIGNED_ACCESS
182 select HAVE_FTRACE_MCOUNT_RECORD
183 select HAVE_FUNCTION_TRACER
184 select HAVE_FUNCTION_ERROR_INJECTION
185 select HAVE_FUNCTION_GRAPH_TRACER
186 select HAVE_GCC_PLUGINS
187 select HAVE_HW_BREAKPOINT if PERF_EVENTS
188 select HAVE_IRQ_TIME_ACCOUNTING
190 select HAVE_PATA_PLATFORM
191 select HAVE_PERF_EVENTS
192 select HAVE_PERF_REGS
193 select HAVE_PERF_USER_STACK_DUMP
194 select HAVE_REGS_AND_STACK_ACCESS_API
195 select HAVE_FUNCTION_ARG_ACCESS_API
196 select HAVE_FUTEX_CMPXCHG if FUTEX
197 select MMU_GATHER_RCU_TABLE_FREE
199 select HAVE_STACKPROTECTOR
200 select HAVE_SYSCALL_TRACEPOINTS
202 select HAVE_KRETPROBES
203 select HAVE_GENERIC_VDSO
204 select IOMMU_DMA if IOMMU_SUPPORT
206 select IRQ_FORCED_THREADING
207 select KASAN_VMALLOC if KASAN_GENERIC
208 select MODULES_USE_ELF_RELA
209 select NEED_DMA_MAP_STATE
210 select NEED_SG_DMA_LENGTH
212 select OF_EARLY_FLATTREE
213 select PCI_DOMAINS_GENERIC if PCI
214 select PCI_ECAM if (ACPI && PCI)
215 select PCI_SYSCALL if PCI
220 select SYSCTL_EXCEPTION_TRACE
221 select THREAD_INFO_IN_TASK
222 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
224 ARM 64-bit (AArch64) Linux support.
232 config ARM64_PAGE_SHIFT
234 default 16 if ARM64_64K_PAGES
235 default 14 if ARM64_16K_PAGES
238 config ARM64_CONT_PTE_SHIFT
240 default 5 if ARM64_64K_PAGES
241 default 7 if ARM64_16K_PAGES
244 config ARM64_CONT_PMD_SHIFT
246 default 5 if ARM64_64K_PAGES
247 default 5 if ARM64_16K_PAGES
250 config ARCH_MMAP_RND_BITS_MIN
251 default 14 if ARM64_64K_PAGES
252 default 16 if ARM64_16K_PAGES
255 # max bits determined by the following formula:
256 # VA_BITS - PAGE_SHIFT - 3
257 config ARCH_MMAP_RND_BITS_MAX
258 default 19 if ARM64_VA_BITS=36
259 default 24 if ARM64_VA_BITS=39
260 default 27 if ARM64_VA_BITS=42
261 default 30 if ARM64_VA_BITS=47
262 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
263 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
264 default 33 if ARM64_VA_BITS=48
265 default 14 if ARM64_64K_PAGES
266 default 16 if ARM64_16K_PAGES
269 config ARCH_MMAP_RND_COMPAT_BITS_MIN
270 default 7 if ARM64_64K_PAGES
271 default 9 if ARM64_16K_PAGES
274 config ARCH_MMAP_RND_COMPAT_BITS_MAX
280 config STACKTRACE_SUPPORT
283 config ILLEGAL_POINTER_VALUE
285 default 0xdead000000000000
287 config LOCKDEP_SUPPORT
290 config TRACE_IRQFLAGS_SUPPORT
297 config GENERIC_BUG_RELATIVE_POINTERS
299 depends on GENERIC_BUG
301 config GENERIC_HWEIGHT
307 config GENERIC_CALIBRATE_DELAY
310 config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
316 config KERNEL_MODE_NEON
319 config FIX_EARLYCON_MEM
322 config PGTABLE_LEVELS
324 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
325 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
326 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
327 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
328 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
329 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
331 config ARCH_SUPPORTS_UPROBES
334 config ARCH_PROC_KCORE_TEXT
337 config BROKEN_GAS_INST
338 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
340 config KASAN_SHADOW_OFFSET
342 depends on KASAN_GENERIC || KASAN_SW_TAGS
343 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
344 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
345 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
346 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
347 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
348 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
349 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
350 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
351 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
352 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
353 default 0xffffffffffffffff
355 source "arch/arm64/Kconfig.platforms"
357 menu "Kernel Features"
359 menu "ARM errata workarounds via the alternatives framework"
361 config ARM64_WORKAROUND_CLEAN_CACHE
364 config ARM64_ERRATUM_826319
365 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
367 select ARM64_WORKAROUND_CLEAN_CACHE
369 This option adds an alternative code sequence to work around ARM
370 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
371 AXI master interface and an L2 cache.
373 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
374 and is unable to accept a certain write via this interface, it will
375 not progress on read data presented on the read data channel and the
378 The workaround promotes data cache clean instructions to
379 data cache clean-and-invalidate.
380 Please note that this does not necessarily enable the workaround,
381 as it depends on the alternative framework, which will only patch
382 the kernel if an affected CPU is detected.
386 config ARM64_ERRATUM_827319
387 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
389 select ARM64_WORKAROUND_CLEAN_CACHE
391 This option adds an alternative code sequence to work around ARM
392 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
393 master interface and an L2 cache.
395 Under certain conditions this erratum can cause a clean line eviction
396 to occur at the same time as another transaction to the same address
397 on the AMBA 5 CHI interface, which can cause data corruption if the
398 interconnect reorders the two transactions.
400 The workaround promotes data cache clean instructions to
401 data cache clean-and-invalidate.
402 Please note that this does not necessarily enable the workaround,
403 as it depends on the alternative framework, which will only patch
404 the kernel if an affected CPU is detected.
408 config ARM64_ERRATUM_824069
409 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
411 select ARM64_WORKAROUND_CLEAN_CACHE
413 This option adds an alternative code sequence to work around ARM
414 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
415 to a coherent interconnect.
417 If a Cortex-A53 processor is executing a store or prefetch for
418 write instruction at the same time as a processor in another
419 cluster is executing a cache maintenance operation to the same
420 address, then this erratum might cause a clean cache line to be
421 incorrectly marked as dirty.
423 The workaround promotes data cache clean instructions to
424 data cache clean-and-invalidate.
425 Please note that this option does not necessarily enable the
426 workaround, as it depends on the alternative framework, which will
427 only patch the kernel if an affected CPU is detected.
431 config ARM64_ERRATUM_819472
432 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
434 select ARM64_WORKAROUND_CLEAN_CACHE
436 This option adds an alternative code sequence to work around ARM
437 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
438 present when it is connected to a coherent interconnect.
440 If the processor is executing a load and store exclusive sequence at
441 the same time as a processor in another cluster is executing a cache
442 maintenance operation to the same address, then this erratum might
443 cause data corruption.
445 The workaround promotes data cache clean instructions to
446 data cache clean-and-invalidate.
447 Please note that this does not necessarily enable the workaround,
448 as it depends on the alternative framework, which will only patch
449 the kernel if an affected CPU is detected.
453 config ARM64_ERRATUM_832075
454 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
457 This option adds an alternative code sequence to work around ARM
458 erratum 832075 on Cortex-A57 parts up to r1p2.
460 Affected Cortex-A57 parts might deadlock when exclusive load/store
461 instructions to Write-Back memory are mixed with Device loads.
463 The workaround is to promote device loads to use Load-Acquire
465 Please note that this does not necessarily enable the workaround,
466 as it depends on the alternative framework, which will only patch
467 the kernel if an affected CPU is detected.
471 config ARM64_ERRATUM_834220
472 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
476 This option adds an alternative code sequence to work around ARM
477 erratum 834220 on Cortex-A57 parts up to r1p2.
479 Affected Cortex-A57 parts might report a Stage 2 translation
480 fault as the result of a Stage 1 fault for load crossing a
481 page boundary when there is a permission or device memory
482 alignment fault at Stage 1 and a translation fault at Stage 2.
484 The workaround is to verify that the Stage 1 translation
485 doesn't generate a fault before handling the Stage 2 fault.
486 Please note that this does not necessarily enable the workaround,
487 as it depends on the alternative framework, which will only patch
488 the kernel if an affected CPU is detected.
492 config ARM64_ERRATUM_845719
493 bool "Cortex-A53: 845719: a load might read incorrect data"
497 This option adds an alternative code sequence to work around ARM
498 erratum 845719 on Cortex-A53 parts up to r0p4.
500 When running a compat (AArch32) userspace on an affected Cortex-A53
501 part, a load at EL0 from a virtual address that matches the bottom 32
502 bits of the virtual address used by a recent load at (AArch64) EL1
503 might return incorrect data.
505 The workaround is to write the contextidr_el1 register on exception
506 return to a 32-bit task.
507 Please note that this does not necessarily enable the workaround,
508 as it depends on the alternative framework, which will only patch
509 the kernel if an affected CPU is detected.
513 config ARM64_ERRATUM_843419
514 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
516 select ARM64_MODULE_PLTS if MODULES
518 This option links the kernel with '--fix-cortex-a53-843419' and
519 enables PLT support to replace certain ADRP instructions, which can
520 cause subsequent memory accesses to use an incorrect address on
521 Cortex-A53 parts up to r0p4.
525 config ARM64_LD_HAS_FIX_ERRATUM_843419
526 def_bool $(ld-option,--fix-cortex-a53-843419)
528 config ARM64_ERRATUM_1024718
529 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
532 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
534 Affected Cortex-A55 cores (all revisions) could cause incorrect
535 update of the hardware dirty bit when the DBM/AP bits are updated
536 without a break-before-make. The workaround is to disable the usage
537 of hardware DBM locally on the affected cores. CPUs not affected by
538 this erratum will continue to use the feature.
542 config ARM64_ERRATUM_1418040
543 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
547 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
548 errata 1188873 and 1418040.
550 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
551 cause register corruption when accessing the timer registers
552 from AArch32 userspace.
556 config ARM64_WORKAROUND_SPECULATIVE_AT
559 config ARM64_ERRATUM_1165522
560 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
562 select ARM64_WORKAROUND_SPECULATIVE_AT
564 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
566 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
567 corrupted TLBs by speculating an AT instruction during a guest
572 config ARM64_ERRATUM_1319367
573 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
575 select ARM64_WORKAROUND_SPECULATIVE_AT
577 This option adds work arounds for ARM Cortex-A57 erratum 1319537
578 and A72 erratum 1319367
580 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
581 speculating an AT instruction during a guest context switch.
585 config ARM64_ERRATUM_1530923
586 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
588 select ARM64_WORKAROUND_SPECULATIVE_AT
590 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
592 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
593 corrupted TLBs by speculating an AT instruction during a guest
598 config ARM64_WORKAROUND_REPEAT_TLBI
601 config ARM64_ERRATUM_1286807
602 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
604 select ARM64_WORKAROUND_REPEAT_TLBI
606 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
608 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
609 address for a cacheable mapping of a location is being
610 accessed by a core while another core is remapping the virtual
611 address to a new physical page using the recommended
612 break-before-make sequence, then under very rare circumstances
613 TLBI+DSB completes before a read using the translation being
614 invalidated has been observed by other observers. The
615 workaround repeats the TLBI+DSB operation.
617 config ARM64_ERRATUM_1463225
618 bool "Cortex-A76: Software Step might prevent interrupt recognition"
621 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
623 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
624 of a system call instruction (SVC) can prevent recognition of
625 subsequent interrupts when software stepping is disabled in the
626 exception handler of the system call and either kernel debugging
627 is enabled or VHE is in use.
629 Work around the erratum by triggering a dummy step exception
630 when handling a system call from a task that is being stepped
631 in a VHE configuration of the kernel.
635 config ARM64_ERRATUM_1542419
636 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
639 This option adds a workaround for ARM Neoverse-N1 erratum
642 Affected Neoverse-N1 cores could execute a stale instruction when
643 modified by another CPU. The workaround depends on a firmware
646 Workaround the issue by hiding the DIC feature from EL0. This
647 forces user-space to perform cache maintenance.
651 config ARM64_ERRATUM_1508412
652 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
655 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
657 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
658 of a store-exclusive or read of PAR_EL1 and a load with device or
659 non-cacheable memory attributes. The workaround depends on a firmware
662 KVM guests must also have the workaround implemented or they can
665 Work around the issue by inserting DMB SY barriers around PAR_EL1
666 register reads and warning KVM users. The DMB barrier is sufficient
667 to prevent a speculative PAR_EL1 read.
671 config CAVIUM_ERRATUM_22375
672 bool "Cavium erratum 22375, 24313"
675 Enable workaround for errata 22375 and 24313.
677 This implements two gicv3-its errata workarounds for ThunderX. Both
678 with a small impact affecting only ITS table allocation.
680 erratum 22375: only alloc 8MB table size
681 erratum 24313: ignore memory access type
683 The fixes are in ITS initialization and basically ignore memory access
684 type and table size provided by the TYPER and BASER registers.
688 config CAVIUM_ERRATUM_23144
689 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
693 ITS SYNC command hang for cross node io and collections/cpu mapping.
697 config CAVIUM_ERRATUM_23154
698 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
701 The gicv3 of ThunderX requires a modified version for
702 reading the IAR status to ensure data synchronization
703 (access to icc_iar1_el1 is not sync'ed before and after).
707 config CAVIUM_ERRATUM_27456
708 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
711 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
712 instructions may cause the icache to become corrupted if it
713 contains data for a non-current ASID. The fix is to
714 invalidate the icache when changing the mm context.
718 config CAVIUM_ERRATUM_30115
719 bool "Cavium erratum 30115: Guest may disable interrupts in host"
722 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
723 1.2, and T83 Pass 1.0, KVM guest execution may disable
724 interrupts in host. Trapping both GICv3 group-0 and group-1
725 accesses sidesteps the issue.
729 config CAVIUM_TX2_ERRATUM_219
730 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
733 On Cavium ThunderX2, a load, store or prefetch instruction between a
734 TTBR update and the corresponding context synchronizing operation can
735 cause a spurious Data Abort to be delivered to any hardware thread in
738 Work around the issue by avoiding the problematic code sequence and
739 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
740 trap handler performs the corresponding register access, skips the
741 instruction and ensures context synchronization by virtue of the
746 config FUJITSU_ERRATUM_010001
747 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
750 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
751 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
752 accesses may cause undefined fault (Data abort, DFSC=0b111111).
753 This fault occurs under a specific hardware condition when a
754 load/store instruction performs an address translation using:
755 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
756 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
757 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
758 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
760 The workaround is to ensure these bits are clear in TCR_ELx.
761 The workaround only affects the Fujitsu-A64FX.
765 config HISILICON_ERRATUM_161600802
766 bool "Hip07 161600802: Erroneous redistributor VLPI base"
769 The HiSilicon Hip07 SoC uses the wrong redistributor base
770 when issued ITS commands such as VMOVP and VMAPP, and requires
771 a 128kB offset to be applied to the target address in this commands.
775 config QCOM_FALKOR_ERRATUM_1003
776 bool "Falkor E1003: Incorrect translation due to ASID change"
779 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
780 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
781 in TTBR1_EL1, this situation only occurs in the entry trampoline and
782 then only for entries in the walk cache, since the leaf translation
783 is unchanged. Work around the erratum by invalidating the walk cache
784 entries for the trampoline before entering the kernel proper.
786 config QCOM_FALKOR_ERRATUM_1009
787 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
789 select ARM64_WORKAROUND_REPEAT_TLBI
791 On Falkor v1, the CPU may prematurely complete a DSB following a
792 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
793 one more time to fix the issue.
797 config QCOM_QDF2400_ERRATUM_0065
798 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
801 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
802 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
803 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
807 config QCOM_FALKOR_ERRATUM_E1041
808 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
811 Falkor CPU may speculatively fetch instructions from an improper
812 memory location when MMU translation is changed from SCTLR_ELn[M]=1
813 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
817 config NVIDIA_CARMEL_CNP_ERRATUM
818 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
821 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
822 invalidate shared TLB entries installed by a different core, as it would
823 on standard ARM cores.
827 config SOCIONEXT_SYNQUACER_PREITS
828 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
831 Socionext Synquacer SoCs implement a separate h/w block to generate
832 MSI doorbell writes with non-zero values for the device ID.
841 default ARM64_4K_PAGES
843 Page size (translation granule) configuration.
845 config ARM64_4K_PAGES
848 This feature enables 4KB pages support.
850 config ARM64_16K_PAGES
853 The system will use 16KB pages support. AArch32 emulation
854 requires applications compiled with 16K (or a multiple of 16K)
857 config ARM64_64K_PAGES
860 This feature enables 64KB pages support (4KB by default)
861 allowing only two levels of page tables and faster TLB
862 look-up. AArch32 emulation requires applications compiled
863 with 64K aligned segments.
868 prompt "Virtual address space size"
869 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
870 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
871 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
873 Allows choosing one of multiple possible virtual address
874 space sizes. The level of translation table is determined by
875 a combination of page size and virtual address space size.
877 config ARM64_VA_BITS_36
878 bool "36-bit" if EXPERT
879 depends on ARM64_16K_PAGES
881 config ARM64_VA_BITS_39
883 depends on ARM64_4K_PAGES
885 config ARM64_VA_BITS_42
887 depends on ARM64_64K_PAGES
889 config ARM64_VA_BITS_47
891 depends on ARM64_16K_PAGES
893 config ARM64_VA_BITS_48
896 config ARM64_VA_BITS_52
898 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
900 Enable 52-bit virtual addressing for userspace when explicitly
901 requested via a hint to mmap(). The kernel will also use 52-bit
902 virtual addresses for its own mappings (provided HW support for
903 this feature is available, otherwise it reverts to 48-bit).
905 NOTE: Enabling 52-bit virtual addressing in conjunction with
906 ARMv8.3 Pointer Authentication will result in the PAC being
907 reduced from 7 bits to 3 bits, which may have a significant
908 impact on its susceptibility to brute-force attacks.
910 If unsure, select 48-bit virtual addressing instead.
914 config ARM64_FORCE_52BIT
915 bool "Force 52-bit virtual addresses for userspace"
916 depends on ARM64_VA_BITS_52 && EXPERT
918 For systems with 52-bit userspace VAs enabled, the kernel will attempt
919 to maintain compatibility with older software by providing 48-bit VAs
920 unless a hint is supplied to mmap.
922 This configuration option disables the 48-bit compatibility logic, and
923 forces all userspace addresses to be 52-bit on HW that supports it. One
924 should only enable this configuration option for stress testing userspace
925 memory management code. If unsure say N here.
929 default 36 if ARM64_VA_BITS_36
930 default 39 if ARM64_VA_BITS_39
931 default 42 if ARM64_VA_BITS_42
932 default 47 if ARM64_VA_BITS_47
933 default 48 if ARM64_VA_BITS_48
934 default 52 if ARM64_VA_BITS_52
937 prompt "Physical address space size"
938 default ARM64_PA_BITS_48
940 Choose the maximum physical address range that the kernel will
943 config ARM64_PA_BITS_48
946 config ARM64_PA_BITS_52
947 bool "52-bit (ARMv8.2)"
948 depends on ARM64_64K_PAGES
949 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
951 Enable support for a 52-bit physical address space, introduced as
952 part of the ARMv8.2-LPA extension.
954 With this enabled, the kernel will also continue to work on CPUs that
955 do not support ARMv8.2-LPA, but with some added memory overhead (and
956 minor performance overhead).
962 default 48 if ARM64_PA_BITS_48
963 default 52 if ARM64_PA_BITS_52
967 default CPU_LITTLE_ENDIAN
969 Select the endianness of data accesses performed by the CPU. Userspace
970 applications will need to be compiled and linked for the endianness
971 that is selected here.
973 config CPU_BIG_ENDIAN
974 bool "Build big-endian kernel"
975 depends on !LD_IS_LLD || LLD_VERSION >= 130000
977 Say Y if you plan on running a kernel with a big-endian userspace.
979 config CPU_LITTLE_ENDIAN
980 bool "Build little-endian kernel"
982 Say Y if you plan on running a kernel with a little-endian userspace.
983 This is usually the case for distributions targeting arm64.
988 bool "Multi-core scheduler support"
990 Multi-core scheduler support improves the CPU scheduler's decision
991 making when dealing with multi-core CPU chips at a cost of slightly
992 increased overhead in some places. If unsure say N here.
995 bool "SMT scheduler support"
997 Improves the CPU scheduler's decision making when dealing with
998 MultiThreading at a cost of slightly increased overhead in some
999 places. If unsure say N here.
1002 int "Maximum number of CPUs (2-4096)"
1007 bool "Support for hot-pluggable CPUs"
1008 select GENERIC_IRQ_MIGRATION
1010 Say Y here to experiment with turning CPUs off and on. CPUs
1011 can be controlled through /sys/devices/system/cpu.
1013 # Common NUMA Features
1015 bool "NUMA Memory Allocation and Scheduler Support"
1016 select GENERIC_ARCH_NUMA
1017 select ACPI_NUMA if ACPI
1020 Enable NUMA (Non-Uniform Memory Access) support.
1022 The kernel will try to allocate memory used by a CPU on the
1023 local memory of the CPU and add some more
1024 NUMA awareness to the kernel.
1027 int "Maximum NUMA Nodes (as a power of 2)"
1032 Specify the maximum number of NUMA Nodes available on the target
1033 system. Increases memory reserved to accommodate various tables.
1035 config USE_PERCPU_NUMA_NODE_ID
1039 config HAVE_SETUP_PER_CPU_AREA
1043 config NEED_PER_CPU_EMBED_FIRST_CHUNK
1047 source "kernel/Kconfig.hz"
1049 config ARCH_SPARSEMEM_ENABLE
1051 select SPARSEMEM_VMEMMAP_ENABLE
1052 select SPARSEMEM_VMEMMAP
1054 config HW_PERF_EVENTS
1058 config ARCH_HAS_FILTER_PGPROT
1061 # Supported by clang >= 7.0
1062 config CC_HAVE_SHADOW_CALL_STACK
1063 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1066 bool "Enable paravirtualization code"
1068 This changes the kernel so it can modify itself when it is run
1069 under a hypervisor, potentially improving performance significantly
1070 over full virtualization.
1072 config PARAVIRT_TIME_ACCOUNTING
1073 bool "Paravirtual steal time accounting"
1076 Select this option to enable fine granularity task steal time
1077 accounting. Time spent executing other tasks in parallel with
1078 the current vCPU is discounted from the vCPU power. To account for
1079 that, there can be a small performance impact.
1081 If in doubt, say N here.
1084 depends on PM_SLEEP_SMP
1086 bool "kexec system call"
1088 kexec is a system call that implements the ability to shutdown your
1089 current kernel, and to start another kernel. It is like a reboot
1090 but it is independent of the system firmware. And like a reboot
1091 you can start any kernel with it, not just Linux.
1094 bool "kexec file based system call"
1096 select HAVE_IMA_KEXEC if IMA
1098 This is new version of kexec system call. This system call is
1099 file based and takes file descriptors as system call argument
1100 for kernel and initramfs as opposed to list of segments as
1101 accepted by previous system call.
1104 bool "Verify kernel signature during kexec_file_load() syscall"
1105 depends on KEXEC_FILE
1107 Select this option to verify a signature with loaded kernel
1108 image. If configured, any attempt of loading a image without
1109 valid signature will fail.
1111 In addition to that option, you need to enable signature
1112 verification for the corresponding kernel image type being
1113 loaded in order for this to work.
1115 config KEXEC_IMAGE_VERIFY_SIG
1116 bool "Enable Image signature verification support"
1118 depends on KEXEC_SIG
1119 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1121 Enable Image signature verification support.
1123 comment "Support for PE file signature verification disabled"
1124 depends on KEXEC_SIG
1125 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1128 bool "Build kdump crash kernel"
1130 Generate crash dump after being started by kexec. This should
1131 be normally only set in special crash dump kernels which are
1132 loaded in the main kernel with kexec-tools into a specially
1133 reserved region and then later executed after a crash by
1136 For more details see Documentation/admin-guide/kdump/kdump.rst
1140 depends on HIBERNATION
1147 bool "Xen guest support on ARM64"
1148 depends on ARM64 && OF
1152 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1154 config FORCE_MAX_ZONEORDER
1156 default "14" if ARM64_64K_PAGES
1157 default "12" if ARM64_16K_PAGES
1160 The kernel memory allocator divides physically contiguous memory
1161 blocks into "zones", where each zone is a power of two number of
1162 pages. This option selects the largest power of two that the kernel
1163 keeps in the memory allocator. If you need to allocate very large
1164 blocks of physically contiguous memory, then you may need to
1165 increase this value.
1167 This config option is actually maximum order plus one. For example,
1168 a value of 11 means that the largest free memory block is 2^10 pages.
1170 We make sure that we can allocate upto a HugePage size for each configuration.
1172 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1174 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1175 4M allocations matching the default size used by generic code.
1177 config UNMAP_KERNEL_AT_EL0
1178 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1181 Speculation attacks against some high-performance processors can
1182 be used to bypass MMU permission checks and leak kernel data to
1183 userspace. This can be defended against by unmapping the kernel
1184 when running in userspace, mapping it back in on exception entry
1185 via a trampoline page in the vector table.
1189 config RODATA_FULL_DEFAULT_ENABLED
1190 bool "Apply r/o permissions of VM areas also to their linear aliases"
1193 Apply read-only attributes of VM areas to the linear alias of
1194 the backing pages as well. This prevents code or read-only data
1195 from being modified (inadvertently or intentionally) via another
1196 mapping of the same memory page. This additional enhancement can
1197 be turned off at runtime by passing rodata=[off|on] (and turned on
1198 with rodata=full if this option is set to 'n')
1200 This requires the linear region to be mapped down to pages,
1201 which may adversely affect performance in some cases.
1203 config ARM64_SW_TTBR0_PAN
1204 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1206 Enabling this option prevents the kernel from accessing
1207 user-space memory directly by pointing TTBR0_EL1 to a reserved
1208 zeroed area and reserved ASID. The user access routines
1209 restore the valid TTBR0_EL1 temporarily.
1211 config ARM64_TAGGED_ADDR_ABI
1212 bool "Enable the tagged user addresses syscall ABI"
1215 When this option is enabled, user applications can opt in to a
1216 relaxed ABI via prctl() allowing tagged addresses to be passed
1217 to system calls as pointer arguments. For details, see
1218 Documentation/arm64/tagged-address-abi.rst.
1221 bool "Kernel support for 32-bit EL0"
1222 depends on ARM64_4K_PAGES || EXPERT
1224 select OLD_SIGSUSPEND3
1225 select COMPAT_OLD_SIGACTION
1227 This option enables support for a 32-bit EL0 running under a 64-bit
1228 kernel at EL1. AArch32-specific components such as system calls,
1229 the user helper functions, VFP support and the ptrace interface are
1230 handled appropriately by the kernel.
1232 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1233 that you will only be able to execute AArch32 binaries that were compiled
1234 with page size aligned segments.
1236 If you want to execute 32-bit userspace applications, say Y.
1240 config KUSER_HELPERS
1241 bool "Enable kuser helpers page for 32-bit applications"
1244 Warning: disabling this option may break 32-bit user programs.
1246 Provide kuser helpers to compat tasks. The kernel provides
1247 helper code to userspace in read only form at a fixed location
1248 to allow userspace to be independent of the CPU type fitted to
1249 the system. This permits binaries to be run on ARMv4 through
1250 to ARMv8 without modification.
1252 See Documentation/arm/kernel_user_helpers.rst for details.
1254 However, the fixed address nature of these helpers can be used
1255 by ROP (return orientated programming) authors when creating
1258 If all of the binaries and libraries which run on your platform
1259 are built specifically for your platform, and make no use of
1260 these helpers, then you can turn this option off to hinder
1261 such exploits. However, in that case, if a binary or library
1262 relying on those helpers is run, it will not function correctly.
1264 Say N here only if you are absolutely certain that you do not
1265 need these helpers; otherwise, the safe option is to say Y.
1268 bool "Enable vDSO for 32-bit applications"
1269 depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1270 select GENERIC_COMPAT_VDSO
1273 Place in the process address space of 32-bit applications an
1274 ELF shared object providing fast implementations of gettimeofday
1277 You must have a 32-bit build of glibc 2.22 or later for programs
1278 to seamlessly take advantage of this.
1280 config THUMB2_COMPAT_VDSO
1281 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1282 depends on COMPAT_VDSO
1285 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1286 otherwise with '-marm'.
1288 menuconfig ARMV8_DEPRECATED
1289 bool "Emulate deprecated/obsolete ARMv8 instructions"
1292 Legacy software support may require certain instructions
1293 that have been deprecated or obsoleted in the architecture.
1295 Enable this config to enable selective emulation of these
1302 config SWP_EMULATION
1303 bool "Emulate SWP/SWPB instructions"
1305 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1306 they are always undefined. Say Y here to enable software
1307 emulation of these instructions for userspace using LDXR/STXR.
1308 This feature can be controlled at runtime with the abi.swp
1309 sysctl which is disabled by default.
1311 In some older versions of glibc [<=2.8] SWP is used during futex
1312 trylock() operations with the assumption that the code will not
1313 be preempted. This invalid assumption may be more likely to fail
1314 with SWP emulation enabled, leading to deadlock of the user
1317 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1318 on an external transaction monitoring block called a global
1319 monitor to maintain update atomicity. If your system does not
1320 implement a global monitor, this option can cause programs that
1321 perform SWP operations to uncached memory to deadlock.
1325 config CP15_BARRIER_EMULATION
1326 bool "Emulate CP15 Barrier instructions"
1328 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1329 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1330 strongly recommended to use the ISB, DSB, and DMB
1331 instructions instead.
1333 Say Y here to enable software emulation of these
1334 instructions for AArch32 userspace code. When this option is
1335 enabled, CP15 barrier usage is traced which can help
1336 identify software that needs updating. This feature can be
1337 controlled at runtime with the abi.cp15_barrier sysctl.
1341 config SETEND_EMULATION
1342 bool "Emulate SETEND instruction"
1344 The SETEND instruction alters the data-endianness of the
1345 AArch32 EL0, and is deprecated in ARMv8.
1347 Say Y here to enable software emulation of the instruction
1348 for AArch32 userspace code. This feature can be controlled
1349 at runtime with the abi.setend sysctl.
1351 Note: All the cpus on the system must have mixed endian support at EL0
1352 for this feature to be enabled. If a new CPU - which doesn't support mixed
1353 endian - is hotplugged in after this feature has been enabled, there could
1354 be unexpected results in the applications.
1361 menu "ARMv8.1 architectural features"
1363 config ARM64_HW_AFDBM
1364 bool "Support for hardware updates of the Access and Dirty page flags"
1367 The ARMv8.1 architecture extensions introduce support for
1368 hardware updates of the access and dirty information in page
1369 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1370 capable processors, accesses to pages with PTE_AF cleared will
1371 set this bit instead of raising an access flag fault.
1372 Similarly, writes to read-only pages with the DBM bit set will
1373 clear the read-only bit (AP[2]) instead of raising a
1376 Kernels built with this configuration option enabled continue
1377 to work on pre-ARMv8.1 hardware and the performance impact is
1378 minimal. If unsure, say Y.
1381 bool "Enable support for Privileged Access Never (PAN)"
1384 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1385 prevents the kernel or hypervisor from accessing user-space (EL0)
1388 Choosing this option will cause any unprotected (not using
1389 copy_to_user et al) memory access to fail with a permission fault.
1391 The feature is detected at runtime, and will remain as a 'nop'
1392 instruction if the cpu does not implement the feature.
1395 def_bool $(as-instr,.arch_extension rcpc)
1397 config AS_HAS_LSE_ATOMICS
1398 def_bool $(as-instr,.arch_extension lse)
1400 config ARM64_LSE_ATOMICS
1402 default ARM64_USE_LSE_ATOMICS
1403 depends on AS_HAS_LSE_ATOMICS
1405 config ARM64_USE_LSE_ATOMICS
1406 bool "Atomic instructions"
1407 depends on JUMP_LABEL
1410 As part of the Large System Extensions, ARMv8.1 introduces new
1411 atomic instructions that are designed specifically to scale in
1414 Say Y here to make use of these instructions for the in-kernel
1415 atomic routines. This incurs a small overhead on CPUs that do
1416 not support these instructions and requires the kernel to be
1417 built with binutils >= 2.25 in order for the new instructions
1422 menu "ARMv8.2 architectural features"
1425 bool "Enable support for persistent memory"
1426 select ARCH_HAS_PMEM_API
1427 select ARCH_HAS_UACCESS_FLUSHCACHE
1429 Say Y to enable support for the persistent memory API based on the
1430 ARMv8.2 DCPoP feature.
1432 The feature is detected at runtime, and the kernel will use DC CVAC
1433 operations if DC CVAP is not supported (following the behaviour of
1434 DC CVAP itself if the system does not define a point of persistence).
1436 config ARM64_RAS_EXTN
1437 bool "Enable support for RAS CPU Extensions"
1440 CPUs that support the Reliability, Availability and Serviceability
1441 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1442 errors, classify them and report them to software.
1444 On CPUs with these extensions system software can use additional
1445 barriers to determine if faults are pending and read the
1446 classification from a new set of registers.
1448 Selecting this feature will allow the kernel to use these barriers
1449 and access the new registers if the system supports the extension.
1450 Platform RAS features may additionally depend on firmware support.
1453 bool "Enable support for Common Not Private (CNP) translations"
1455 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1457 Common Not Private (CNP) allows translation table entries to
1458 be shared between different PEs in the same inner shareable
1459 domain, so the hardware can use this fact to optimise the
1460 caching of such entries in the TLB.
1462 Selecting this option allows the CNP feature to be detected
1463 at runtime, and does not affect PEs that do not implement
1468 menu "ARMv8.3 architectural features"
1470 config ARM64_PTR_AUTH
1471 bool "Enable support for pointer authentication"
1474 Pointer authentication (part of the ARMv8.3 Extensions) provides
1475 instructions for signing and authenticating pointers against secret
1476 keys, which can be used to mitigate Return Oriented Programming (ROP)
1479 This option enables these instructions at EL0 (i.e. for userspace).
1480 Choosing this option will cause the kernel to initialise secret keys
1481 for each process at exec() time, with these keys being
1482 context-switched along with the process.
1484 The feature is detected at runtime. If the feature is not present in
1485 hardware it will not be advertised to userspace/KVM guest nor will it
1488 If the feature is present on the boot CPU but not on a late CPU, then
1489 the late CPU will be parked. Also, if the boot CPU does not have
1490 address auth and the late CPU has then the late CPU will still boot
1491 but with the feature disabled. On such a system, this option should
1494 config ARM64_PTR_AUTH_KERNEL
1495 bool "Use pointer authentication for kernel"
1497 depends on ARM64_PTR_AUTH
1498 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1499 # Modern compilers insert a .note.gnu.property section note for PAC
1500 # which is only understood by binutils starting with version 2.33.1.
1501 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1502 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1503 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1505 If the compiler supports the -mbranch-protection or
1506 -msign-return-address flag (e.g. GCC 7 or later), then this option
1507 will cause the kernel itself to be compiled with return address
1508 protection. In this case, and if the target hardware is known to
1509 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1510 disabled with minimal loss of protection.
1512 This feature works with FUNCTION_GRAPH_TRACER option only if
1513 DYNAMIC_FTRACE_WITH_REGS is enabled.
1515 config CC_HAS_BRANCH_PROT_PAC_RET
1516 # GCC 9 or later, clang 8 or later
1517 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1519 config CC_HAS_SIGN_RETURN_ADDRESS
1521 def_bool $(cc-option,-msign-return-address=all)
1524 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1526 config AS_HAS_CFI_NEGATE_RA_STATE
1527 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1531 menu "ARMv8.4 architectural features"
1533 config ARM64_AMU_EXTN
1534 bool "Enable support for the Activity Monitors Unit CPU extension"
1537 The activity monitors extension is an optional extension introduced
1538 by the ARMv8.4 CPU architecture. This enables support for version 1
1539 of the activity monitors architecture, AMUv1.
1541 To enable the use of this extension on CPUs that implement it, say Y.
1543 Note that for architectural reasons, firmware _must_ implement AMU
1544 support when running on CPUs that present the activity monitors
1545 extension. The required support is present in:
1546 * Version 1.5 and later of the ARM Trusted Firmware
1548 For kernels that have this configuration enabled but boot with broken
1549 firmware, you may need to say N here until the firmware is fixed.
1550 Otherwise you may experience firmware panics or lockups when
1551 accessing the counter registers. Even if you are not observing these
1552 symptoms, the values returned by the register reads might not
1553 correctly reflect reality. Most commonly, the value read will be 0,
1554 indicating that the counter is not enabled.
1556 config AS_HAS_ARMV8_4
1557 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1559 config ARM64_TLB_RANGE
1560 bool "Enable support for tlbi range feature"
1562 depends on AS_HAS_ARMV8_4
1564 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1565 range of input addresses.
1567 The feature introduces new assembly instructions, and they were
1568 support when binutils >= 2.30.
1572 menu "ARMv8.5 architectural features"
1574 config AS_HAS_ARMV8_5
1575 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1578 bool "Branch Target Identification support"
1581 Branch Target Identification (part of the ARMv8.5 Extensions)
1582 provides a mechanism to limit the set of locations to which computed
1583 branch instructions such as BR or BLR can jump.
1585 To make use of BTI on CPUs that support it, say Y.
1587 BTI is intended to provide complementary protection to other control
1588 flow integrity protection mechanisms, such as the Pointer
1589 authentication mechanism provided as part of the ARMv8.3 Extensions.
1590 For this reason, it does not make sense to enable this option without
1591 also enabling support for pointer authentication. Thus, when
1592 enabling this option you should also select ARM64_PTR_AUTH=y.
1594 Userspace binaries must also be specifically compiled to make use of
1595 this mechanism. If you say N here or the hardware does not support
1596 BTI, such binaries can still run, but you get no additional
1597 enforcement of branch destinations.
1599 config ARM64_BTI_KERNEL
1600 bool "Use Branch Target Identification for kernel"
1602 depends on ARM64_BTI
1603 depends on ARM64_PTR_AUTH_KERNEL
1604 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1605 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1606 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1607 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1608 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
1609 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1611 Build the kernel with Branch Target Identification annotations
1612 and enable enforcement of this for kernel code. When this option
1613 is enabled and the system supports BTI all kernel code including
1614 modular code must have BTI enabled.
1616 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1617 # GCC 9 or later, clang 8 or later
1618 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1621 bool "Enable support for E0PD"
1624 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1625 that EL0 accesses made via TTBR1 always fault in constant time,
1626 providing similar benefits to KASLR as those provided by KPTI, but
1627 with lower overhead and without disrupting legitimate access to
1628 kernel memory such as SPE.
1630 This option enables E0PD for TTBR1 where available.
1633 bool "Enable support for random number generation"
1636 Random number generation (part of the ARMv8.5 Extensions)
1637 provides a high bandwidth, cryptographically secure
1638 hardware random number generator.
1640 config ARM64_AS_HAS_MTE
1641 # Initial support for MTE went in binutils 2.32.0, checked with
1642 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1643 # as a late addition to the final architecture spec (LDGM/STGM)
1644 # is only supported in the newer 2.32.x and 2.33 binutils
1645 # versions, hence the extra "stgm" instruction check below.
1646 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1649 bool "Memory Tagging Extension support"
1651 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1652 depends on AS_HAS_ARMV8_5
1653 depends on AS_HAS_LSE_ATOMICS
1654 # Required for tag checking in the uaccess routines
1655 depends on ARM64_PAN
1656 select ARCH_USES_HIGH_VMA_FLAGS
1658 Memory Tagging (part of the ARMv8.5 Extensions) provides
1659 architectural support for run-time, always-on detection of
1660 various classes of memory error to aid with software debugging
1661 to eliminate vulnerabilities arising from memory-unsafe
1664 This option enables the support for the Memory Tagging
1665 Extension at EL0 (i.e. for userspace).
1667 Selecting this option allows the feature to be detected at
1668 runtime. Any secondary CPU not implementing this feature will
1669 not be allowed a late bring-up.
1671 Userspace binaries that want to use this feature must
1672 explicitly opt in. The mechanism for the userspace is
1675 Documentation/arm64/memory-tagging-extension.rst.
1679 menu "ARMv8.7 architectural features"
1682 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
1684 depends on ARM64_PAN
1686 Enhanced Privileged Access Never (EPAN) allows Privileged
1687 Access Never to be used with Execute-only mappings.
1689 The feature is detected at runtime, and will remain disabled
1690 if the cpu does not implement the feature.
1694 bool "ARM Scalable Vector Extension support"
1697 The Scalable Vector Extension (SVE) is an extension to the AArch64
1698 execution state which complements and extends the SIMD functionality
1699 of the base architecture to support much larger vectors and to enable
1700 additional vectorisation opportunities.
1702 To enable use of this extension on CPUs that implement it, say Y.
1704 On CPUs that support the SVE2 extensions, this option will enable
1707 Note that for architectural reasons, firmware _must_ implement SVE
1708 support when running on SVE capable hardware. The required support
1711 * version 1.5 and later of the ARM Trusted Firmware
1712 * the AArch64 boot wrapper since commit 5e1261e08abf
1713 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1715 For other firmware implementations, consult the firmware documentation
1718 If you need the kernel to boot on SVE-capable hardware with broken
1719 firmware, you may need to say N here until you get your firmware
1720 fixed. Otherwise, you may experience firmware panics or lockups when
1721 booting the kernel. If unsure and you are not observing these
1722 symptoms, you should assume that it is safe to say Y.
1724 config ARM64_MODULE_PLTS
1725 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1727 select HAVE_MOD_ARCH_SPECIFIC
1729 Allocate PLTs when loading modules so that jumps and calls whose
1730 targets are too far away for their relative offsets to be encoded
1731 in the instructions themselves can be bounced via veneers in the
1732 module's PLT. This allows modules to be allocated in the generic
1733 vmalloc area after the dedicated module memory area has been
1736 When running with address space randomization (KASLR), the module
1737 region itself may be too far away for ordinary relative jumps and
1738 calls, and so in that case, module PLTs are required and cannot be
1741 Specific errata workaround(s) might also force module PLTs to be
1742 enabled (ARM64_ERRATUM_843419).
1744 config ARM64_PSEUDO_NMI
1745 bool "Support for NMI-like interrupts"
1748 Adds support for mimicking Non-Maskable Interrupts through the use of
1749 GIC interrupt priority. This support requires version 3 or later of
1752 This high priority configuration for interrupts needs to be
1753 explicitly enabled by setting the kernel parameter
1754 "irqchip.gicv3_pseudo_nmi" to 1.
1759 config ARM64_DEBUG_PRIORITY_MASKING
1760 bool "Debug interrupt priority masking"
1762 This adds runtime checks to functions enabling/disabling
1763 interrupts when using priority masking. The additional checks verify
1764 the validity of ICC_PMR_EL1 when calling concerned functions.
1770 bool "Build a relocatable kernel image" if EXPERT
1771 select ARCH_HAS_RELR
1774 This builds the kernel as a Position Independent Executable (PIE),
1775 which retains all relocation metadata required to relocate the
1776 kernel binary at runtime to a different virtual address than the
1777 address it was linked at.
1778 Since AArch64 uses the RELA relocation format, this requires a
1779 relocation pass at runtime even if the kernel is loaded at the
1780 same address it was linked at.
1782 config RANDOMIZE_BASE
1783 bool "Randomize the address of the kernel image"
1784 select ARM64_MODULE_PLTS if MODULES
1787 Randomizes the virtual address at which the kernel image is
1788 loaded, as a security feature that deters exploit attempts
1789 relying on knowledge of the location of kernel internals.
1791 It is the bootloader's job to provide entropy, by passing a
1792 random u64 value in /chosen/kaslr-seed at kernel entry.
1794 When booting via the UEFI stub, it will invoke the firmware's
1795 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1796 to the kernel proper. In addition, it will randomise the physical
1797 location of the kernel Image as well.
1801 config RANDOMIZE_MODULE_REGION_FULL
1802 bool "Randomize the module region over a 2 GB range"
1803 depends on RANDOMIZE_BASE
1806 Randomizes the location of the module region inside a 2 GB window
1807 covering the core kernel. This way, it is less likely for modules
1808 to leak information about the location of core kernel data structures
1809 but it does imply that function calls between modules and the core
1810 kernel will need to be resolved via veneers in the module PLT.
1812 When this option is not set, the module region will be randomized over
1813 a limited range that contains the [_stext, _etext] interval of the
1814 core kernel, so branch relocations are almost always in range unless
1815 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this
1816 particular case of region exhaustion, modules might be able to fall
1817 back to a larger 2GB area.
1819 config CC_HAVE_STACKPROTECTOR_SYSREG
1820 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1822 config STACKPROTECTOR_PER_TASK
1824 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1830 config ARM64_ACPI_PARKING_PROTOCOL
1831 bool "Enable support for the ARM64 ACPI parking protocol"
1834 Enable support for the ARM64 ACPI parking protocol. If disabled
1835 the kernel will not allow booting through the ARM64 ACPI parking
1836 protocol even if the corresponding data is present in the ACPI
1840 string "Default kernel command string"
1843 Provide a set of default command-line options at build time by
1844 entering them here. As a minimum, you should specify the the
1845 root device (e.g. root=/dev/nfs).
1848 prompt "Kernel command line type" if CMDLINE != ""
1849 default CMDLINE_FROM_BOOTLOADER
1851 Choose how the kernel will handle the provided default kernel
1852 command line string.
1854 config CMDLINE_FROM_BOOTLOADER
1855 bool "Use bootloader kernel arguments if available"
1857 Uses the command-line options passed by the boot loader. If
1858 the boot loader doesn't provide any, the default kernel command
1859 string provided in CMDLINE will be used.
1861 config CMDLINE_FORCE
1862 bool "Always use the default kernel command string"
1864 Always use the default kernel command string, even if the boot
1865 loader passes other arguments to the kernel.
1866 This is useful if you cannot or don't want to change the
1867 command-line options your boot loader passes to the kernel.
1875 bool "UEFI runtime support"
1876 depends on OF && !CPU_BIG_ENDIAN
1877 depends on KERNEL_MODE_NEON
1878 select ARCH_SUPPORTS_ACPI
1881 select EFI_PARAMS_FROM_FDT
1882 select EFI_RUNTIME_WRAPPERS
1884 select EFI_GENERIC_STUB
1885 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
1888 This option provides support for runtime services provided
1889 by UEFI firmware (such as non-volatile variables, realtime
1890 clock, and platform reset). A UEFI stub is also provided to
1891 allow the kernel to be booted as an EFI application. This
1892 is only useful on systems that have UEFI firmware.
1895 bool "Enable support for SMBIOS (DMI) tables"
1899 This enables SMBIOS/DMI feature for systems.
1901 This option is only useful on systems that have UEFI firmware.
1902 However, even with this option, the resultant kernel should
1903 continue to boot on existing non-UEFI platforms.
1907 config SYSVIPC_COMPAT
1909 depends on COMPAT && SYSVIPC
1911 menu "Power management options"
1913 source "kernel/power/Kconfig"
1915 config ARCH_HIBERNATION_POSSIBLE
1919 config ARCH_HIBERNATION_HEADER
1921 depends on HIBERNATION
1923 config ARCH_SUSPEND_POSSIBLE
1928 menu "CPU Power Management"
1930 source "drivers/cpuidle/Kconfig"
1932 source "drivers/cpufreq/Kconfig"
1936 source "drivers/firmware/Kconfig"
1938 source "drivers/acpi/Kconfig"
1940 source "arch/arm64/kvm/Kconfig"
1943 source "arch/arm64/crypto/Kconfig"