1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_WX
13 select ARCH_BINFMT_ELF_STATE
14 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE
15 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
16 select ARCH_ENABLE_MEMORY_HOTPLUG
17 select ARCH_ENABLE_MEMORY_HOTREMOVE
18 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
19 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
20 select ARCH_HAS_CACHE_LINE_SIZE
21 select ARCH_HAS_DEBUG_VIRTUAL
22 select ARCH_HAS_DEBUG_VM_PGTABLE
23 select ARCH_HAS_DMA_PREP_COHERENT
24 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
25 select ARCH_HAS_FAST_MULTIPLIER
26 select ARCH_HAS_FORTIFY_SOURCE
27 select ARCH_HAS_GCOV_PROFILE_ALL
28 select ARCH_HAS_GIGANTIC_PAGE
30 select ARCH_HAS_KEEPINITRD
31 select ARCH_HAS_MEMBARRIER_SYNC_CORE
32 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
33 select ARCH_HAS_PTE_DEVMAP
34 select ARCH_HAS_PTE_SPECIAL
35 select ARCH_HAS_SETUP_DMA_OPS
36 select ARCH_HAS_SET_DIRECT_MAP
37 select ARCH_HAS_SET_MEMORY
39 select ARCH_HAS_STRICT_KERNEL_RWX
40 select ARCH_HAS_STRICT_MODULE_RWX
41 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
42 select ARCH_HAS_SYNC_DMA_FOR_CPU
43 select ARCH_HAS_SYSCALL_WRAPPER
44 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
45 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
46 select ARCH_HAS_ZONE_DMA_SET if EXPERT
47 select ARCH_HAVE_ELF_PROT
48 select ARCH_HAVE_NMI_SAFE_CMPXCHG
49 select ARCH_INLINE_READ_LOCK if !PREEMPTION
50 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
51 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
52 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
53 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
54 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
55 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
56 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
57 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
58 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
59 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
60 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
61 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
62 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
63 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
64 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
65 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
66 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
67 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
68 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
69 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
70 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
71 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
72 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
73 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
74 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
75 select ARCH_KEEP_MEMBLOCK
76 select ARCH_USE_CMPXCHG_LOCKREF
77 select ARCH_USE_GNU_PROPERTY
78 select ARCH_USE_MEMTEST
79 select ARCH_USE_QUEUED_RWLOCKS
80 select ARCH_USE_QUEUED_SPINLOCKS
81 select ARCH_USE_SYM_ANNOTATIONS
82 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
83 select ARCH_SUPPORTS_HUGETLBFS
84 select ARCH_SUPPORTS_MEMORY_FAILURE
85 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
86 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
87 select ARCH_SUPPORTS_LTO_CLANG_THIN
88 select ARCH_SUPPORTS_CFI_CLANG
89 select ARCH_SUPPORTS_ATOMIC_RMW
90 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
91 select ARCH_SUPPORTS_NUMA_BALANCING
92 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
93 select ARCH_WANT_DEFAULT_BPF_JIT
94 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
95 select ARCH_WANT_FRAME_POINTERS
96 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
97 select ARCH_WANT_LD_ORPHAN_WARN
98 select ARCH_WANTS_NO_INSTR
99 select ARCH_HAS_UBSAN_SANITIZE_ALL
101 select ARM_ARCH_TIMER
103 select AUDIT_ARCH_COMPAT_GENERIC
104 select ARM_GIC_V2M if PCI
106 select ARM_GIC_V3_ITS if PCI
108 select BUILDTIME_TABLE_SORT
109 select CLONE_BACKWARDS
111 select CPU_PM if (SUSPEND || CPU_IDLE)
113 select DCACHE_WORD_ACCESS
114 select DMA_DIRECT_REMAP
117 select GENERIC_ALLOCATOR
118 select GENERIC_ARCH_TOPOLOGY
119 select GENERIC_CLOCKEVENTS_BROADCAST
120 select GENERIC_CPU_AUTOPROBE
121 select GENERIC_CPU_VULNERABILITIES
122 select GENERIC_EARLY_IOREMAP
123 select GENERIC_IDLE_POLL_SETUP
124 select GENERIC_IRQ_IPI
125 select GENERIC_IRQ_PROBE
126 select GENERIC_IRQ_SHOW
127 select GENERIC_IRQ_SHOW_LEVEL
128 select GENERIC_LIB_DEVMEM_IS_ALLOWED
129 select GENERIC_PCI_IOMAP
130 select GENERIC_PTDUMP
131 select GENERIC_SCHED_CLOCK
132 select GENERIC_SMP_IDLE_THREAD
133 select GENERIC_TIME_VSYSCALL
134 select GENERIC_GETTIMEOFDAY
135 select GENERIC_VDSO_TIME_NS
136 select HARDIRQS_SW_RESEND
140 select HAVE_ACPI_APEI if (ACPI && EFI)
141 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
142 select HAVE_ARCH_AUDITSYSCALL
143 select HAVE_ARCH_BITREVERSE
144 select HAVE_ARCH_COMPILER_H
145 select HAVE_ARCH_HUGE_VMAP
146 select HAVE_ARCH_JUMP_LABEL
147 select HAVE_ARCH_JUMP_LABEL_RELATIVE
148 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
149 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
150 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
151 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
152 # Some instrumentation may be unsound, hence EXPERT
153 select HAVE_ARCH_KCSAN if EXPERT
154 select HAVE_ARCH_KFENCE
155 select HAVE_ARCH_KGDB
156 select HAVE_ARCH_MMAP_RND_BITS
157 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
158 select HAVE_ARCH_PREL32_RELOCATIONS
159 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
160 select HAVE_ARCH_SECCOMP_FILTER
161 select HAVE_ARCH_STACKLEAK
162 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
163 select HAVE_ARCH_TRACEHOOK
164 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
165 select HAVE_ARCH_VMAP_STACK
166 select HAVE_ARM_SMCCC
167 select HAVE_ASM_MODVERSIONS
169 select HAVE_C_RECORDMCOUNT
170 select HAVE_CMPXCHG_DOUBLE
171 select HAVE_CMPXCHG_LOCAL
172 select HAVE_CONTEXT_TRACKING
173 select HAVE_DEBUG_KMEMLEAK
174 select HAVE_DMA_CONTIGUOUS
175 select HAVE_DYNAMIC_FTRACE
176 select HAVE_DYNAMIC_FTRACE_WITH_REGS \
177 if $(cc-option,-fpatchable-function-entry=2)
178 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
179 if DYNAMIC_FTRACE_WITH_REGS
180 select HAVE_EFFICIENT_UNALIGNED_ACCESS
182 select HAVE_FTRACE_MCOUNT_RECORD
183 select HAVE_FUNCTION_TRACER
184 select HAVE_FUNCTION_ERROR_INJECTION
185 select HAVE_FUNCTION_GRAPH_TRACER
186 select HAVE_GCC_PLUGINS
187 select HAVE_HW_BREAKPOINT if PERF_EVENTS
188 select HAVE_IRQ_TIME_ACCOUNTING
191 select HAVE_PATA_PLATFORM
192 select HAVE_PERF_EVENTS
193 select HAVE_PERF_REGS
194 select HAVE_PERF_USER_STACK_DUMP
195 select HAVE_PREEMPT_DYNAMIC_KEY
196 select HAVE_REGS_AND_STACK_ACCESS_API
197 select HAVE_POSIX_CPU_TIMERS_TASK_WORK
198 select HAVE_FUNCTION_ARG_ACCESS_API
199 select MMU_GATHER_RCU_TABLE_FREE
201 select HAVE_STACKPROTECTOR
202 select HAVE_SYSCALL_TRACEPOINTS
204 select HAVE_KRETPROBES
205 select HAVE_GENERIC_VDSO
206 select IOMMU_DMA if IOMMU_SUPPORT
208 select IRQ_FORCED_THREADING
209 select KASAN_VMALLOC if KASAN_GENERIC
210 select MODULES_USE_ELF_RELA
211 select NEED_DMA_MAP_STATE
212 select NEED_SG_DMA_LENGTH
214 select OF_EARLY_FLATTREE
215 select PCI_DOMAINS_GENERIC if PCI
216 select PCI_ECAM if (ACPI && PCI)
217 select PCI_SYSCALL if PCI
222 select SYSCTL_EXCEPTION_TRACE
223 select THREAD_INFO_IN_TASK
224 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
225 select TRACE_IRQFLAGS_SUPPORT
227 ARM 64-bit (AArch64) Linux support.
235 config ARM64_PAGE_SHIFT
237 default 16 if ARM64_64K_PAGES
238 default 14 if ARM64_16K_PAGES
241 config ARM64_CONT_PTE_SHIFT
243 default 5 if ARM64_64K_PAGES
244 default 7 if ARM64_16K_PAGES
247 config ARM64_CONT_PMD_SHIFT
249 default 5 if ARM64_64K_PAGES
250 default 5 if ARM64_16K_PAGES
253 config ARCH_MMAP_RND_BITS_MIN
254 default 14 if ARM64_64K_PAGES
255 default 16 if ARM64_16K_PAGES
258 # max bits determined by the following formula:
259 # VA_BITS - PAGE_SHIFT - 3
260 config ARCH_MMAP_RND_BITS_MAX
261 default 19 if ARM64_VA_BITS=36
262 default 24 if ARM64_VA_BITS=39
263 default 27 if ARM64_VA_BITS=42
264 default 30 if ARM64_VA_BITS=47
265 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
266 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
267 default 33 if ARM64_VA_BITS=48
268 default 14 if ARM64_64K_PAGES
269 default 16 if ARM64_16K_PAGES
272 config ARCH_MMAP_RND_COMPAT_BITS_MIN
273 default 7 if ARM64_64K_PAGES
274 default 9 if ARM64_16K_PAGES
277 config ARCH_MMAP_RND_COMPAT_BITS_MAX
283 config STACKTRACE_SUPPORT
286 config ILLEGAL_POINTER_VALUE
288 default 0xdead000000000000
290 config LOCKDEP_SUPPORT
297 config GENERIC_BUG_RELATIVE_POINTERS
299 depends on GENERIC_BUG
301 config GENERIC_HWEIGHT
307 config GENERIC_CALIBRATE_DELAY
310 config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
316 config KERNEL_MODE_NEON
319 config FIX_EARLYCON_MEM
322 config PGTABLE_LEVELS
324 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
325 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
326 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
327 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
328 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
329 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
331 config ARCH_SUPPORTS_UPROBES
334 config ARCH_PROC_KCORE_TEXT
337 config BROKEN_GAS_INST
338 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
340 config KASAN_SHADOW_OFFSET
342 depends on KASAN_GENERIC || KASAN_SW_TAGS
343 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
344 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
345 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
346 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
347 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
348 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
349 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
350 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
351 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
352 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
353 default 0xffffffffffffffff
355 source "arch/arm64/Kconfig.platforms"
357 menu "Kernel Features"
359 menu "ARM errata workarounds via the alternatives framework"
361 config ARM64_WORKAROUND_CLEAN_CACHE
364 config ARM64_ERRATUM_826319
365 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
367 select ARM64_WORKAROUND_CLEAN_CACHE
369 This option adds an alternative code sequence to work around ARM
370 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
371 AXI master interface and an L2 cache.
373 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
374 and is unable to accept a certain write via this interface, it will
375 not progress on read data presented on the read data channel and the
378 The workaround promotes data cache clean instructions to
379 data cache clean-and-invalidate.
380 Please note that this does not necessarily enable the workaround,
381 as it depends on the alternative framework, which will only patch
382 the kernel if an affected CPU is detected.
386 config ARM64_ERRATUM_827319
387 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
389 select ARM64_WORKAROUND_CLEAN_CACHE
391 This option adds an alternative code sequence to work around ARM
392 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
393 master interface and an L2 cache.
395 Under certain conditions this erratum can cause a clean line eviction
396 to occur at the same time as another transaction to the same address
397 on the AMBA 5 CHI interface, which can cause data corruption if the
398 interconnect reorders the two transactions.
400 The workaround promotes data cache clean instructions to
401 data cache clean-and-invalidate.
402 Please note that this does not necessarily enable the workaround,
403 as it depends on the alternative framework, which will only patch
404 the kernel if an affected CPU is detected.
408 config ARM64_ERRATUM_824069
409 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
411 select ARM64_WORKAROUND_CLEAN_CACHE
413 This option adds an alternative code sequence to work around ARM
414 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
415 to a coherent interconnect.
417 If a Cortex-A53 processor is executing a store or prefetch for
418 write instruction at the same time as a processor in another
419 cluster is executing a cache maintenance operation to the same
420 address, then this erratum might cause a clean cache line to be
421 incorrectly marked as dirty.
423 The workaround promotes data cache clean instructions to
424 data cache clean-and-invalidate.
425 Please note that this option does not necessarily enable the
426 workaround, as it depends on the alternative framework, which will
427 only patch the kernel if an affected CPU is detected.
431 config ARM64_ERRATUM_819472
432 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
434 select ARM64_WORKAROUND_CLEAN_CACHE
436 This option adds an alternative code sequence to work around ARM
437 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
438 present when it is connected to a coherent interconnect.
440 If the processor is executing a load and store exclusive sequence at
441 the same time as a processor in another cluster is executing a cache
442 maintenance operation to the same address, then this erratum might
443 cause data corruption.
445 The workaround promotes data cache clean instructions to
446 data cache clean-and-invalidate.
447 Please note that this does not necessarily enable the workaround,
448 as it depends on the alternative framework, which will only patch
449 the kernel if an affected CPU is detected.
453 config ARM64_ERRATUM_832075
454 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
457 This option adds an alternative code sequence to work around ARM
458 erratum 832075 on Cortex-A57 parts up to r1p2.
460 Affected Cortex-A57 parts might deadlock when exclusive load/store
461 instructions to Write-Back memory are mixed with Device loads.
463 The workaround is to promote device loads to use Load-Acquire
465 Please note that this does not necessarily enable the workaround,
466 as it depends on the alternative framework, which will only patch
467 the kernel if an affected CPU is detected.
471 config ARM64_ERRATUM_834220
472 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
476 This option adds an alternative code sequence to work around ARM
477 erratum 834220 on Cortex-A57 parts up to r1p2.
479 Affected Cortex-A57 parts might report a Stage 2 translation
480 fault as the result of a Stage 1 fault for load crossing a
481 page boundary when there is a permission or device memory
482 alignment fault at Stage 1 and a translation fault at Stage 2.
484 The workaround is to verify that the Stage 1 translation
485 doesn't generate a fault before handling the Stage 2 fault.
486 Please note that this does not necessarily enable the workaround,
487 as it depends on the alternative framework, which will only patch
488 the kernel if an affected CPU is detected.
492 config ARM64_ERRATUM_845719
493 bool "Cortex-A53: 845719: a load might read incorrect data"
497 This option adds an alternative code sequence to work around ARM
498 erratum 845719 on Cortex-A53 parts up to r0p4.
500 When running a compat (AArch32) userspace on an affected Cortex-A53
501 part, a load at EL0 from a virtual address that matches the bottom 32
502 bits of the virtual address used by a recent load at (AArch64) EL1
503 might return incorrect data.
505 The workaround is to write the contextidr_el1 register on exception
506 return to a 32-bit task.
507 Please note that this does not necessarily enable the workaround,
508 as it depends on the alternative framework, which will only patch
509 the kernel if an affected CPU is detected.
513 config ARM64_ERRATUM_843419
514 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
516 select ARM64_MODULE_PLTS if MODULES
518 This option links the kernel with '--fix-cortex-a53-843419' and
519 enables PLT support to replace certain ADRP instructions, which can
520 cause subsequent memory accesses to use an incorrect address on
521 Cortex-A53 parts up to r0p4.
525 config ARM64_LD_HAS_FIX_ERRATUM_843419
526 def_bool $(ld-option,--fix-cortex-a53-843419)
528 config ARM64_ERRATUM_1024718
529 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
532 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
534 Affected Cortex-A55 cores (all revisions) could cause incorrect
535 update of the hardware dirty bit when the DBM/AP bits are updated
536 without a break-before-make. The workaround is to disable the usage
537 of hardware DBM locally on the affected cores. CPUs not affected by
538 this erratum will continue to use the feature.
542 config ARM64_ERRATUM_1418040
543 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
547 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
548 errata 1188873 and 1418040.
550 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
551 cause register corruption when accessing the timer registers
552 from AArch32 userspace.
556 config ARM64_WORKAROUND_SPECULATIVE_AT
559 config ARM64_ERRATUM_1165522
560 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
562 select ARM64_WORKAROUND_SPECULATIVE_AT
564 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
566 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
567 corrupted TLBs by speculating an AT instruction during a guest
572 config ARM64_ERRATUM_1319367
573 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
575 select ARM64_WORKAROUND_SPECULATIVE_AT
577 This option adds work arounds for ARM Cortex-A57 erratum 1319537
578 and A72 erratum 1319367
580 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
581 speculating an AT instruction during a guest context switch.
585 config ARM64_ERRATUM_1530923
586 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
588 select ARM64_WORKAROUND_SPECULATIVE_AT
590 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
592 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
593 corrupted TLBs by speculating an AT instruction during a guest
598 config ARM64_WORKAROUND_REPEAT_TLBI
601 config ARM64_ERRATUM_1286807
602 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
604 select ARM64_WORKAROUND_REPEAT_TLBI
606 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
608 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
609 address for a cacheable mapping of a location is being
610 accessed by a core while another core is remapping the virtual
611 address to a new physical page using the recommended
612 break-before-make sequence, then under very rare circumstances
613 TLBI+DSB completes before a read using the translation being
614 invalidated has been observed by other observers. The
615 workaround repeats the TLBI+DSB operation.
617 config ARM64_ERRATUM_1463225
618 bool "Cortex-A76: Software Step might prevent interrupt recognition"
621 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
623 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
624 of a system call instruction (SVC) can prevent recognition of
625 subsequent interrupts when software stepping is disabled in the
626 exception handler of the system call and either kernel debugging
627 is enabled or VHE is in use.
629 Work around the erratum by triggering a dummy step exception
630 when handling a system call from a task that is being stepped
631 in a VHE configuration of the kernel.
635 config ARM64_ERRATUM_1542419
636 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
639 This option adds a workaround for ARM Neoverse-N1 erratum
642 Affected Neoverse-N1 cores could execute a stale instruction when
643 modified by another CPU. The workaround depends on a firmware
646 Workaround the issue by hiding the DIC feature from EL0. This
647 forces user-space to perform cache maintenance.
651 config ARM64_ERRATUM_1508412
652 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
655 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
657 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
658 of a store-exclusive or read of PAR_EL1 and a load with device or
659 non-cacheable memory attributes. The workaround depends on a firmware
662 KVM guests must also have the workaround implemented or they can
665 Work around the issue by inserting DMB SY barriers around PAR_EL1
666 register reads and warning KVM users. The DMB barrier is sufficient
667 to prevent a speculative PAR_EL1 read.
671 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
674 config ARM64_ERRATUM_2119858
675 bool "Cortex-A710: 2119858: workaround TRBE overwriting trace data in FILL mode"
677 depends on CORESIGHT_TRBE
678 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
680 This option adds the workaround for ARM Cortex-A710 erratum 2119858.
682 Affected Cortex-A710 cores could overwrite up to 3 cache lines of trace
683 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
684 the event of a WRAP event.
686 Work around the issue by always making sure we move the TRBPTR_EL1 by
687 256 bytes before enabling the buffer and filling the first 256 bytes of
688 the buffer with ETM ignore packets upon disabling.
692 config ARM64_ERRATUM_2139208
693 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
695 depends on CORESIGHT_TRBE
696 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
698 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
700 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
701 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
702 the event of a WRAP event.
704 Work around the issue by always making sure we move the TRBPTR_EL1 by
705 256 bytes before enabling the buffer and filling the first 256 bytes of
706 the buffer with ETM ignore packets upon disabling.
710 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
713 config ARM64_ERRATUM_2054223
714 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
716 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
718 Enable workaround for ARM Cortex-A710 erratum 2054223
720 Affected cores may fail to flush the trace data on a TSB instruction, when
721 the PE is in trace prohibited state. This will cause losing a few bytes
724 Workaround is to issue two TSB consecutively on affected cores.
728 config ARM64_ERRATUM_2067961
729 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
731 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
733 Enable workaround for ARM Neoverse-N2 erratum 2067961
735 Affected cores may fail to flush the trace data on a TSB instruction, when
736 the PE is in trace prohibited state. This will cause losing a few bytes
739 Workaround is to issue two TSB consecutively on affected cores.
743 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
746 config ARM64_ERRATUM_2253138
747 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
748 depends on CORESIGHT_TRBE
750 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
752 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
754 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
755 for TRBE. Under some conditions, the TRBE might generate a write to the next
756 virtually addressed page following the last page of the TRBE address space
757 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
759 Work around this in the driver by always making sure that there is a
760 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
764 config ARM64_ERRATUM_2224489
765 bool "Cortex-A710: 2224489: workaround TRBE writing to address out-of-range"
766 depends on CORESIGHT_TRBE
768 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
770 This option adds the workaround for ARM Cortex-A710 erratum 2224489.
772 Affected Cortex-A710 cores might write to an out-of-range address, not reserved
773 for TRBE. Under some conditions, the TRBE might generate a write to the next
774 virtually addressed page following the last page of the TRBE address space
775 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
777 Work around this in the driver by always making sure that there is a
778 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
782 config CAVIUM_ERRATUM_22375
783 bool "Cavium erratum 22375, 24313"
786 Enable workaround for errata 22375 and 24313.
788 This implements two gicv3-its errata workarounds for ThunderX. Both
789 with a small impact affecting only ITS table allocation.
791 erratum 22375: only alloc 8MB table size
792 erratum 24313: ignore memory access type
794 The fixes are in ITS initialization and basically ignore memory access
795 type and table size provided by the TYPER and BASER registers.
799 config CAVIUM_ERRATUM_23144
800 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
804 ITS SYNC command hang for cross node io and collections/cpu mapping.
808 config CAVIUM_ERRATUM_23154
809 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
812 The gicv3 of ThunderX requires a modified version for
813 reading the IAR status to ensure data synchronization
814 (access to icc_iar1_el1 is not sync'ed before and after).
818 config CAVIUM_ERRATUM_27456
819 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
822 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
823 instructions may cause the icache to become corrupted if it
824 contains data for a non-current ASID. The fix is to
825 invalidate the icache when changing the mm context.
829 config CAVIUM_ERRATUM_30115
830 bool "Cavium erratum 30115: Guest may disable interrupts in host"
833 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
834 1.2, and T83 Pass 1.0, KVM guest execution may disable
835 interrupts in host. Trapping both GICv3 group-0 and group-1
836 accesses sidesteps the issue.
840 config CAVIUM_TX2_ERRATUM_219
841 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
844 On Cavium ThunderX2, a load, store or prefetch instruction between a
845 TTBR update and the corresponding context synchronizing operation can
846 cause a spurious Data Abort to be delivered to any hardware thread in
849 Work around the issue by avoiding the problematic code sequence and
850 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
851 trap handler performs the corresponding register access, skips the
852 instruction and ensures context synchronization by virtue of the
857 config FUJITSU_ERRATUM_010001
858 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
861 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
862 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
863 accesses may cause undefined fault (Data abort, DFSC=0b111111).
864 This fault occurs under a specific hardware condition when a
865 load/store instruction performs an address translation using:
866 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
867 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
868 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
869 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
871 The workaround is to ensure these bits are clear in TCR_ELx.
872 The workaround only affects the Fujitsu-A64FX.
876 config HISILICON_ERRATUM_161600802
877 bool "Hip07 161600802: Erroneous redistributor VLPI base"
880 The HiSilicon Hip07 SoC uses the wrong redistributor base
881 when issued ITS commands such as VMOVP and VMAPP, and requires
882 a 128kB offset to be applied to the target address in this commands.
886 config QCOM_FALKOR_ERRATUM_1003
887 bool "Falkor E1003: Incorrect translation due to ASID change"
890 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
891 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
892 in TTBR1_EL1, this situation only occurs in the entry trampoline and
893 then only for entries in the walk cache, since the leaf translation
894 is unchanged. Work around the erratum by invalidating the walk cache
895 entries for the trampoline before entering the kernel proper.
897 config QCOM_FALKOR_ERRATUM_1009
898 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
900 select ARM64_WORKAROUND_REPEAT_TLBI
902 On Falkor v1, the CPU may prematurely complete a DSB following a
903 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
904 one more time to fix the issue.
908 config QCOM_QDF2400_ERRATUM_0065
909 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
912 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
913 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
914 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
918 config QCOM_FALKOR_ERRATUM_E1041
919 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
922 Falkor CPU may speculatively fetch instructions from an improper
923 memory location when MMU translation is changed from SCTLR_ELn[M]=1
924 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
928 config NVIDIA_CARMEL_CNP_ERRATUM
929 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
932 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
933 invalidate shared TLB entries installed by a different core, as it would
934 on standard ARM cores.
938 config SOCIONEXT_SYNQUACER_PREITS
939 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
942 Socionext Synquacer SoCs implement a separate h/w block to generate
943 MSI doorbell writes with non-zero values for the device ID.
952 default ARM64_4K_PAGES
954 Page size (translation granule) configuration.
956 config ARM64_4K_PAGES
959 This feature enables 4KB pages support.
961 config ARM64_16K_PAGES
964 The system will use 16KB pages support. AArch32 emulation
965 requires applications compiled with 16K (or a multiple of 16K)
968 config ARM64_64K_PAGES
971 This feature enables 64KB pages support (4KB by default)
972 allowing only two levels of page tables and faster TLB
973 look-up. AArch32 emulation requires applications compiled
974 with 64K aligned segments.
979 prompt "Virtual address space size"
980 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
981 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
982 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
984 Allows choosing one of multiple possible virtual address
985 space sizes. The level of translation table is determined by
986 a combination of page size and virtual address space size.
988 config ARM64_VA_BITS_36
989 bool "36-bit" if EXPERT
990 depends on ARM64_16K_PAGES
992 config ARM64_VA_BITS_39
994 depends on ARM64_4K_PAGES
996 config ARM64_VA_BITS_42
998 depends on ARM64_64K_PAGES
1000 config ARM64_VA_BITS_47
1002 depends on ARM64_16K_PAGES
1004 config ARM64_VA_BITS_48
1007 config ARM64_VA_BITS_52
1009 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
1011 Enable 52-bit virtual addressing for userspace when explicitly
1012 requested via a hint to mmap(). The kernel will also use 52-bit
1013 virtual addresses for its own mappings (provided HW support for
1014 this feature is available, otherwise it reverts to 48-bit).
1016 NOTE: Enabling 52-bit virtual addressing in conjunction with
1017 ARMv8.3 Pointer Authentication will result in the PAC being
1018 reduced from 7 bits to 3 bits, which may have a significant
1019 impact on its susceptibility to brute-force attacks.
1021 If unsure, select 48-bit virtual addressing instead.
1025 config ARM64_FORCE_52BIT
1026 bool "Force 52-bit virtual addresses for userspace"
1027 depends on ARM64_VA_BITS_52 && EXPERT
1029 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1030 to maintain compatibility with older software by providing 48-bit VAs
1031 unless a hint is supplied to mmap.
1033 This configuration option disables the 48-bit compatibility logic, and
1034 forces all userspace addresses to be 52-bit on HW that supports it. One
1035 should only enable this configuration option for stress testing userspace
1036 memory management code. If unsure say N here.
1038 config ARM64_VA_BITS
1040 default 36 if ARM64_VA_BITS_36
1041 default 39 if ARM64_VA_BITS_39
1042 default 42 if ARM64_VA_BITS_42
1043 default 47 if ARM64_VA_BITS_47
1044 default 48 if ARM64_VA_BITS_48
1045 default 52 if ARM64_VA_BITS_52
1048 prompt "Physical address space size"
1049 default ARM64_PA_BITS_48
1051 Choose the maximum physical address range that the kernel will
1054 config ARM64_PA_BITS_48
1057 config ARM64_PA_BITS_52
1058 bool "52-bit (ARMv8.2)"
1059 depends on ARM64_64K_PAGES
1060 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1062 Enable support for a 52-bit physical address space, introduced as
1063 part of the ARMv8.2-LPA extension.
1065 With this enabled, the kernel will also continue to work on CPUs that
1066 do not support ARMv8.2-LPA, but with some added memory overhead (and
1067 minor performance overhead).
1071 config ARM64_PA_BITS
1073 default 48 if ARM64_PA_BITS_48
1074 default 52 if ARM64_PA_BITS_52
1078 default CPU_LITTLE_ENDIAN
1080 Select the endianness of data accesses performed by the CPU. Userspace
1081 applications will need to be compiled and linked for the endianness
1082 that is selected here.
1084 config CPU_BIG_ENDIAN
1085 bool "Build big-endian kernel"
1086 depends on !LD_IS_LLD || LLD_VERSION >= 130000
1088 Say Y if you plan on running a kernel with a big-endian userspace.
1090 config CPU_LITTLE_ENDIAN
1091 bool "Build little-endian kernel"
1093 Say Y if you plan on running a kernel with a little-endian userspace.
1094 This is usually the case for distributions targeting arm64.
1099 bool "Multi-core scheduler support"
1101 Multi-core scheduler support improves the CPU scheduler's decision
1102 making when dealing with multi-core CPU chips at a cost of slightly
1103 increased overhead in some places. If unsure say N here.
1105 config SCHED_CLUSTER
1106 bool "Cluster scheduler support"
1108 Cluster scheduler support improves the CPU scheduler's decision
1109 making when dealing with machines that have clusters of CPUs.
1110 Cluster usually means a couple of CPUs which are placed closely
1111 by sharing mid-level caches, last-level cache tags or internal
1115 bool "SMT scheduler support"
1117 Improves the CPU scheduler's decision making when dealing with
1118 MultiThreading at a cost of slightly increased overhead in some
1119 places. If unsure say N here.
1122 int "Maximum number of CPUs (2-4096)"
1127 bool "Support for hot-pluggable CPUs"
1128 select GENERIC_IRQ_MIGRATION
1130 Say Y here to experiment with turning CPUs off and on. CPUs
1131 can be controlled through /sys/devices/system/cpu.
1133 # Common NUMA Features
1135 bool "NUMA Memory Allocation and Scheduler Support"
1136 select GENERIC_ARCH_NUMA
1137 select ACPI_NUMA if ACPI
1139 select HAVE_SETUP_PER_CPU_AREA
1140 select NEED_PER_CPU_EMBED_FIRST_CHUNK
1141 select NEED_PER_CPU_PAGE_FIRST_CHUNK
1142 select USE_PERCPU_NUMA_NODE_ID
1144 Enable NUMA (Non-Uniform Memory Access) support.
1146 The kernel will try to allocate memory used by a CPU on the
1147 local memory of the CPU and add some more
1148 NUMA awareness to the kernel.
1151 int "Maximum NUMA Nodes (as a power of 2)"
1156 Specify the maximum number of NUMA Nodes available on the target
1157 system. Increases memory reserved to accommodate various tables.
1159 source "kernel/Kconfig.hz"
1161 config ARCH_SPARSEMEM_ENABLE
1163 select SPARSEMEM_VMEMMAP_ENABLE
1164 select SPARSEMEM_VMEMMAP
1166 config HW_PERF_EVENTS
1170 config ARCH_HAS_FILTER_PGPROT
1173 # Supported by clang >= 7.0
1174 config CC_HAVE_SHADOW_CALL_STACK
1175 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1178 bool "Enable paravirtualization code"
1180 This changes the kernel so it can modify itself when it is run
1181 under a hypervisor, potentially improving performance significantly
1182 over full virtualization.
1184 config PARAVIRT_TIME_ACCOUNTING
1185 bool "Paravirtual steal time accounting"
1188 Select this option to enable fine granularity task steal time
1189 accounting. Time spent executing other tasks in parallel with
1190 the current vCPU is discounted from the vCPU power. To account for
1191 that, there can be a small performance impact.
1193 If in doubt, say N here.
1196 depends on PM_SLEEP_SMP
1198 bool "kexec system call"
1200 kexec is a system call that implements the ability to shutdown your
1201 current kernel, and to start another kernel. It is like a reboot
1202 but it is independent of the system firmware. And like a reboot
1203 you can start any kernel with it, not just Linux.
1206 bool "kexec file based system call"
1208 select HAVE_IMA_KEXEC if IMA
1210 This is new version of kexec system call. This system call is
1211 file based and takes file descriptors as system call argument
1212 for kernel and initramfs as opposed to list of segments as
1213 accepted by previous system call.
1216 bool "Verify kernel signature during kexec_file_load() syscall"
1217 depends on KEXEC_FILE
1219 Select this option to verify a signature with loaded kernel
1220 image. If configured, any attempt of loading a image without
1221 valid signature will fail.
1223 In addition to that option, you need to enable signature
1224 verification for the corresponding kernel image type being
1225 loaded in order for this to work.
1227 config KEXEC_IMAGE_VERIFY_SIG
1228 bool "Enable Image signature verification support"
1230 depends on KEXEC_SIG
1231 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1233 Enable Image signature verification support.
1235 comment "Support for PE file signature verification disabled"
1236 depends on KEXEC_SIG
1237 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1240 bool "Build kdump crash kernel"
1242 Generate crash dump after being started by kexec. This should
1243 be normally only set in special crash dump kernels which are
1244 loaded in the main kernel with kexec-tools into a specially
1245 reserved region and then later executed after a crash by
1248 For more details see Documentation/admin-guide/kdump/kdump.rst
1252 depends on HIBERNATION || KEXEC_CORE
1259 bool "Xen guest support on ARM64"
1260 depends on ARM64 && OF
1264 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1266 config FORCE_MAX_ZONEORDER
1268 default "14" if ARM64_64K_PAGES
1269 default "12" if ARM64_16K_PAGES
1272 The kernel memory allocator divides physically contiguous memory
1273 blocks into "zones", where each zone is a power of two number of
1274 pages. This option selects the largest power of two that the kernel
1275 keeps in the memory allocator. If you need to allocate very large
1276 blocks of physically contiguous memory, then you may need to
1277 increase this value.
1279 This config option is actually maximum order plus one. For example,
1280 a value of 11 means that the largest free memory block is 2^10 pages.
1282 We make sure that we can allocate upto a HugePage size for each configuration.
1284 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1286 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1287 4M allocations matching the default size used by generic code.
1289 config UNMAP_KERNEL_AT_EL0
1290 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1293 Speculation attacks against some high-performance processors can
1294 be used to bypass MMU permission checks and leak kernel data to
1295 userspace. This can be defended against by unmapping the kernel
1296 when running in userspace, mapping it back in on exception entry
1297 via a trampoline page in the vector table.
1301 config RODATA_FULL_DEFAULT_ENABLED
1302 bool "Apply r/o permissions of VM areas also to their linear aliases"
1305 Apply read-only attributes of VM areas to the linear alias of
1306 the backing pages as well. This prevents code or read-only data
1307 from being modified (inadvertently or intentionally) via another
1308 mapping of the same memory page. This additional enhancement can
1309 be turned off at runtime by passing rodata=[off|on] (and turned on
1310 with rodata=full if this option is set to 'n')
1312 This requires the linear region to be mapped down to pages,
1313 which may adversely affect performance in some cases.
1315 config ARM64_SW_TTBR0_PAN
1316 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1318 Enabling this option prevents the kernel from accessing
1319 user-space memory directly by pointing TTBR0_EL1 to a reserved
1320 zeroed area and reserved ASID. The user access routines
1321 restore the valid TTBR0_EL1 temporarily.
1323 config ARM64_TAGGED_ADDR_ABI
1324 bool "Enable the tagged user addresses syscall ABI"
1327 When this option is enabled, user applications can opt in to a
1328 relaxed ABI via prctl() allowing tagged addresses to be passed
1329 to system calls as pointer arguments. For details, see
1330 Documentation/arm64/tagged-address-abi.rst.
1333 bool "Kernel support for 32-bit EL0"
1334 depends on ARM64_4K_PAGES || EXPERT
1336 select OLD_SIGSUSPEND3
1337 select COMPAT_OLD_SIGACTION
1339 This option enables support for a 32-bit EL0 running under a 64-bit
1340 kernel at EL1. AArch32-specific components such as system calls,
1341 the user helper functions, VFP support and the ptrace interface are
1342 handled appropriately by the kernel.
1344 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1345 that you will only be able to execute AArch32 binaries that were compiled
1346 with page size aligned segments.
1348 If you want to execute 32-bit userspace applications, say Y.
1352 config KUSER_HELPERS
1353 bool "Enable kuser helpers page for 32-bit applications"
1356 Warning: disabling this option may break 32-bit user programs.
1358 Provide kuser helpers to compat tasks. The kernel provides
1359 helper code to userspace in read only form at a fixed location
1360 to allow userspace to be independent of the CPU type fitted to
1361 the system. This permits binaries to be run on ARMv4 through
1362 to ARMv8 without modification.
1364 See Documentation/arm/kernel_user_helpers.rst for details.
1366 However, the fixed address nature of these helpers can be used
1367 by ROP (return orientated programming) authors when creating
1370 If all of the binaries and libraries which run on your platform
1371 are built specifically for your platform, and make no use of
1372 these helpers, then you can turn this option off to hinder
1373 such exploits. However, in that case, if a binary or library
1374 relying on those helpers is run, it will not function correctly.
1376 Say N here only if you are absolutely certain that you do not
1377 need these helpers; otherwise, the safe option is to say Y.
1380 bool "Enable vDSO for 32-bit applications"
1381 depends on !CPU_BIG_ENDIAN
1382 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1383 select GENERIC_COMPAT_VDSO
1386 Place in the process address space of 32-bit applications an
1387 ELF shared object providing fast implementations of gettimeofday
1390 You must have a 32-bit build of glibc 2.22 or later for programs
1391 to seamlessly take advantage of this.
1393 config THUMB2_COMPAT_VDSO
1394 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1395 depends on COMPAT_VDSO
1398 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1399 otherwise with '-marm'.
1401 menuconfig ARMV8_DEPRECATED
1402 bool "Emulate deprecated/obsolete ARMv8 instructions"
1405 Legacy software support may require certain instructions
1406 that have been deprecated or obsoleted in the architecture.
1408 Enable this config to enable selective emulation of these
1415 config SWP_EMULATION
1416 bool "Emulate SWP/SWPB instructions"
1418 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1419 they are always undefined. Say Y here to enable software
1420 emulation of these instructions for userspace using LDXR/STXR.
1421 This feature can be controlled at runtime with the abi.swp
1422 sysctl which is disabled by default.
1424 In some older versions of glibc [<=2.8] SWP is used during futex
1425 trylock() operations with the assumption that the code will not
1426 be preempted. This invalid assumption may be more likely to fail
1427 with SWP emulation enabled, leading to deadlock of the user
1430 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1431 on an external transaction monitoring block called a global
1432 monitor to maintain update atomicity. If your system does not
1433 implement a global monitor, this option can cause programs that
1434 perform SWP operations to uncached memory to deadlock.
1438 config CP15_BARRIER_EMULATION
1439 bool "Emulate CP15 Barrier instructions"
1441 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1442 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1443 strongly recommended to use the ISB, DSB, and DMB
1444 instructions instead.
1446 Say Y here to enable software emulation of these
1447 instructions for AArch32 userspace code. When this option is
1448 enabled, CP15 barrier usage is traced which can help
1449 identify software that needs updating. This feature can be
1450 controlled at runtime with the abi.cp15_barrier sysctl.
1454 config SETEND_EMULATION
1455 bool "Emulate SETEND instruction"
1457 The SETEND instruction alters the data-endianness of the
1458 AArch32 EL0, and is deprecated in ARMv8.
1460 Say Y here to enable software emulation of the instruction
1461 for AArch32 userspace code. This feature can be controlled
1462 at runtime with the abi.setend sysctl.
1464 Note: All the cpus on the system must have mixed endian support at EL0
1465 for this feature to be enabled. If a new CPU - which doesn't support mixed
1466 endian - is hotplugged in after this feature has been enabled, there could
1467 be unexpected results in the applications.
1474 menu "ARMv8.1 architectural features"
1476 config ARM64_HW_AFDBM
1477 bool "Support for hardware updates of the Access and Dirty page flags"
1480 The ARMv8.1 architecture extensions introduce support for
1481 hardware updates of the access and dirty information in page
1482 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1483 capable processors, accesses to pages with PTE_AF cleared will
1484 set this bit instead of raising an access flag fault.
1485 Similarly, writes to read-only pages with the DBM bit set will
1486 clear the read-only bit (AP[2]) instead of raising a
1489 Kernels built with this configuration option enabled continue
1490 to work on pre-ARMv8.1 hardware and the performance impact is
1491 minimal. If unsure, say Y.
1494 bool "Enable support for Privileged Access Never (PAN)"
1497 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1498 prevents the kernel or hypervisor from accessing user-space (EL0)
1501 Choosing this option will cause any unprotected (not using
1502 copy_to_user et al) memory access to fail with a permission fault.
1504 The feature is detected at runtime, and will remain as a 'nop'
1505 instruction if the cpu does not implement the feature.
1508 def_bool $(as-instr,.arch_extension rcpc)
1510 config AS_HAS_LSE_ATOMICS
1511 def_bool $(as-instr,.arch_extension lse)
1513 config ARM64_LSE_ATOMICS
1515 default ARM64_USE_LSE_ATOMICS
1516 depends on AS_HAS_LSE_ATOMICS
1518 config ARM64_USE_LSE_ATOMICS
1519 bool "Atomic instructions"
1520 depends on JUMP_LABEL
1523 As part of the Large System Extensions, ARMv8.1 introduces new
1524 atomic instructions that are designed specifically to scale in
1527 Say Y here to make use of these instructions for the in-kernel
1528 atomic routines. This incurs a small overhead on CPUs that do
1529 not support these instructions and requires the kernel to be
1530 built with binutils >= 2.25 in order for the new instructions
1535 menu "ARMv8.2 architectural features"
1537 config AS_HAS_ARMV8_2
1538 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1541 def_bool $(as-instr,.arch armv8.2-a+sha3)
1544 bool "Enable support for persistent memory"
1545 select ARCH_HAS_PMEM_API
1546 select ARCH_HAS_UACCESS_FLUSHCACHE
1548 Say Y to enable support for the persistent memory API based on the
1549 ARMv8.2 DCPoP feature.
1551 The feature is detected at runtime, and the kernel will use DC CVAC
1552 operations if DC CVAP is not supported (following the behaviour of
1553 DC CVAP itself if the system does not define a point of persistence).
1555 config ARM64_RAS_EXTN
1556 bool "Enable support for RAS CPU Extensions"
1559 CPUs that support the Reliability, Availability and Serviceability
1560 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1561 errors, classify them and report them to software.
1563 On CPUs with these extensions system software can use additional
1564 barriers to determine if faults are pending and read the
1565 classification from a new set of registers.
1567 Selecting this feature will allow the kernel to use these barriers
1568 and access the new registers if the system supports the extension.
1569 Platform RAS features may additionally depend on firmware support.
1572 bool "Enable support for Common Not Private (CNP) translations"
1574 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1576 Common Not Private (CNP) allows translation table entries to
1577 be shared between different PEs in the same inner shareable
1578 domain, so the hardware can use this fact to optimise the
1579 caching of such entries in the TLB.
1581 Selecting this option allows the CNP feature to be detected
1582 at runtime, and does not affect PEs that do not implement
1587 menu "ARMv8.3 architectural features"
1589 config ARM64_PTR_AUTH
1590 bool "Enable support for pointer authentication"
1593 Pointer authentication (part of the ARMv8.3 Extensions) provides
1594 instructions for signing and authenticating pointers against secret
1595 keys, which can be used to mitigate Return Oriented Programming (ROP)
1598 This option enables these instructions at EL0 (i.e. for userspace).
1599 Choosing this option will cause the kernel to initialise secret keys
1600 for each process at exec() time, with these keys being
1601 context-switched along with the process.
1603 The feature is detected at runtime. If the feature is not present in
1604 hardware it will not be advertised to userspace/KVM guest nor will it
1607 If the feature is present on the boot CPU but not on a late CPU, then
1608 the late CPU will be parked. Also, if the boot CPU does not have
1609 address auth and the late CPU has then the late CPU will still boot
1610 but with the feature disabled. On such a system, this option should
1613 config ARM64_PTR_AUTH_KERNEL
1614 bool "Use pointer authentication for kernel"
1616 depends on ARM64_PTR_AUTH
1617 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1618 # Modern compilers insert a .note.gnu.property section note for PAC
1619 # which is only understood by binutils starting with version 2.33.1.
1620 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1621 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1622 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1624 If the compiler supports the -mbranch-protection or
1625 -msign-return-address flag (e.g. GCC 7 or later), then this option
1626 will cause the kernel itself to be compiled with return address
1627 protection. In this case, and if the target hardware is known to
1628 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1629 disabled with minimal loss of protection.
1631 This feature works with FUNCTION_GRAPH_TRACER option only if
1632 DYNAMIC_FTRACE_WITH_REGS is enabled.
1634 config CC_HAS_BRANCH_PROT_PAC_RET
1635 # GCC 9 or later, clang 8 or later
1636 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1638 config CC_HAS_SIGN_RETURN_ADDRESS
1640 def_bool $(cc-option,-msign-return-address=all)
1643 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1645 config AS_HAS_CFI_NEGATE_RA_STATE
1646 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1650 menu "ARMv8.4 architectural features"
1652 config ARM64_AMU_EXTN
1653 bool "Enable support for the Activity Monitors Unit CPU extension"
1656 The activity monitors extension is an optional extension introduced
1657 by the ARMv8.4 CPU architecture. This enables support for version 1
1658 of the activity monitors architecture, AMUv1.
1660 To enable the use of this extension on CPUs that implement it, say Y.
1662 Note that for architectural reasons, firmware _must_ implement AMU
1663 support when running on CPUs that present the activity monitors
1664 extension. The required support is present in:
1665 * Version 1.5 and later of the ARM Trusted Firmware
1667 For kernels that have this configuration enabled but boot with broken
1668 firmware, you may need to say N here until the firmware is fixed.
1669 Otherwise you may experience firmware panics or lockups when
1670 accessing the counter registers. Even if you are not observing these
1671 symptoms, the values returned by the register reads might not
1672 correctly reflect reality. Most commonly, the value read will be 0,
1673 indicating that the counter is not enabled.
1675 config AS_HAS_ARMV8_4
1676 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1678 config ARM64_TLB_RANGE
1679 bool "Enable support for tlbi range feature"
1681 depends on AS_HAS_ARMV8_4
1683 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1684 range of input addresses.
1686 The feature introduces new assembly instructions, and they were
1687 support when binutils >= 2.30.
1691 menu "ARMv8.5 architectural features"
1693 config AS_HAS_ARMV8_5
1694 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1697 bool "Branch Target Identification support"
1700 Branch Target Identification (part of the ARMv8.5 Extensions)
1701 provides a mechanism to limit the set of locations to which computed
1702 branch instructions such as BR or BLR can jump.
1704 To make use of BTI on CPUs that support it, say Y.
1706 BTI is intended to provide complementary protection to other control
1707 flow integrity protection mechanisms, such as the Pointer
1708 authentication mechanism provided as part of the ARMv8.3 Extensions.
1709 For this reason, it does not make sense to enable this option without
1710 also enabling support for pointer authentication. Thus, when
1711 enabling this option you should also select ARM64_PTR_AUTH=y.
1713 Userspace binaries must also be specifically compiled to make use of
1714 this mechanism. If you say N here or the hardware does not support
1715 BTI, such binaries can still run, but you get no additional
1716 enforcement of branch destinations.
1718 config ARM64_BTI_KERNEL
1719 bool "Use Branch Target Identification for kernel"
1721 depends on ARM64_BTI
1722 depends on ARM64_PTR_AUTH_KERNEL
1723 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1724 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1725 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1726 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1727 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
1728 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1730 Build the kernel with Branch Target Identification annotations
1731 and enable enforcement of this for kernel code. When this option
1732 is enabled and the system supports BTI all kernel code including
1733 modular code must have BTI enabled.
1735 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1736 # GCC 9 or later, clang 8 or later
1737 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1740 bool "Enable support for E0PD"
1743 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1744 that EL0 accesses made via TTBR1 always fault in constant time,
1745 providing similar benefits to KASLR as those provided by KPTI, but
1746 with lower overhead and without disrupting legitimate access to
1747 kernel memory such as SPE.
1749 This option enables E0PD for TTBR1 where available.
1752 bool "Enable support for random number generation"
1755 Random number generation (part of the ARMv8.5 Extensions)
1756 provides a high bandwidth, cryptographically secure
1757 hardware random number generator.
1759 config ARM64_AS_HAS_MTE
1760 # Initial support for MTE went in binutils 2.32.0, checked with
1761 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1762 # as a late addition to the final architecture spec (LDGM/STGM)
1763 # is only supported in the newer 2.32.x and 2.33 binutils
1764 # versions, hence the extra "stgm" instruction check below.
1765 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1768 bool "Memory Tagging Extension support"
1770 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1771 depends on AS_HAS_ARMV8_5
1772 depends on AS_HAS_LSE_ATOMICS
1773 # Required for tag checking in the uaccess routines
1774 depends on ARM64_PAN
1775 select ARCH_USES_HIGH_VMA_FLAGS
1777 Memory Tagging (part of the ARMv8.5 Extensions) provides
1778 architectural support for run-time, always-on detection of
1779 various classes of memory error to aid with software debugging
1780 to eliminate vulnerabilities arising from memory-unsafe
1783 This option enables the support for the Memory Tagging
1784 Extension at EL0 (i.e. for userspace).
1786 Selecting this option allows the feature to be detected at
1787 runtime. Any secondary CPU not implementing this feature will
1788 not be allowed a late bring-up.
1790 Userspace binaries that want to use this feature must
1791 explicitly opt in. The mechanism for the userspace is
1794 Documentation/arm64/memory-tagging-extension.rst.
1798 menu "ARMv8.7 architectural features"
1801 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
1803 depends on ARM64_PAN
1805 Enhanced Privileged Access Never (EPAN) allows Privileged
1806 Access Never to be used with Execute-only mappings.
1808 The feature is detected at runtime, and will remain disabled
1809 if the cpu does not implement the feature.
1813 bool "ARM Scalable Vector Extension support"
1816 The Scalable Vector Extension (SVE) is an extension to the AArch64
1817 execution state which complements and extends the SIMD functionality
1818 of the base architecture to support much larger vectors and to enable
1819 additional vectorisation opportunities.
1821 To enable use of this extension on CPUs that implement it, say Y.
1823 On CPUs that support the SVE2 extensions, this option will enable
1826 Note that for architectural reasons, firmware _must_ implement SVE
1827 support when running on SVE capable hardware. The required support
1830 * version 1.5 and later of the ARM Trusted Firmware
1831 * the AArch64 boot wrapper since commit 5e1261e08abf
1832 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1834 For other firmware implementations, consult the firmware documentation
1837 If you need the kernel to boot on SVE-capable hardware with broken
1838 firmware, you may need to say N here until you get your firmware
1839 fixed. Otherwise, you may experience firmware panics or lockups when
1840 booting the kernel. If unsure and you are not observing these
1841 symptoms, you should assume that it is safe to say Y.
1843 config ARM64_MODULE_PLTS
1844 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1846 select HAVE_MOD_ARCH_SPECIFIC
1848 Allocate PLTs when loading modules so that jumps and calls whose
1849 targets are too far away for their relative offsets to be encoded
1850 in the instructions themselves can be bounced via veneers in the
1851 module's PLT. This allows modules to be allocated in the generic
1852 vmalloc area after the dedicated module memory area has been
1855 When running with address space randomization (KASLR), the module
1856 region itself may be too far away for ordinary relative jumps and
1857 calls, and so in that case, module PLTs are required and cannot be
1860 Specific errata workaround(s) might also force module PLTs to be
1861 enabled (ARM64_ERRATUM_843419).
1863 config ARM64_PSEUDO_NMI
1864 bool "Support for NMI-like interrupts"
1867 Adds support for mimicking Non-Maskable Interrupts through the use of
1868 GIC interrupt priority. This support requires version 3 or later of
1871 This high priority configuration for interrupts needs to be
1872 explicitly enabled by setting the kernel parameter
1873 "irqchip.gicv3_pseudo_nmi" to 1.
1878 config ARM64_DEBUG_PRIORITY_MASKING
1879 bool "Debug interrupt priority masking"
1881 This adds runtime checks to functions enabling/disabling
1882 interrupts when using priority masking. The additional checks verify
1883 the validity of ICC_PMR_EL1 when calling concerned functions.
1889 bool "Build a relocatable kernel image" if EXPERT
1890 select ARCH_HAS_RELR
1893 This builds the kernel as a Position Independent Executable (PIE),
1894 which retains all relocation metadata required to relocate the
1895 kernel binary at runtime to a different virtual address than the
1896 address it was linked at.
1897 Since AArch64 uses the RELA relocation format, this requires a
1898 relocation pass at runtime even if the kernel is loaded at the
1899 same address it was linked at.
1901 config RANDOMIZE_BASE
1902 bool "Randomize the address of the kernel image"
1903 select ARM64_MODULE_PLTS if MODULES
1906 Randomizes the virtual address at which the kernel image is
1907 loaded, as a security feature that deters exploit attempts
1908 relying on knowledge of the location of kernel internals.
1910 It is the bootloader's job to provide entropy, by passing a
1911 random u64 value in /chosen/kaslr-seed at kernel entry.
1913 When booting via the UEFI stub, it will invoke the firmware's
1914 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1915 to the kernel proper. In addition, it will randomise the physical
1916 location of the kernel Image as well.
1920 config RANDOMIZE_MODULE_REGION_FULL
1921 bool "Randomize the module region over a 2 GB range"
1922 depends on RANDOMIZE_BASE
1925 Randomizes the location of the module region inside a 2 GB window
1926 covering the core kernel. This way, it is less likely for modules
1927 to leak information about the location of core kernel data structures
1928 but it does imply that function calls between modules and the core
1929 kernel will need to be resolved via veneers in the module PLT.
1931 When this option is not set, the module region will be randomized over
1932 a limited range that contains the [_stext, _etext] interval of the
1933 core kernel, so branch relocations are almost always in range unless
1934 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this
1935 particular case of region exhaustion, modules might be able to fall
1936 back to a larger 2GB area.
1938 config CC_HAVE_STACKPROTECTOR_SYSREG
1939 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1941 config STACKPROTECTOR_PER_TASK
1943 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1949 config ARM64_ACPI_PARKING_PROTOCOL
1950 bool "Enable support for the ARM64 ACPI parking protocol"
1953 Enable support for the ARM64 ACPI parking protocol. If disabled
1954 the kernel will not allow booting through the ARM64 ACPI parking
1955 protocol even if the corresponding data is present in the ACPI
1959 string "Default kernel command string"
1962 Provide a set of default command-line options at build time by
1963 entering them here. As a minimum, you should specify the the
1964 root device (e.g. root=/dev/nfs).
1967 prompt "Kernel command line type" if CMDLINE != ""
1968 default CMDLINE_FROM_BOOTLOADER
1970 Choose how the kernel will handle the provided default kernel
1971 command line string.
1973 config CMDLINE_FROM_BOOTLOADER
1974 bool "Use bootloader kernel arguments if available"
1976 Uses the command-line options passed by the boot loader. If
1977 the boot loader doesn't provide any, the default kernel command
1978 string provided in CMDLINE will be used.
1980 config CMDLINE_FORCE
1981 bool "Always use the default kernel command string"
1983 Always use the default kernel command string, even if the boot
1984 loader passes other arguments to the kernel.
1985 This is useful if you cannot or don't want to change the
1986 command-line options your boot loader passes to the kernel.
1994 bool "UEFI runtime support"
1995 depends on OF && !CPU_BIG_ENDIAN
1996 depends on KERNEL_MODE_NEON
1997 select ARCH_SUPPORTS_ACPI
2000 select EFI_PARAMS_FROM_FDT
2001 select EFI_RUNTIME_WRAPPERS
2003 select EFI_GENERIC_STUB
2004 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
2007 This option provides support for runtime services provided
2008 by UEFI firmware (such as non-volatile variables, realtime
2009 clock, and platform reset). A UEFI stub is also provided to
2010 allow the kernel to be booted as an EFI application. This
2011 is only useful on systems that have UEFI firmware.
2014 bool "Enable support for SMBIOS (DMI) tables"
2018 This enables SMBIOS/DMI feature for systems.
2020 This option is only useful on systems that have UEFI firmware.
2021 However, even with this option, the resultant kernel should
2022 continue to boot on existing non-UEFI platforms.
2026 config SYSVIPC_COMPAT
2028 depends on COMPAT && SYSVIPC
2030 menu "Power management options"
2032 source "kernel/power/Kconfig"
2034 config ARCH_HIBERNATION_POSSIBLE
2038 config ARCH_HIBERNATION_HEADER
2040 depends on HIBERNATION
2042 config ARCH_SUSPEND_POSSIBLE
2047 menu "CPU Power Management"
2049 source "drivers/cpuidle/Kconfig"
2051 source "drivers/cpufreq/Kconfig"
2055 source "drivers/acpi/Kconfig"
2057 source "arch/arm64/kvm/Kconfig"
2060 source "arch/arm64/crypto/Kconfig"