1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_WX
13 select ARCH_BINFMT_ELF_STATE
14 select ARCH_HAS_DEBUG_VIRTUAL
15 select ARCH_HAS_DEBUG_VM_PGTABLE
16 select ARCH_HAS_DEVMEM_IS_ALLOWED
17 select ARCH_HAS_DMA_PREP_COHERENT
18 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
19 select ARCH_HAS_FAST_MULTIPLIER
20 select ARCH_HAS_FORTIFY_SOURCE
21 select ARCH_HAS_GCOV_PROFILE_ALL
22 select ARCH_HAS_GIGANTIC_PAGE
24 select ARCH_HAS_KEEPINITRD
25 select ARCH_HAS_MEMBARRIER_SYNC_CORE
26 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
27 select ARCH_HAS_PTE_DEVMAP
28 select ARCH_HAS_PTE_SPECIAL
29 select ARCH_HAS_SETUP_DMA_OPS
30 select ARCH_HAS_SET_DIRECT_MAP
31 select ARCH_HAS_SET_MEMORY
32 select ARCH_HAS_STRICT_KERNEL_RWX
33 select ARCH_HAS_STRICT_MODULE_RWX
34 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
35 select ARCH_HAS_SYNC_DMA_FOR_CPU
36 select ARCH_HAS_SYSCALL_WRAPPER
37 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
38 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
39 select ARCH_HAVE_ELF_PROT
40 select ARCH_HAVE_NMI_SAFE_CMPXCHG
41 select ARCH_INLINE_READ_LOCK if !PREEMPTION
42 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
43 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
44 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
45 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
46 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
47 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
48 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
49 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
50 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
51 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
52 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
53 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
54 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
55 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
56 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
57 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
58 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
59 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
60 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
61 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
62 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
63 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
64 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
65 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
66 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
67 select ARCH_KEEP_MEMBLOCK
68 select ARCH_USE_CMPXCHG_LOCKREF
69 select ARCH_USE_GNU_PROPERTY
70 select ARCH_USE_QUEUED_RWLOCKS
71 select ARCH_USE_QUEUED_SPINLOCKS
72 select ARCH_USE_SYM_ANNOTATIONS
73 select ARCH_SUPPORTS_MEMORY_FAILURE
74 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
75 select ARCH_SUPPORTS_ATOMIC_RMW
76 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG)
77 select ARCH_SUPPORTS_NUMA_BALANCING
78 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
79 select ARCH_WANT_DEFAULT_BPF_JIT
80 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
81 select ARCH_WANT_FRAME_POINTERS
82 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
83 select ARCH_HAS_UBSAN_SANITIZE_ALL
87 select AUDIT_ARCH_COMPAT_GENERIC
88 select ARM_GIC_V2M if PCI
90 select ARM_GIC_V3_ITS if PCI
92 select BUILDTIME_TABLE_SORT
93 select CLONE_BACKWARDS
95 select CPU_PM if (SUSPEND || CPU_IDLE)
97 select DCACHE_WORD_ACCESS
98 select DMA_DIRECT_REMAP
101 select GENERIC_ALLOCATOR
102 select GENERIC_ARCH_TOPOLOGY
103 select GENERIC_CLOCKEVENTS
104 select GENERIC_CLOCKEVENTS_BROADCAST
105 select GENERIC_CPU_AUTOPROBE
106 select GENERIC_CPU_VULNERABILITIES
107 select GENERIC_EARLY_IOREMAP
108 select GENERIC_IDLE_POLL_SETUP
109 select GENERIC_IRQ_MULTI_HANDLER
110 select GENERIC_IRQ_PROBE
111 select GENERIC_IRQ_SHOW
112 select GENERIC_IRQ_SHOW_LEVEL
113 select GENERIC_PCI_IOMAP
114 select GENERIC_PTDUMP
115 select GENERIC_SCHED_CLOCK
116 select GENERIC_SMP_IDLE_THREAD
117 select GENERIC_STRNCPY_FROM_USER
118 select GENERIC_STRNLEN_USER
119 select GENERIC_TIME_VSYSCALL
120 select GENERIC_GETTIMEOFDAY
121 select HANDLE_DOMAIN_IRQ
122 select HARDIRQS_SW_RESEND
124 select HAVE_ACPI_APEI if (ACPI && EFI)
125 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
126 select HAVE_ARCH_AUDITSYSCALL
127 select HAVE_ARCH_BITREVERSE
128 select HAVE_ARCH_COMPILER_H
129 select HAVE_ARCH_HUGE_VMAP
130 select HAVE_ARCH_JUMP_LABEL
131 select HAVE_ARCH_JUMP_LABEL_RELATIVE
132 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
133 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
134 select HAVE_ARCH_KGDB
135 select HAVE_ARCH_MMAP_RND_BITS
136 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
137 select HAVE_ARCH_PREL32_RELOCATIONS
138 select HAVE_ARCH_SECCOMP_FILTER
139 select HAVE_ARCH_STACKLEAK
140 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
141 select HAVE_ARCH_TRACEHOOK
142 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
143 select HAVE_ARCH_VMAP_STACK
144 select HAVE_ARM_SMCCC
145 select HAVE_ASM_MODVERSIONS
147 select HAVE_C_RECORDMCOUNT
148 select HAVE_CMPXCHG_DOUBLE
149 select HAVE_CMPXCHG_LOCAL
150 select HAVE_CONTEXT_TRACKING
151 select HAVE_COPY_THREAD_TLS
152 select HAVE_DEBUG_BUGVERBOSE
153 select HAVE_DEBUG_KMEMLEAK
154 select HAVE_DMA_CONTIGUOUS
155 select HAVE_DYNAMIC_FTRACE
156 select HAVE_DYNAMIC_FTRACE_WITH_REGS \
157 if $(cc-option,-fpatchable-function-entry=2)
158 select HAVE_EFFICIENT_UNALIGNED_ACCESS
160 select HAVE_FTRACE_MCOUNT_RECORD
161 select HAVE_FUNCTION_TRACER
162 select HAVE_FUNCTION_ERROR_INJECTION
163 select HAVE_FUNCTION_GRAPH_TRACER
164 select HAVE_GCC_PLUGINS
165 select HAVE_HW_BREAKPOINT if PERF_EVENTS
166 select HAVE_IRQ_TIME_ACCOUNTING
168 select HAVE_PATA_PLATFORM
169 select HAVE_PERF_EVENTS
170 select HAVE_PERF_REGS
171 select HAVE_PERF_USER_STACK_DUMP
172 select HAVE_REGS_AND_STACK_ACCESS_API
173 select HAVE_FUNCTION_ARG_ACCESS_API
174 select HAVE_FUTEX_CMPXCHG if FUTEX
175 select MMU_GATHER_RCU_TABLE_FREE
177 select HAVE_STACKPROTECTOR
178 select HAVE_SYSCALL_TRACEPOINTS
180 select HAVE_KRETPROBES
181 select HAVE_GENERIC_VDSO
182 select IOMMU_DMA if IOMMU_SUPPORT
184 select IRQ_FORCED_THREADING
185 select MODULES_USE_ELF_RELA
186 select NEED_DMA_MAP_STATE
187 select NEED_SG_DMA_LENGTH
189 select OF_EARLY_FLATTREE
190 select PCI_DOMAINS_GENERIC if PCI
191 select PCI_ECAM if (ACPI && PCI)
192 select PCI_SYSCALL if PCI
197 select SYSCTL_EXCEPTION_TRACE
198 select THREAD_INFO_IN_TASK
200 ARM 64-bit (AArch64) Linux support.
208 config ARM64_PAGE_SHIFT
210 default 16 if ARM64_64K_PAGES
211 default 14 if ARM64_16K_PAGES
214 config ARM64_CONT_SHIFT
216 default 5 if ARM64_64K_PAGES
217 default 7 if ARM64_16K_PAGES
220 config ARCH_MMAP_RND_BITS_MIN
221 default 14 if ARM64_64K_PAGES
222 default 16 if ARM64_16K_PAGES
225 # max bits determined by the following formula:
226 # VA_BITS - PAGE_SHIFT - 3
227 config ARCH_MMAP_RND_BITS_MAX
228 default 19 if ARM64_VA_BITS=36
229 default 24 if ARM64_VA_BITS=39
230 default 27 if ARM64_VA_BITS=42
231 default 30 if ARM64_VA_BITS=47
232 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
233 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
234 default 33 if ARM64_VA_BITS=48
235 default 14 if ARM64_64K_PAGES
236 default 16 if ARM64_16K_PAGES
239 config ARCH_MMAP_RND_COMPAT_BITS_MIN
240 default 7 if ARM64_64K_PAGES
241 default 9 if ARM64_16K_PAGES
244 config ARCH_MMAP_RND_COMPAT_BITS_MAX
250 config STACKTRACE_SUPPORT
253 config ILLEGAL_POINTER_VALUE
255 default 0xdead000000000000
257 config LOCKDEP_SUPPORT
260 config TRACE_IRQFLAGS_SUPPORT
267 config GENERIC_BUG_RELATIVE_POINTERS
269 depends on GENERIC_BUG
271 config GENERIC_HWEIGHT
277 config GENERIC_CALIBRATE_DELAY
281 bool "Support DMA zone" if EXPERT
285 bool "Support DMA32 zone" if EXPERT
288 config ARCH_ENABLE_MEMORY_HOTPLUG
291 config ARCH_ENABLE_MEMORY_HOTREMOVE
297 config KERNEL_MODE_NEON
300 config FIX_EARLYCON_MEM
303 config PGTABLE_LEVELS
305 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
306 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
307 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
308 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
309 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
310 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
312 config ARCH_SUPPORTS_UPROBES
315 config ARCH_PROC_KCORE_TEXT
318 config BROKEN_GAS_INST
319 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
321 config KASAN_SHADOW_OFFSET
324 default 0xdfffa00000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
325 default 0xdfffd00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
326 default 0xdffffe8000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
327 default 0xdfffffd000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
328 default 0xdffffffa00000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
329 default 0xefff900000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
330 default 0xefffc80000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
331 default 0xeffffe4000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
332 default 0xefffffc800000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
333 default 0xeffffff900000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
334 default 0xffffffffffffffff
336 source "arch/arm64/Kconfig.platforms"
338 menu "Kernel Features"
340 menu "ARM errata workarounds via the alternatives framework"
342 config ARM64_WORKAROUND_CLEAN_CACHE
345 config ARM64_ERRATUM_826319
346 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
348 select ARM64_WORKAROUND_CLEAN_CACHE
350 This option adds an alternative code sequence to work around ARM
351 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
352 AXI master interface and an L2 cache.
354 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
355 and is unable to accept a certain write via this interface, it will
356 not progress on read data presented on the read data channel and the
359 The workaround promotes data cache clean instructions to
360 data cache clean-and-invalidate.
361 Please note that this does not necessarily enable the workaround,
362 as it depends on the alternative framework, which will only patch
363 the kernel if an affected CPU is detected.
367 config ARM64_ERRATUM_827319
368 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
370 select ARM64_WORKAROUND_CLEAN_CACHE
372 This option adds an alternative code sequence to work around ARM
373 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
374 master interface and an L2 cache.
376 Under certain conditions this erratum can cause a clean line eviction
377 to occur at the same time as another transaction to the same address
378 on the AMBA 5 CHI interface, which can cause data corruption if the
379 interconnect reorders the two transactions.
381 The workaround promotes data cache clean instructions to
382 data cache clean-and-invalidate.
383 Please note that this does not necessarily enable the workaround,
384 as it depends on the alternative framework, which will only patch
385 the kernel if an affected CPU is detected.
389 config ARM64_ERRATUM_824069
390 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
392 select ARM64_WORKAROUND_CLEAN_CACHE
394 This option adds an alternative code sequence to work around ARM
395 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
396 to a coherent interconnect.
398 If a Cortex-A53 processor is executing a store or prefetch for
399 write instruction at the same time as a processor in another
400 cluster is executing a cache maintenance operation to the same
401 address, then this erratum might cause a clean cache line to be
402 incorrectly marked as dirty.
404 The workaround promotes data cache clean instructions to
405 data cache clean-and-invalidate.
406 Please note that this option does not necessarily enable the
407 workaround, as it depends on the alternative framework, which will
408 only patch the kernel if an affected CPU is detected.
412 config ARM64_ERRATUM_819472
413 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
415 select ARM64_WORKAROUND_CLEAN_CACHE
417 This option adds an alternative code sequence to work around ARM
418 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
419 present when it is connected to a coherent interconnect.
421 If the processor is executing a load and store exclusive sequence at
422 the same time as a processor in another cluster is executing a cache
423 maintenance operation to the same address, then this erratum might
424 cause data corruption.
426 The workaround promotes data cache clean instructions to
427 data cache clean-and-invalidate.
428 Please note that this does not necessarily enable the workaround,
429 as it depends on the alternative framework, which will only patch
430 the kernel if an affected CPU is detected.
434 config ARM64_ERRATUM_832075
435 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
438 This option adds an alternative code sequence to work around ARM
439 erratum 832075 on Cortex-A57 parts up to r1p2.
441 Affected Cortex-A57 parts might deadlock when exclusive load/store
442 instructions to Write-Back memory are mixed with Device loads.
444 The workaround is to promote device loads to use Load-Acquire
446 Please note that this does not necessarily enable the workaround,
447 as it depends on the alternative framework, which will only patch
448 the kernel if an affected CPU is detected.
452 config ARM64_ERRATUM_834220
453 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
457 This option adds an alternative code sequence to work around ARM
458 erratum 834220 on Cortex-A57 parts up to r1p2.
460 Affected Cortex-A57 parts might report a Stage 2 translation
461 fault as the result of a Stage 1 fault for load crossing a
462 page boundary when there is a permission or device memory
463 alignment fault at Stage 1 and a translation fault at Stage 2.
465 The workaround is to verify that the Stage 1 translation
466 doesn't generate a fault before handling the Stage 2 fault.
467 Please note that this does not necessarily enable the workaround,
468 as it depends on the alternative framework, which will only patch
469 the kernel if an affected CPU is detected.
473 config ARM64_ERRATUM_845719
474 bool "Cortex-A53: 845719: a load might read incorrect data"
478 This option adds an alternative code sequence to work around ARM
479 erratum 845719 on Cortex-A53 parts up to r0p4.
481 When running a compat (AArch32) userspace on an affected Cortex-A53
482 part, a load at EL0 from a virtual address that matches the bottom 32
483 bits of the virtual address used by a recent load at (AArch64) EL1
484 might return incorrect data.
486 The workaround is to write the contextidr_el1 register on exception
487 return to a 32-bit task.
488 Please note that this does not necessarily enable the workaround,
489 as it depends on the alternative framework, which will only patch
490 the kernel if an affected CPU is detected.
494 config ARM64_ERRATUM_843419
495 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
497 select ARM64_MODULE_PLTS if MODULES
499 This option links the kernel with '--fix-cortex-a53-843419' and
500 enables PLT support to replace certain ADRP instructions, which can
501 cause subsequent memory accesses to use an incorrect address on
502 Cortex-A53 parts up to r0p4.
506 config ARM64_ERRATUM_1024718
507 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
510 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
512 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
513 update of the hardware dirty bit when the DBM/AP bits are updated
514 without a break-before-make. The workaround is to disable the usage
515 of hardware DBM locally on the affected cores. CPUs not affected by
516 this erratum will continue to use the feature.
520 config ARM64_ERRATUM_1418040
521 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
525 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
526 errata 1188873 and 1418040.
528 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
529 cause register corruption when accessing the timer registers
530 from AArch32 userspace.
534 config ARM64_WORKAROUND_SPECULATIVE_AT
537 config ARM64_ERRATUM_1165522
538 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
540 select ARM64_WORKAROUND_SPECULATIVE_AT
542 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
544 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
545 corrupted TLBs by speculating an AT instruction during a guest
550 config ARM64_ERRATUM_1319367
551 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
553 select ARM64_WORKAROUND_SPECULATIVE_AT
555 This option adds work arounds for ARM Cortex-A57 erratum 1319537
556 and A72 erratum 1319367
558 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
559 speculating an AT instruction during a guest context switch.
563 config ARM64_ERRATUM_1530923
564 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
566 select ARM64_WORKAROUND_SPECULATIVE_AT
568 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
570 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
571 corrupted TLBs by speculating an AT instruction during a guest
576 config ARM64_WORKAROUND_REPEAT_TLBI
579 config ARM64_ERRATUM_1286807
580 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
582 select ARM64_WORKAROUND_REPEAT_TLBI
584 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
586 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
587 address for a cacheable mapping of a location is being
588 accessed by a core while another core is remapping the virtual
589 address to a new physical page using the recommended
590 break-before-make sequence, then under very rare circumstances
591 TLBI+DSB completes before a read using the translation being
592 invalidated has been observed by other observers. The
593 workaround repeats the TLBI+DSB operation.
595 config ARM64_ERRATUM_1463225
596 bool "Cortex-A76: Software Step might prevent interrupt recognition"
599 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
601 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
602 of a system call instruction (SVC) can prevent recognition of
603 subsequent interrupts when software stepping is disabled in the
604 exception handler of the system call and either kernel debugging
605 is enabled or VHE is in use.
607 Work around the erratum by triggering a dummy step exception
608 when handling a system call from a task that is being stepped
609 in a VHE configuration of the kernel.
613 config ARM64_ERRATUM_1542419
614 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
617 This option adds a workaround for ARM Neoverse-N1 erratum
620 Affected Neoverse-N1 cores could execute a stale instruction when
621 modified by another CPU. The workaround depends on a firmware
624 Workaround the issue by hiding the DIC feature from EL0. This
625 forces user-space to perform cache maintenance.
629 config CAVIUM_ERRATUM_22375
630 bool "Cavium erratum 22375, 24313"
633 Enable workaround for errata 22375 and 24313.
635 This implements two gicv3-its errata workarounds for ThunderX. Both
636 with a small impact affecting only ITS table allocation.
638 erratum 22375: only alloc 8MB table size
639 erratum 24313: ignore memory access type
641 The fixes are in ITS initialization and basically ignore memory access
642 type and table size provided by the TYPER and BASER registers.
646 config CAVIUM_ERRATUM_23144
647 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
651 ITS SYNC command hang for cross node io and collections/cpu mapping.
655 config CAVIUM_ERRATUM_23154
656 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
659 The gicv3 of ThunderX requires a modified version for
660 reading the IAR status to ensure data synchronization
661 (access to icc_iar1_el1 is not sync'ed before and after).
665 config CAVIUM_ERRATUM_27456
666 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
669 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
670 instructions may cause the icache to become corrupted if it
671 contains data for a non-current ASID. The fix is to
672 invalidate the icache when changing the mm context.
676 config CAVIUM_ERRATUM_30115
677 bool "Cavium erratum 30115: Guest may disable interrupts in host"
680 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
681 1.2, and T83 Pass 1.0, KVM guest execution may disable
682 interrupts in host. Trapping both GICv3 group-0 and group-1
683 accesses sidesteps the issue.
687 config CAVIUM_TX2_ERRATUM_219
688 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
691 On Cavium ThunderX2, a load, store or prefetch instruction between a
692 TTBR update and the corresponding context synchronizing operation can
693 cause a spurious Data Abort to be delivered to any hardware thread in
696 Work around the issue by avoiding the problematic code sequence and
697 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
698 trap handler performs the corresponding register access, skips the
699 instruction and ensures context synchronization by virtue of the
704 config FUJITSU_ERRATUM_010001
705 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
708 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
709 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
710 accesses may cause undefined fault (Data abort, DFSC=0b111111).
711 This fault occurs under a specific hardware condition when a
712 load/store instruction performs an address translation using:
713 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
714 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
715 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
716 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
718 The workaround is to ensure these bits are clear in TCR_ELx.
719 The workaround only affects the Fujitsu-A64FX.
723 config HISILICON_ERRATUM_161600802
724 bool "Hip07 161600802: Erroneous redistributor VLPI base"
727 The HiSilicon Hip07 SoC uses the wrong redistributor base
728 when issued ITS commands such as VMOVP and VMAPP, and requires
729 a 128kB offset to be applied to the target address in this commands.
733 config QCOM_FALKOR_ERRATUM_1003
734 bool "Falkor E1003: Incorrect translation due to ASID change"
737 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
738 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
739 in TTBR1_EL1, this situation only occurs in the entry trampoline and
740 then only for entries in the walk cache, since the leaf translation
741 is unchanged. Work around the erratum by invalidating the walk cache
742 entries for the trampoline before entering the kernel proper.
744 config QCOM_FALKOR_ERRATUM_1009
745 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
747 select ARM64_WORKAROUND_REPEAT_TLBI
749 On Falkor v1, the CPU may prematurely complete a DSB following a
750 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
751 one more time to fix the issue.
755 config QCOM_QDF2400_ERRATUM_0065
756 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
759 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
760 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
761 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
765 config QCOM_FALKOR_ERRATUM_E1041
766 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
769 Falkor CPU may speculatively fetch instructions from an improper
770 memory location when MMU translation is changed from SCTLR_ELn[M]=1
771 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
775 config SOCIONEXT_SYNQUACER_PREITS
776 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
779 Socionext Synquacer SoCs implement a separate h/w block to generate
780 MSI doorbell writes with non-zero values for the device ID.
789 default ARM64_4K_PAGES
791 Page size (translation granule) configuration.
793 config ARM64_4K_PAGES
796 This feature enables 4KB pages support.
798 config ARM64_16K_PAGES
801 The system will use 16KB pages support. AArch32 emulation
802 requires applications compiled with 16K (or a multiple of 16K)
805 config ARM64_64K_PAGES
808 This feature enables 64KB pages support (4KB by default)
809 allowing only two levels of page tables and faster TLB
810 look-up. AArch32 emulation requires applications compiled
811 with 64K aligned segments.
816 prompt "Virtual address space size"
817 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
818 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
819 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
821 Allows choosing one of multiple possible virtual address
822 space sizes. The level of translation table is determined by
823 a combination of page size and virtual address space size.
825 config ARM64_VA_BITS_36
826 bool "36-bit" if EXPERT
827 depends on ARM64_16K_PAGES
829 config ARM64_VA_BITS_39
831 depends on ARM64_4K_PAGES
833 config ARM64_VA_BITS_42
835 depends on ARM64_64K_PAGES
837 config ARM64_VA_BITS_47
839 depends on ARM64_16K_PAGES
841 config ARM64_VA_BITS_48
844 config ARM64_VA_BITS_52
846 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
848 Enable 52-bit virtual addressing for userspace when explicitly
849 requested via a hint to mmap(). The kernel will also use 52-bit
850 virtual addresses for its own mappings (provided HW support for
851 this feature is available, otherwise it reverts to 48-bit).
853 NOTE: Enabling 52-bit virtual addressing in conjunction with
854 ARMv8.3 Pointer Authentication will result in the PAC being
855 reduced from 7 bits to 3 bits, which may have a significant
856 impact on its susceptibility to brute-force attacks.
858 If unsure, select 48-bit virtual addressing instead.
862 config ARM64_FORCE_52BIT
863 bool "Force 52-bit virtual addresses for userspace"
864 depends on ARM64_VA_BITS_52 && EXPERT
866 For systems with 52-bit userspace VAs enabled, the kernel will attempt
867 to maintain compatibility with older software by providing 48-bit VAs
868 unless a hint is supplied to mmap.
870 This configuration option disables the 48-bit compatibility logic, and
871 forces all userspace addresses to be 52-bit on HW that supports it. One
872 should only enable this configuration option for stress testing userspace
873 memory management code. If unsure say N here.
877 default 36 if ARM64_VA_BITS_36
878 default 39 if ARM64_VA_BITS_39
879 default 42 if ARM64_VA_BITS_42
880 default 47 if ARM64_VA_BITS_47
881 default 48 if ARM64_VA_BITS_48
882 default 52 if ARM64_VA_BITS_52
885 prompt "Physical address space size"
886 default ARM64_PA_BITS_48
888 Choose the maximum physical address range that the kernel will
891 config ARM64_PA_BITS_48
894 config ARM64_PA_BITS_52
895 bool "52-bit (ARMv8.2)"
896 depends on ARM64_64K_PAGES
897 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
899 Enable support for a 52-bit physical address space, introduced as
900 part of the ARMv8.2-LPA extension.
902 With this enabled, the kernel will also continue to work on CPUs that
903 do not support ARMv8.2-LPA, but with some added memory overhead (and
904 minor performance overhead).
910 default 48 if ARM64_PA_BITS_48
911 default 52 if ARM64_PA_BITS_52
915 default CPU_LITTLE_ENDIAN
917 Select the endianness of data accesses performed by the CPU. Userspace
918 applications will need to be compiled and linked for the endianness
919 that is selected here.
921 config CPU_BIG_ENDIAN
922 bool "Build big-endian kernel"
924 Say Y if you plan on running a kernel with a big-endian userspace.
926 config CPU_LITTLE_ENDIAN
927 bool "Build little-endian kernel"
929 Say Y if you plan on running a kernel with a little-endian userspace.
930 This is usually the case for distributions targeting arm64.
935 bool "Multi-core scheduler support"
937 Multi-core scheduler support improves the CPU scheduler's decision
938 making when dealing with multi-core CPU chips at a cost of slightly
939 increased overhead in some places. If unsure say N here.
942 bool "SMT scheduler support"
944 Improves the CPU scheduler's decision making when dealing with
945 MultiThreading at a cost of slightly increased overhead in some
946 places. If unsure say N here.
949 int "Maximum number of CPUs (2-4096)"
954 bool "Support for hot-pluggable CPUs"
955 select GENERIC_IRQ_MIGRATION
957 Say Y here to experiment with turning CPUs off and on. CPUs
958 can be controlled through /sys/devices/system/cpu.
960 # Common NUMA Features
962 bool "NUMA Memory Allocation and Scheduler Support"
963 select ACPI_NUMA if ACPI
966 Enable NUMA (Non-Uniform Memory Access) support.
968 The kernel will try to allocate memory used by a CPU on the
969 local memory of the CPU and add some more
970 NUMA awareness to the kernel.
973 int "Maximum NUMA Nodes (as a power of 2)"
976 depends on NEED_MULTIPLE_NODES
978 Specify the maximum number of NUMA Nodes available on the target
979 system. Increases memory reserved to accommodate various tables.
981 config USE_PERCPU_NUMA_NODE_ID
985 config HAVE_SETUP_PER_CPU_AREA
989 config NEED_PER_CPU_EMBED_FIRST_CHUNK
996 source "kernel/Kconfig.hz"
998 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
1001 config ARCH_SPARSEMEM_ENABLE
1003 select SPARSEMEM_VMEMMAP_ENABLE
1005 config ARCH_SPARSEMEM_DEFAULT
1006 def_bool ARCH_SPARSEMEM_ENABLE
1008 config ARCH_SELECT_MEMORY_MODEL
1009 def_bool ARCH_SPARSEMEM_ENABLE
1011 config ARCH_FLATMEM_ENABLE
1014 config HAVE_ARCH_PFN_VALID
1017 config HW_PERF_EVENTS
1021 config SYS_SUPPORTS_HUGETLBFS
1024 config ARCH_WANT_HUGE_PMD_SHARE
1026 config ARCH_HAS_CACHE_LINE_SIZE
1029 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
1030 def_bool y if PGTABLE_LEVELS > 2
1032 # Supported by clang >= 7.0
1033 config CC_HAVE_SHADOW_CALL_STACK
1034 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1037 bool "Enable seccomp to safely compute untrusted bytecode"
1039 This kernel feature is useful for number crunching applications
1040 that may need to compute untrusted bytecode during their
1041 execution. By using pipes or other transports made available to
1042 the process as file descriptors supporting the read/write
1043 syscalls, it's possible to isolate those applications in
1044 their own address space using seccomp. Once seccomp is
1045 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1046 and the task is only allowed to execute a few safe syscalls
1047 defined by each seccomp mode.
1050 bool "Enable paravirtualization code"
1052 This changes the kernel so it can modify itself when it is run
1053 under a hypervisor, potentially improving performance significantly
1054 over full virtualization.
1056 config PARAVIRT_TIME_ACCOUNTING
1057 bool "Paravirtual steal time accounting"
1060 Select this option to enable fine granularity task steal time
1061 accounting. Time spent executing other tasks in parallel with
1062 the current vCPU is discounted from the vCPU power. To account for
1063 that, there can be a small performance impact.
1065 If in doubt, say N here.
1068 depends on PM_SLEEP_SMP
1070 bool "kexec system call"
1072 kexec is a system call that implements the ability to shutdown your
1073 current kernel, and to start another kernel. It is like a reboot
1074 but it is independent of the system firmware. And like a reboot
1075 you can start any kernel with it, not just Linux.
1078 bool "kexec file based system call"
1081 This is new version of kexec system call. This system call is
1082 file based and takes file descriptors as system call argument
1083 for kernel and initramfs as opposed to list of segments as
1084 accepted by previous system call.
1087 bool "Verify kernel signature during kexec_file_load() syscall"
1088 depends on KEXEC_FILE
1090 Select this option to verify a signature with loaded kernel
1091 image. If configured, any attempt of loading a image without
1092 valid signature will fail.
1094 In addition to that option, you need to enable signature
1095 verification for the corresponding kernel image type being
1096 loaded in order for this to work.
1098 config KEXEC_IMAGE_VERIFY_SIG
1099 bool "Enable Image signature verification support"
1101 depends on KEXEC_SIG
1102 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1104 Enable Image signature verification support.
1106 comment "Support for PE file signature verification disabled"
1107 depends on KEXEC_SIG
1108 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1111 bool "Build kdump crash kernel"
1113 Generate crash dump after being started by kexec. This should
1114 be normally only set in special crash dump kernels which are
1115 loaded in the main kernel with kexec-tools into a specially
1116 reserved region and then later executed after a crash by
1119 For more details see Documentation/admin-guide/kdump/kdump.rst
1126 bool "Xen guest support on ARM64"
1127 depends on ARM64 && OF
1131 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1133 config FORCE_MAX_ZONEORDER
1135 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1136 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1139 The kernel memory allocator divides physically contiguous memory
1140 blocks into "zones", where each zone is a power of two number of
1141 pages. This option selects the largest power of two that the kernel
1142 keeps in the memory allocator. If you need to allocate very large
1143 blocks of physically contiguous memory, then you may need to
1144 increase this value.
1146 This config option is actually maximum order plus one. For example,
1147 a value of 11 means that the largest free memory block is 2^10 pages.
1149 We make sure that we can allocate upto a HugePage size for each configuration.
1151 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1153 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1154 4M allocations matching the default size used by generic code.
1156 config UNMAP_KERNEL_AT_EL0
1157 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1160 Speculation attacks against some high-performance processors can
1161 be used to bypass MMU permission checks and leak kernel data to
1162 userspace. This can be defended against by unmapping the kernel
1163 when running in userspace, mapping it back in on exception entry
1164 via a trampoline page in the vector table.
1168 config HARDEN_BRANCH_PREDICTOR
1169 bool "Harden the branch predictor against aliasing attacks" if EXPERT
1172 Speculation attacks against some high-performance processors rely on
1173 being able to manipulate the branch predictor for a victim context by
1174 executing aliasing branches in the attacker context. Such attacks
1175 can be partially mitigated against by clearing internal branch
1176 predictor state and limiting the prediction logic in some situations.
1178 This config option will take CPU-specific actions to harden the
1179 branch predictor against aliasing attacks and may rely on specific
1180 instruction sequences or control bits being set by the system
1185 config HARDEN_EL2_VECTORS
1186 bool "Harden EL2 vector mapping against system register leak" if EXPERT
1189 Speculation attacks against some high-performance processors can
1190 be used to leak privileged information such as the vector base
1191 register, resulting in a potential defeat of the EL2 layout
1194 This config option will map the vectors to a fixed location,
1195 independent of the EL2 code mapping, so that revealing VBAR_EL2
1196 to an attacker does not give away any extra information. This
1197 only gets enabled on affected CPUs.
1202 bool "Speculative Store Bypass Disable" if EXPERT
1205 This enables mitigation of the bypassing of previous stores
1206 by speculative loads.
1210 config RODATA_FULL_DEFAULT_ENABLED
1211 bool "Apply r/o permissions of VM areas also to their linear aliases"
1214 Apply read-only attributes of VM areas to the linear alias of
1215 the backing pages as well. This prevents code or read-only data
1216 from being modified (inadvertently or intentionally) via another
1217 mapping of the same memory page. This additional enhancement can
1218 be turned off at runtime by passing rodata=[off|on] (and turned on
1219 with rodata=full if this option is set to 'n')
1221 This requires the linear region to be mapped down to pages,
1222 which may adversely affect performance in some cases.
1224 config ARM64_SW_TTBR0_PAN
1225 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1227 Enabling this option prevents the kernel from accessing
1228 user-space memory directly by pointing TTBR0_EL1 to a reserved
1229 zeroed area and reserved ASID. The user access routines
1230 restore the valid TTBR0_EL1 temporarily.
1232 config ARM64_TAGGED_ADDR_ABI
1233 bool "Enable the tagged user addresses syscall ABI"
1236 When this option is enabled, user applications can opt in to a
1237 relaxed ABI via prctl() allowing tagged addresses to be passed
1238 to system calls as pointer arguments. For details, see
1239 Documentation/arm64/tagged-address-abi.rst.
1242 bool "Kernel support for 32-bit EL0"
1243 depends on ARM64_4K_PAGES || EXPERT
1244 select COMPAT_BINFMT_ELF if BINFMT_ELF
1246 select OLD_SIGSUSPEND3
1247 select COMPAT_OLD_SIGACTION
1249 This option enables support for a 32-bit EL0 running under a 64-bit
1250 kernel at EL1. AArch32-specific components such as system calls,
1251 the user helper functions, VFP support and the ptrace interface are
1252 handled appropriately by the kernel.
1254 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1255 that you will only be able to execute AArch32 binaries that were compiled
1256 with page size aligned segments.
1258 If you want to execute 32-bit userspace applications, say Y.
1262 config KUSER_HELPERS
1263 bool "Enable kuser helpers page for 32-bit applications"
1266 Warning: disabling this option may break 32-bit user programs.
1268 Provide kuser helpers to compat tasks. The kernel provides
1269 helper code to userspace in read only form at a fixed location
1270 to allow userspace to be independent of the CPU type fitted to
1271 the system. This permits binaries to be run on ARMv4 through
1272 to ARMv8 without modification.
1274 See Documentation/arm/kernel_user_helpers.rst for details.
1276 However, the fixed address nature of these helpers can be used
1277 by ROP (return orientated programming) authors when creating
1280 If all of the binaries and libraries which run on your platform
1281 are built specifically for your platform, and make no use of
1282 these helpers, then you can turn this option off to hinder
1283 such exploits. However, in that case, if a binary or library
1284 relying on those helpers is run, it will not function correctly.
1286 Say N here only if you are absolutely certain that you do not
1287 need these helpers; otherwise, the safe option is to say Y.
1290 bool "Enable vDSO for 32-bit applications"
1291 depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1292 select GENERIC_COMPAT_VDSO
1295 Place in the process address space of 32-bit applications an
1296 ELF shared object providing fast implementations of gettimeofday
1299 You must have a 32-bit build of glibc 2.22 or later for programs
1300 to seamlessly take advantage of this.
1302 config THUMB2_COMPAT_VDSO
1303 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1304 depends on COMPAT_VDSO
1307 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1308 otherwise with '-marm'.
1310 menuconfig ARMV8_DEPRECATED
1311 bool "Emulate deprecated/obsolete ARMv8 instructions"
1314 Legacy software support may require certain instructions
1315 that have been deprecated or obsoleted in the architecture.
1317 Enable this config to enable selective emulation of these
1324 config SWP_EMULATION
1325 bool "Emulate SWP/SWPB instructions"
1327 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1328 they are always undefined. Say Y here to enable software
1329 emulation of these instructions for userspace using LDXR/STXR.
1331 In some older versions of glibc [<=2.8] SWP is used during futex
1332 trylock() operations with the assumption that the code will not
1333 be preempted. This invalid assumption may be more likely to fail
1334 with SWP emulation enabled, leading to deadlock of the user
1337 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1338 on an external transaction monitoring block called a global
1339 monitor to maintain update atomicity. If your system does not
1340 implement a global monitor, this option can cause programs that
1341 perform SWP operations to uncached memory to deadlock.
1345 config CP15_BARRIER_EMULATION
1346 bool "Emulate CP15 Barrier instructions"
1348 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1349 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1350 strongly recommended to use the ISB, DSB, and DMB
1351 instructions instead.
1353 Say Y here to enable software emulation of these
1354 instructions for AArch32 userspace code. When this option is
1355 enabled, CP15 barrier usage is traced which can help
1356 identify software that needs updating.
1360 config SETEND_EMULATION
1361 bool "Emulate SETEND instruction"
1363 The SETEND instruction alters the data-endianness of the
1364 AArch32 EL0, and is deprecated in ARMv8.
1366 Say Y here to enable software emulation of the instruction
1367 for AArch32 userspace code.
1369 Note: All the cpus on the system must have mixed endian support at EL0
1370 for this feature to be enabled. If a new CPU - which doesn't support mixed
1371 endian - is hotplugged in after this feature has been enabled, there could
1372 be unexpected results in the applications.
1379 menu "ARMv8.1 architectural features"
1381 config ARM64_HW_AFDBM
1382 bool "Support for hardware updates of the Access and Dirty page flags"
1385 The ARMv8.1 architecture extensions introduce support for
1386 hardware updates of the access and dirty information in page
1387 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1388 capable processors, accesses to pages with PTE_AF cleared will
1389 set this bit instead of raising an access flag fault.
1390 Similarly, writes to read-only pages with the DBM bit set will
1391 clear the read-only bit (AP[2]) instead of raising a
1394 Kernels built with this configuration option enabled continue
1395 to work on pre-ARMv8.1 hardware and the performance impact is
1396 minimal. If unsure, say Y.
1399 bool "Enable support for Privileged Access Never (PAN)"
1402 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1403 prevents the kernel or hypervisor from accessing user-space (EL0)
1406 Choosing this option will cause any unprotected (not using
1407 copy_to_user et al) memory access to fail with a permission fault.
1409 The feature is detected at runtime, and will remain as a 'nop'
1410 instruction if the cpu does not implement the feature.
1412 config ARM64_LSE_ATOMICS
1414 default ARM64_USE_LSE_ATOMICS
1415 depends on $(as-instr,.arch_extension lse)
1417 config ARM64_USE_LSE_ATOMICS
1418 bool "Atomic instructions"
1419 depends on JUMP_LABEL
1422 As part of the Large System Extensions, ARMv8.1 introduces new
1423 atomic instructions that are designed specifically to scale in
1426 Say Y here to make use of these instructions for the in-kernel
1427 atomic routines. This incurs a small overhead on CPUs that do
1428 not support these instructions and requires the kernel to be
1429 built with binutils >= 2.25 in order for the new instructions
1433 bool "Enable support for Virtualization Host Extensions (VHE)"
1436 Virtualization Host Extensions (VHE) allow the kernel to run
1437 directly at EL2 (instead of EL1) on processors that support
1438 it. This leads to better performance for KVM, as they reduce
1439 the cost of the world switch.
1441 Selecting this option allows the VHE feature to be detected
1442 at runtime, and does not affect processors that do not
1443 implement this feature.
1447 menu "ARMv8.2 architectural features"
1450 bool "Enable support for User Access Override (UAO)"
1453 User Access Override (UAO; part of the ARMv8.2 Extensions)
1454 causes the 'unprivileged' variant of the load/store instructions to
1455 be overridden to be privileged.
1457 This option changes get_user() and friends to use the 'unprivileged'
1458 variant of the load/store instructions. This ensures that user-space
1459 really did have access to the supplied memory. When addr_limit is
1460 set to kernel memory the UAO bit will be set, allowing privileged
1461 access to kernel memory.
1463 Choosing this option will cause copy_to_user() et al to use user-space
1466 The feature is detected at runtime, the kernel will use the
1467 regular load/store instructions if the cpu does not implement the
1471 bool "Enable support for persistent memory"
1472 select ARCH_HAS_PMEM_API
1473 select ARCH_HAS_UACCESS_FLUSHCACHE
1475 Say Y to enable support for the persistent memory API based on the
1476 ARMv8.2 DCPoP feature.
1478 The feature is detected at runtime, and the kernel will use DC CVAC
1479 operations if DC CVAP is not supported (following the behaviour of
1480 DC CVAP itself if the system does not define a point of persistence).
1482 config ARM64_RAS_EXTN
1483 bool "Enable support for RAS CPU Extensions"
1486 CPUs that support the Reliability, Availability and Serviceability
1487 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1488 errors, classify them and report them to software.
1490 On CPUs with these extensions system software can use additional
1491 barriers to determine if faults are pending and read the
1492 classification from a new set of registers.
1494 Selecting this feature will allow the kernel to use these barriers
1495 and access the new registers if the system supports the extension.
1496 Platform RAS features may additionally depend on firmware support.
1499 bool "Enable support for Common Not Private (CNP) translations"
1501 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1503 Common Not Private (CNP) allows translation table entries to
1504 be shared between different PEs in the same inner shareable
1505 domain, so the hardware can use this fact to optimise the
1506 caching of such entries in the TLB.
1508 Selecting this option allows the CNP feature to be detected
1509 at runtime, and does not affect PEs that do not implement
1514 menu "ARMv8.3 architectural features"
1516 config ARM64_PTR_AUTH
1517 bool "Enable support for pointer authentication"
1519 depends on !KVM || ARM64_VHE
1520 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1521 # Modern compilers insert a .note.gnu.property section note for PAC
1522 # which is only understood by binutils starting with version 2.33.1.
1523 depends on LD_IS_LLD || LD_VERSION >= 233010000 || (CC_IS_GCC && GCC_VERSION < 90100)
1524 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1525 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1527 Pointer authentication (part of the ARMv8.3 Extensions) provides
1528 instructions for signing and authenticating pointers against secret
1529 keys, which can be used to mitigate Return Oriented Programming (ROP)
1532 This option enables these instructions at EL0 (i.e. for userspace).
1533 Choosing this option will cause the kernel to initialise secret keys
1534 for each process at exec() time, with these keys being
1535 context-switched along with the process.
1537 If the compiler supports the -mbranch-protection or
1538 -msign-return-address flag (e.g. GCC 7 or later), then this option
1539 will also cause the kernel itself to be compiled with return address
1540 protection. In this case, and if the target hardware is known to
1541 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1542 disabled with minimal loss of protection.
1544 The feature is detected at runtime. If the feature is not present in
1545 hardware it will not be advertised to userspace/KVM guest nor will it
1546 be enabled. However, KVM guest also require VHE mode and hence
1547 CONFIG_ARM64_VHE=y option to use this feature.
1549 If the feature is present on the boot CPU but not on a late CPU, then
1550 the late CPU will be parked. Also, if the boot CPU does not have
1551 address auth and the late CPU has then the late CPU will still boot
1552 but with the feature disabled. On such a system, this option should
1555 This feature works with FUNCTION_GRAPH_TRACER option only if
1556 DYNAMIC_FTRACE_WITH_REGS is enabled.
1558 config CC_HAS_BRANCH_PROT_PAC_RET
1559 # GCC 9 or later, clang 8 or later
1560 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1562 config CC_HAS_SIGN_RETURN_ADDRESS
1564 def_bool $(cc-option,-msign-return-address=all)
1567 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1569 config AS_HAS_CFI_NEGATE_RA_STATE
1570 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1574 menu "ARMv8.4 architectural features"
1576 config ARM64_AMU_EXTN
1577 bool "Enable support for the Activity Monitors Unit CPU extension"
1580 The activity monitors extension is an optional extension introduced
1581 by the ARMv8.4 CPU architecture. This enables support for version 1
1582 of the activity monitors architecture, AMUv1.
1584 To enable the use of this extension on CPUs that implement it, say Y.
1586 Note that for architectural reasons, firmware _must_ implement AMU
1587 support when running on CPUs that present the activity monitors
1588 extension. The required support is present in:
1589 * Version 1.5 and later of the ARM Trusted Firmware
1591 For kernels that have this configuration enabled but boot with broken
1592 firmware, you may need to say N here until the firmware is fixed.
1593 Otherwise you may experience firmware panics or lockups when
1594 accessing the counter registers. Even if you are not observing these
1595 symptoms, the values returned by the register reads might not
1596 correctly reflect reality. Most commonly, the value read will be 0,
1597 indicating that the counter is not enabled.
1601 menu "ARMv8.5 architectural features"
1604 bool "Branch Target Identification support"
1607 Branch Target Identification (part of the ARMv8.5 Extensions)
1608 provides a mechanism to limit the set of locations to which computed
1609 branch instructions such as BR or BLR can jump.
1611 To make use of BTI on CPUs that support it, say Y.
1613 BTI is intended to provide complementary protection to other control
1614 flow integrity protection mechanisms, such as the Pointer
1615 authentication mechanism provided as part of the ARMv8.3 Extensions.
1616 For this reason, it does not make sense to enable this option without
1617 also enabling support for pointer authentication. Thus, when
1618 enabling this option you should also select ARM64_PTR_AUTH=y.
1620 Userspace binaries must also be specifically compiled to make use of
1621 this mechanism. If you say N here or the hardware does not support
1622 BTI, such binaries can still run, but you get no additional
1623 enforcement of branch destinations.
1625 config ARM64_BTI_KERNEL
1626 bool "Use Branch Target Identification for kernel"
1628 depends on ARM64_BTI
1629 depends on ARM64_PTR_AUTH
1630 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1631 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1632 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1633 # https://reviews.llvm.org/rGb8ae3fdfa579dbf366b1bb1cbfdbf8c51db7fa55
1634 depends on !CC_IS_CLANG || CLANG_VERSION >= 100001
1635 depends on !(CC_IS_CLANG && GCOV_KERNEL)
1636 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1638 Build the kernel with Branch Target Identification annotations
1639 and enable enforcement of this for kernel code. When this option
1640 is enabled and the system supports BTI all kernel code including
1641 modular code must have BTI enabled.
1643 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1644 # GCC 9 or later, clang 8 or later
1645 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1648 bool "Enable support for E0PD"
1651 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1652 that EL0 accesses made via TTBR1 always fault in constant time,
1653 providing similar benefits to KASLR as those provided by KPTI, but
1654 with lower overhead and without disrupting legitimate access to
1655 kernel memory such as SPE.
1657 This option enables E0PD for TTBR1 where available.
1660 bool "Enable support for random number generation"
1663 Random number generation (part of the ARMv8.5 Extensions)
1664 provides a high bandwidth, cryptographically secure
1665 hardware random number generator.
1670 bool "ARM Scalable Vector Extension support"
1672 depends on !KVM || ARM64_VHE
1674 The Scalable Vector Extension (SVE) is an extension to the AArch64
1675 execution state which complements and extends the SIMD functionality
1676 of the base architecture to support much larger vectors and to enable
1677 additional vectorisation opportunities.
1679 To enable use of this extension on CPUs that implement it, say Y.
1681 On CPUs that support the SVE2 extensions, this option will enable
1684 Note that for architectural reasons, firmware _must_ implement SVE
1685 support when running on SVE capable hardware. The required support
1688 * version 1.5 and later of the ARM Trusted Firmware
1689 * the AArch64 boot wrapper since commit 5e1261e08abf
1690 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1692 For other firmware implementations, consult the firmware documentation
1695 If you need the kernel to boot on SVE-capable hardware with broken
1696 firmware, you may need to say N here until you get your firmware
1697 fixed. Otherwise, you may experience firmware panics or lockups when
1698 booting the kernel. If unsure and you are not observing these
1699 symptoms, you should assume that it is safe to say Y.
1701 CPUs that support SVE are architecturally required to support the
1702 Virtualization Host Extensions (VHE), so the kernel makes no
1703 provision for supporting SVE alongside KVM without VHE enabled.
1704 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1705 KVM in the same kernel image.
1707 config ARM64_MODULE_PLTS
1708 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1710 select HAVE_MOD_ARCH_SPECIFIC
1712 Allocate PLTs when loading modules so that jumps and calls whose
1713 targets are too far away for their relative offsets to be encoded
1714 in the instructions themselves can be bounced via veneers in the
1715 module's PLT. This allows modules to be allocated in the generic
1716 vmalloc area after the dedicated module memory area has been
1719 When running with address space randomization (KASLR), the module
1720 region itself may be too far away for ordinary relative jumps and
1721 calls, and so in that case, module PLTs are required and cannot be
1724 Specific errata workaround(s) might also force module PLTs to be
1725 enabled (ARM64_ERRATUM_843419).
1727 config ARM64_PSEUDO_NMI
1728 bool "Support for NMI-like interrupts"
1731 Adds support for mimicking Non-Maskable Interrupts through the use of
1732 GIC interrupt priority. This support requires version 3 or later of
1735 This high priority configuration for interrupts needs to be
1736 explicitly enabled by setting the kernel parameter
1737 "irqchip.gicv3_pseudo_nmi" to 1.
1742 config ARM64_DEBUG_PRIORITY_MASKING
1743 bool "Debug interrupt priority masking"
1745 This adds runtime checks to functions enabling/disabling
1746 interrupts when using priority masking. The additional checks verify
1747 the validity of ICC_PMR_EL1 when calling concerned functions.
1753 bool "Build a relocatable kernel image" if EXPERT
1754 select ARCH_HAS_RELR
1757 This builds the kernel as a Position Independent Executable (PIE),
1758 which retains all relocation metadata required to relocate the
1759 kernel binary at runtime to a different virtual address than the
1760 address it was linked at.
1761 Since AArch64 uses the RELA relocation format, this requires a
1762 relocation pass at runtime even if the kernel is loaded at the
1763 same address it was linked at.
1765 config RANDOMIZE_BASE
1766 bool "Randomize the address of the kernel image"
1767 select ARM64_MODULE_PLTS if MODULES
1770 Randomizes the virtual address at which the kernel image is
1771 loaded, as a security feature that deters exploit attempts
1772 relying on knowledge of the location of kernel internals.
1774 It is the bootloader's job to provide entropy, by passing a
1775 random u64 value in /chosen/kaslr-seed at kernel entry.
1777 When booting via the UEFI stub, it will invoke the firmware's
1778 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1779 to the kernel proper. In addition, it will randomise the physical
1780 location of the kernel Image as well.
1784 config RANDOMIZE_MODULE_REGION_FULL
1785 bool "Randomize the module region over a 4 GB range"
1786 depends on RANDOMIZE_BASE
1789 Randomizes the location of the module region inside a 4 GB window
1790 covering the core kernel. This way, it is less likely for modules
1791 to leak information about the location of core kernel data structures
1792 but it does imply that function calls between modules and the core
1793 kernel will need to be resolved via veneers in the module PLT.
1795 When this option is not set, the module region will be randomized over
1796 a limited range that contains the [_stext, _etext] interval of the
1797 core kernel, so branch relocations are always in range.
1799 config CC_HAVE_STACKPROTECTOR_SYSREG
1800 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1802 config STACKPROTECTOR_PER_TASK
1804 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1810 config ARM64_ACPI_PARKING_PROTOCOL
1811 bool "Enable support for the ARM64 ACPI parking protocol"
1814 Enable support for the ARM64 ACPI parking protocol. If disabled
1815 the kernel will not allow booting through the ARM64 ACPI parking
1816 protocol even if the corresponding data is present in the ACPI
1820 string "Default kernel command string"
1823 Provide a set of default command-line options at build time by
1824 entering them here. As a minimum, you should specify the the
1825 root device (e.g. root=/dev/nfs).
1827 config CMDLINE_FORCE
1828 bool "Always use the default kernel command string"
1829 depends on CMDLINE != ""
1831 Always use the default kernel command string, even if the boot
1832 loader passes other arguments to the kernel.
1833 This is useful if you cannot or don't want to change the
1834 command-line options your boot loader passes to the kernel.
1840 bool "UEFI runtime support"
1841 depends on OF && !CPU_BIG_ENDIAN
1842 depends on KERNEL_MODE_NEON
1843 select ARCH_SUPPORTS_ACPI
1846 select EFI_PARAMS_FROM_FDT
1847 select EFI_RUNTIME_WRAPPERS
1849 select EFI_GENERIC_STUB
1852 This option provides support for runtime services provided
1853 by UEFI firmware (such as non-volatile variables, realtime
1854 clock, and platform reset). A UEFI stub is also provided to
1855 allow the kernel to be booted as an EFI application. This
1856 is only useful on systems that have UEFI firmware.
1859 bool "Enable support for SMBIOS (DMI) tables"
1863 This enables SMBIOS/DMI feature for systems.
1865 This option is only useful on systems that have UEFI firmware.
1866 However, even with this option, the resultant kernel should
1867 continue to boot on existing non-UEFI platforms.
1871 config SYSVIPC_COMPAT
1873 depends on COMPAT && SYSVIPC
1875 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1877 depends on HUGETLB_PAGE && MIGRATION
1879 menu "Power management options"
1881 source "kernel/power/Kconfig"
1883 config ARCH_HIBERNATION_POSSIBLE
1887 config ARCH_HIBERNATION_HEADER
1889 depends on HIBERNATION
1891 config ARCH_SUSPEND_POSSIBLE
1896 menu "CPU Power Management"
1898 source "drivers/cpuidle/Kconfig"
1900 source "drivers/cpufreq/Kconfig"
1904 source "drivers/firmware/Kconfig"
1906 source "drivers/acpi/Kconfig"
1908 source "arch/arm64/kvm/Kconfig"
1911 source "arch/arm64/crypto/Kconfig"