1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_APMT if ACPI
5 select ACPI_CCA_REQUIRED if ACPI
6 select ACPI_GENERIC_GSI if ACPI
7 select ACPI_GTDT if ACPI
8 select ACPI_IORT if ACPI
9 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
10 select ACPI_MCFG if (ACPI && PCI)
11 select ACPI_SPCR_TABLE if ACPI
12 select ACPI_PPTT if ACPI
13 select ARCH_HAS_DEBUG_WX
14 select ARCH_BINFMT_ELF_EXTRA_PHDRS
15 select ARCH_BINFMT_ELF_STATE
16 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE
17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
18 select ARCH_ENABLE_MEMORY_HOTPLUG
19 select ARCH_ENABLE_MEMORY_HOTREMOVE
20 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
21 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
22 select ARCH_HAS_CACHE_LINE_SIZE
23 select ARCH_HAS_CURRENT_STACK_POINTER
24 select ARCH_HAS_DEBUG_VIRTUAL
25 select ARCH_HAS_DEBUG_VM_PGTABLE
26 select ARCH_HAS_DMA_PREP_COHERENT
27 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
28 select ARCH_HAS_FAST_MULTIPLIER
29 select ARCH_HAS_FORTIFY_SOURCE
30 select ARCH_HAS_GCOV_PROFILE_ALL
31 select ARCH_HAS_GIGANTIC_PAGE
33 select ARCH_HAS_KEEPINITRD
34 select ARCH_HAS_MEMBARRIER_SYNC_CORE
35 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS
36 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
37 select ARCH_HAS_PTE_DEVMAP
38 select ARCH_HAS_PTE_SPECIAL
39 select ARCH_HAS_SETUP_DMA_OPS
40 select ARCH_HAS_SET_DIRECT_MAP
41 select ARCH_HAS_SET_MEMORY
43 select ARCH_HAS_STRICT_KERNEL_RWX
44 select ARCH_HAS_STRICT_MODULE_RWX
45 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
46 select ARCH_HAS_SYNC_DMA_FOR_CPU
47 select ARCH_HAS_SYSCALL_WRAPPER
48 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
49 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
50 select ARCH_HAS_ZONE_DMA_SET if EXPERT
51 select ARCH_HAVE_ELF_PROT
52 select ARCH_HAVE_NMI_SAFE_CMPXCHG
53 select ARCH_HAVE_TRACE_MMIO_ACCESS
54 select ARCH_INLINE_READ_LOCK if !PREEMPTION
55 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
56 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
57 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
58 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
59 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
60 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
61 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
62 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
63 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
64 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
65 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
66 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
67 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
68 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
69 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
70 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
71 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
72 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
73 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
74 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
75 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
76 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
77 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
78 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
79 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
80 select ARCH_KEEP_MEMBLOCK
81 select ARCH_USE_CMPXCHG_LOCKREF
82 select ARCH_USE_GNU_PROPERTY
83 select ARCH_USE_MEMTEST
84 select ARCH_USE_QUEUED_RWLOCKS
85 select ARCH_USE_QUEUED_SPINLOCKS
86 select ARCH_USE_SYM_ANNOTATIONS
87 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
88 select ARCH_SUPPORTS_HUGETLBFS
89 select ARCH_SUPPORTS_MEMORY_FAILURE
90 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
91 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
92 select ARCH_SUPPORTS_LTO_CLANG_THIN
93 select ARCH_SUPPORTS_CFI_CLANG
94 select ARCH_SUPPORTS_ATOMIC_RMW
95 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
96 select ARCH_SUPPORTS_NUMA_BALANCING
97 select ARCH_SUPPORTS_PAGE_TABLE_CHECK
98 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
99 select ARCH_WANT_DEFAULT_BPF_JIT
100 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
101 select ARCH_WANT_FRAME_POINTERS
102 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
103 select ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP
104 select ARCH_WANT_LD_ORPHAN_WARN
105 select ARCH_WANTS_NO_INSTR
106 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES
107 select ARCH_HAS_UBSAN_SANITIZE_ALL
109 select ARM_ARCH_TIMER
111 select AUDIT_ARCH_COMPAT_GENERIC
112 select ARM_GIC_V2M if PCI
114 select ARM_GIC_V3_ITS if PCI
116 select BUILDTIME_TABLE_SORT
117 select CLONE_BACKWARDS
119 select CPU_PM if (SUSPEND || CPU_IDLE)
121 select DCACHE_WORD_ACCESS
122 select DYNAMIC_FTRACE if FUNCTION_TRACER
123 select DMA_DIRECT_REMAP
126 select FUNCTION_ALIGNMENT_4B
127 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS
128 select GENERIC_ALLOCATOR
129 select GENERIC_ARCH_TOPOLOGY
130 select GENERIC_CLOCKEVENTS_BROADCAST
131 select GENERIC_CPU_AUTOPROBE
132 select GENERIC_CPU_VULNERABILITIES
133 select GENERIC_EARLY_IOREMAP
134 select GENERIC_IDLE_POLL_SETUP
135 select GENERIC_IOREMAP
136 select GENERIC_IRQ_IPI
137 select GENERIC_IRQ_PROBE
138 select GENERIC_IRQ_SHOW
139 select GENERIC_IRQ_SHOW_LEVEL
140 select GENERIC_LIB_DEVMEM_IS_ALLOWED
141 select GENERIC_PCI_IOMAP
142 select GENERIC_PTDUMP
143 select GENERIC_SCHED_CLOCK
144 select GENERIC_SMP_IDLE_THREAD
145 select GENERIC_TIME_VSYSCALL
146 select GENERIC_GETTIMEOFDAY
147 select GENERIC_VDSO_TIME_NS
148 select HARDIRQS_SW_RESEND
152 select HAVE_ACPI_APEI if (ACPI && EFI)
153 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
154 select HAVE_ARCH_AUDITSYSCALL
155 select HAVE_ARCH_BITREVERSE
156 select HAVE_ARCH_COMPILER_H
157 select HAVE_ARCH_HUGE_VMALLOC
158 select HAVE_ARCH_HUGE_VMAP
159 select HAVE_ARCH_JUMP_LABEL
160 select HAVE_ARCH_JUMP_LABEL_RELATIVE
161 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
162 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
163 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
164 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
165 # Some instrumentation may be unsound, hence EXPERT
166 select HAVE_ARCH_KCSAN if EXPERT
167 select HAVE_ARCH_KFENCE
168 select HAVE_ARCH_KGDB
169 select HAVE_ARCH_MMAP_RND_BITS
170 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
171 select HAVE_ARCH_PREL32_RELOCATIONS
172 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
173 select HAVE_ARCH_SECCOMP_FILTER
174 select HAVE_ARCH_STACKLEAK
175 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
176 select HAVE_ARCH_TRACEHOOK
177 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
178 select HAVE_ARCH_VMAP_STACK
179 select HAVE_ARM_SMCCC
180 select HAVE_ASM_MODVERSIONS
182 select HAVE_C_RECORDMCOUNT
183 select HAVE_CMPXCHG_DOUBLE
184 select HAVE_CMPXCHG_LOCAL
185 select HAVE_CONTEXT_TRACKING_USER
186 select HAVE_DEBUG_KMEMLEAK
187 select HAVE_DMA_CONTIGUOUS
188 select HAVE_DYNAMIC_FTRACE
189 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \
190 if $(cc-option,-fpatchable-function-entry=2)
191 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \
192 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG)
193 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
194 if DYNAMIC_FTRACE_WITH_ARGS
195 select HAVE_EFFICIENT_UNALIGNED_ACCESS
197 select HAVE_FTRACE_MCOUNT_RECORD
198 select HAVE_FUNCTION_TRACER
199 select HAVE_FUNCTION_ERROR_INJECTION
200 select HAVE_FUNCTION_GRAPH_TRACER
201 select HAVE_GCC_PLUGINS
202 select HAVE_HW_BREAKPOINT if PERF_EVENTS
203 select HAVE_IOREMAP_PROT
204 select HAVE_IRQ_TIME_ACCOUNTING
207 select HAVE_PERF_EVENTS
208 select HAVE_PERF_REGS
209 select HAVE_PERF_USER_STACK_DUMP
210 select HAVE_PREEMPT_DYNAMIC_KEY
211 select HAVE_REGS_AND_STACK_ACCESS_API
212 select HAVE_POSIX_CPU_TIMERS_TASK_WORK
213 select HAVE_FUNCTION_ARG_ACCESS_API
214 select MMU_GATHER_RCU_TABLE_FREE
216 select HAVE_STACKPROTECTOR
217 select HAVE_SYSCALL_TRACEPOINTS
219 select HAVE_KRETPROBES
220 select HAVE_GENERIC_VDSO
222 select IRQ_FORCED_THREADING
223 select KASAN_VMALLOC if KASAN
224 select MODULES_USE_ELF_RELA
225 select NEED_DMA_MAP_STATE
226 select NEED_SG_DMA_LENGTH
228 select OF_EARLY_FLATTREE
229 select PCI_DOMAINS_GENERIC if PCI
230 select PCI_ECAM if (ACPI && PCI)
231 select PCI_SYSCALL if PCI
236 select SYSCTL_EXCEPTION_TRACE
237 select THREAD_INFO_IN_TASK
238 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
239 select TRACE_IRQFLAGS_SUPPORT
240 select TRACE_IRQFLAGS_NMI_SUPPORT
241 select HAVE_SOFTIRQ_ON_OWN_STACK
243 ARM 64-bit (AArch64) Linux support.
245 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
247 # https://github.com/ClangBuiltLinux/linux/issues/1507
248 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600))
249 select HAVE_DYNAMIC_FTRACE_WITH_ARGS
251 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
253 depends on $(cc-option,-fpatchable-function-entry=2)
254 select HAVE_DYNAMIC_FTRACE_WITH_ARGS
262 config ARM64_PAGE_SHIFT
264 default 16 if ARM64_64K_PAGES
265 default 14 if ARM64_16K_PAGES
268 config ARM64_CONT_PTE_SHIFT
270 default 5 if ARM64_64K_PAGES
271 default 7 if ARM64_16K_PAGES
274 config ARM64_CONT_PMD_SHIFT
276 default 5 if ARM64_64K_PAGES
277 default 5 if ARM64_16K_PAGES
280 config ARCH_MMAP_RND_BITS_MIN
281 default 14 if ARM64_64K_PAGES
282 default 16 if ARM64_16K_PAGES
285 # max bits determined by the following formula:
286 # VA_BITS - PAGE_SHIFT - 3
287 config ARCH_MMAP_RND_BITS_MAX
288 default 19 if ARM64_VA_BITS=36
289 default 24 if ARM64_VA_BITS=39
290 default 27 if ARM64_VA_BITS=42
291 default 30 if ARM64_VA_BITS=47
292 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
293 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
294 default 33 if ARM64_VA_BITS=48
295 default 14 if ARM64_64K_PAGES
296 default 16 if ARM64_16K_PAGES
299 config ARCH_MMAP_RND_COMPAT_BITS_MIN
300 default 7 if ARM64_64K_PAGES
301 default 9 if ARM64_16K_PAGES
304 config ARCH_MMAP_RND_COMPAT_BITS_MAX
310 config STACKTRACE_SUPPORT
313 config ILLEGAL_POINTER_VALUE
315 default 0xdead000000000000
317 config LOCKDEP_SUPPORT
324 config GENERIC_BUG_RELATIVE_POINTERS
326 depends on GENERIC_BUG
328 config GENERIC_HWEIGHT
334 config GENERIC_CALIBRATE_DELAY
337 config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
343 config KERNEL_MODE_NEON
346 config FIX_EARLYCON_MEM
349 config PGTABLE_LEVELS
351 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
352 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
353 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
354 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
355 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
356 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
358 config ARCH_SUPPORTS_UPROBES
361 config ARCH_PROC_KCORE_TEXT
364 config BROKEN_GAS_INST
365 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
367 config KASAN_SHADOW_OFFSET
369 depends on KASAN_GENERIC || KASAN_SW_TAGS
370 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
371 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
372 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
373 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
374 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
375 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
376 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
377 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
378 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
379 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
380 default 0xffffffffffffffff
385 source "arch/arm64/Kconfig.platforms"
387 menu "Kernel Features"
389 menu "ARM errata workarounds via the alternatives framework"
391 config ARM64_WORKAROUND_CLEAN_CACHE
394 config ARM64_ERRATUM_826319
395 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
397 select ARM64_WORKAROUND_CLEAN_CACHE
399 This option adds an alternative code sequence to work around ARM
400 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
401 AXI master interface and an L2 cache.
403 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
404 and is unable to accept a certain write via this interface, it will
405 not progress on read data presented on the read data channel and the
408 The workaround promotes data cache clean instructions to
409 data cache clean-and-invalidate.
410 Please note that this does not necessarily enable the workaround,
411 as it depends on the alternative framework, which will only patch
412 the kernel if an affected CPU is detected.
416 config ARM64_ERRATUM_827319
417 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
419 select ARM64_WORKAROUND_CLEAN_CACHE
421 This option adds an alternative code sequence to work around ARM
422 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
423 master interface and an L2 cache.
425 Under certain conditions this erratum can cause a clean line eviction
426 to occur at the same time as another transaction to the same address
427 on the AMBA 5 CHI interface, which can cause data corruption if the
428 interconnect reorders the two transactions.
430 The workaround promotes data cache clean instructions to
431 data cache clean-and-invalidate.
432 Please note that this does not necessarily enable the workaround,
433 as it depends on the alternative framework, which will only patch
434 the kernel if an affected CPU is detected.
438 config ARM64_ERRATUM_824069
439 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
441 select ARM64_WORKAROUND_CLEAN_CACHE
443 This option adds an alternative code sequence to work around ARM
444 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
445 to a coherent interconnect.
447 If a Cortex-A53 processor is executing a store or prefetch for
448 write instruction at the same time as a processor in another
449 cluster is executing a cache maintenance operation to the same
450 address, then this erratum might cause a clean cache line to be
451 incorrectly marked as dirty.
453 The workaround promotes data cache clean instructions to
454 data cache clean-and-invalidate.
455 Please note that this option does not necessarily enable the
456 workaround, as it depends on the alternative framework, which will
457 only patch the kernel if an affected CPU is detected.
461 config ARM64_ERRATUM_819472
462 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
464 select ARM64_WORKAROUND_CLEAN_CACHE
466 This option adds an alternative code sequence to work around ARM
467 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
468 present when it is connected to a coherent interconnect.
470 If the processor is executing a load and store exclusive sequence at
471 the same time as a processor in another cluster is executing a cache
472 maintenance operation to the same address, then this erratum might
473 cause data corruption.
475 The workaround promotes data cache clean instructions to
476 data cache clean-and-invalidate.
477 Please note that this does not necessarily enable the workaround,
478 as it depends on the alternative framework, which will only patch
479 the kernel if an affected CPU is detected.
483 config ARM64_ERRATUM_832075
484 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
487 This option adds an alternative code sequence to work around ARM
488 erratum 832075 on Cortex-A57 parts up to r1p2.
490 Affected Cortex-A57 parts might deadlock when exclusive load/store
491 instructions to Write-Back memory are mixed with Device loads.
493 The workaround is to promote device loads to use Load-Acquire
495 Please note that this does not necessarily enable the workaround,
496 as it depends on the alternative framework, which will only patch
497 the kernel if an affected CPU is detected.
501 config ARM64_ERRATUM_834220
502 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
506 This option adds an alternative code sequence to work around ARM
507 erratum 834220 on Cortex-A57 parts up to r1p2.
509 Affected Cortex-A57 parts might report a Stage 2 translation
510 fault as the result of a Stage 1 fault for load crossing a
511 page boundary when there is a permission or device memory
512 alignment fault at Stage 1 and a translation fault at Stage 2.
514 The workaround is to verify that the Stage 1 translation
515 doesn't generate a fault before handling the Stage 2 fault.
516 Please note that this does not necessarily enable the workaround,
517 as it depends on the alternative framework, which will only patch
518 the kernel if an affected CPU is detected.
522 config ARM64_ERRATUM_1742098
523 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence"
527 This option removes the AES hwcap for aarch32 user-space to
528 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
530 Affected parts may corrupt the AES state if an interrupt is
531 taken between a pair of AES instructions. These instructions
532 are only present if the cryptography extensions are present.
533 All software should have a fallback implementation for CPUs
534 that don't implement the cryptography extensions.
538 config ARM64_ERRATUM_845719
539 bool "Cortex-A53: 845719: a load might read incorrect data"
543 This option adds an alternative code sequence to work around ARM
544 erratum 845719 on Cortex-A53 parts up to r0p4.
546 When running a compat (AArch32) userspace on an affected Cortex-A53
547 part, a load at EL0 from a virtual address that matches the bottom 32
548 bits of the virtual address used by a recent load at (AArch64) EL1
549 might return incorrect data.
551 The workaround is to write the contextidr_el1 register on exception
552 return to a 32-bit task.
553 Please note that this does not necessarily enable the workaround,
554 as it depends on the alternative framework, which will only patch
555 the kernel if an affected CPU is detected.
559 config ARM64_ERRATUM_843419
560 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
562 select ARM64_MODULE_PLTS if MODULES
564 This option links the kernel with '--fix-cortex-a53-843419' and
565 enables PLT support to replace certain ADRP instructions, which can
566 cause subsequent memory accesses to use an incorrect address on
567 Cortex-A53 parts up to r0p4.
571 config ARM64_LD_HAS_FIX_ERRATUM_843419
572 def_bool $(ld-option,--fix-cortex-a53-843419)
574 config ARM64_ERRATUM_1024718
575 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
578 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
580 Affected Cortex-A55 cores (all revisions) could cause incorrect
581 update of the hardware dirty bit when the DBM/AP bits are updated
582 without a break-before-make. The workaround is to disable the usage
583 of hardware DBM locally on the affected cores. CPUs not affected by
584 this erratum will continue to use the feature.
588 config ARM64_ERRATUM_1418040
589 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
593 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
594 errata 1188873 and 1418040.
596 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
597 cause register corruption when accessing the timer registers
598 from AArch32 userspace.
602 config ARM64_WORKAROUND_SPECULATIVE_AT
605 config ARM64_ERRATUM_1165522
606 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
608 select ARM64_WORKAROUND_SPECULATIVE_AT
610 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
612 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
613 corrupted TLBs by speculating an AT instruction during a guest
618 config ARM64_ERRATUM_1319367
619 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
621 select ARM64_WORKAROUND_SPECULATIVE_AT
623 This option adds work arounds for ARM Cortex-A57 erratum 1319537
624 and A72 erratum 1319367
626 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
627 speculating an AT instruction during a guest context switch.
631 config ARM64_ERRATUM_1530923
632 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
634 select ARM64_WORKAROUND_SPECULATIVE_AT
636 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
638 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
639 corrupted TLBs by speculating an AT instruction during a guest
644 config ARM64_WORKAROUND_REPEAT_TLBI
647 config ARM64_ERRATUM_2441007
648 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
650 select ARM64_WORKAROUND_REPEAT_TLBI
652 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
654 Under very rare circumstances, affected Cortex-A55 CPUs
655 may not handle a race between a break-before-make sequence on one
656 CPU, and another CPU accessing the same page. This could allow a
657 store to a page that has been unmapped.
659 Work around this by adding the affected CPUs to the list that needs
660 TLB sequences to be done twice.
664 config ARM64_ERRATUM_1286807
665 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
667 select ARM64_WORKAROUND_REPEAT_TLBI
669 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
671 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
672 address for a cacheable mapping of a location is being
673 accessed by a core while another core is remapping the virtual
674 address to a new physical page using the recommended
675 break-before-make sequence, then under very rare circumstances
676 TLBI+DSB completes before a read using the translation being
677 invalidated has been observed by other observers. The
678 workaround repeats the TLBI+DSB operation.
680 config ARM64_ERRATUM_1463225
681 bool "Cortex-A76: Software Step might prevent interrupt recognition"
684 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
686 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
687 of a system call instruction (SVC) can prevent recognition of
688 subsequent interrupts when software stepping is disabled in the
689 exception handler of the system call and either kernel debugging
690 is enabled or VHE is in use.
692 Work around the erratum by triggering a dummy step exception
693 when handling a system call from a task that is being stepped
694 in a VHE configuration of the kernel.
698 config ARM64_ERRATUM_1542419
699 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
702 This option adds a workaround for ARM Neoverse-N1 erratum
705 Affected Neoverse-N1 cores could execute a stale instruction when
706 modified by another CPU. The workaround depends on a firmware
709 Workaround the issue by hiding the DIC feature from EL0. This
710 forces user-space to perform cache maintenance.
714 config ARM64_ERRATUM_1508412
715 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
718 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
720 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
721 of a store-exclusive or read of PAR_EL1 and a load with device or
722 non-cacheable memory attributes. The workaround depends on a firmware
725 KVM guests must also have the workaround implemented or they can
728 Work around the issue by inserting DMB SY barriers around PAR_EL1
729 register reads and warning KVM users. The DMB barrier is sufficient
730 to prevent a speculative PAR_EL1 read.
734 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
737 config ARM64_ERRATUM_2051678
738 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
741 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
742 Affected Cortex-A510 might not respect the ordering rules for
743 hardware update of the page table's dirty bit. The workaround
744 is to not enable the feature on affected CPUs.
748 config ARM64_ERRATUM_2077057
749 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
752 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
753 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
754 expected, but a Pointer Authentication trap is taken instead. The
755 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow
756 EL1 to cause a return to EL2 with a guest controlled ELR_EL2.
758 This can only happen when EL2 is stepping EL1.
760 When these conditions occur, the SPSR_EL2 value is unchanged from the
761 previous guest entry, and can be restored from the in-memory copy.
765 config ARM64_ERRATUM_2658417
766 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
769 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
770 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
771 BFMMLA or VMMLA instructions in rare circumstances when a pair of
772 A510 CPUs are using shared neon hardware. As the sharing is not
773 discoverable by the kernel, hide the BF16 HWCAP to indicate that
774 user-space should not be using these instructions.
778 config ARM64_ERRATUM_2119858
779 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
781 depends on CORESIGHT_TRBE
782 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
784 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
786 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
787 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
788 the event of a WRAP event.
790 Work around the issue by always making sure we move the TRBPTR_EL1 by
791 256 bytes before enabling the buffer and filling the first 256 bytes of
792 the buffer with ETM ignore packets upon disabling.
796 config ARM64_ERRATUM_2139208
797 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
799 depends on CORESIGHT_TRBE
800 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
802 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
804 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
805 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
806 the event of a WRAP event.
808 Work around the issue by always making sure we move the TRBPTR_EL1 by
809 256 bytes before enabling the buffer and filling the first 256 bytes of
810 the buffer with ETM ignore packets upon disabling.
814 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
817 config ARM64_ERRATUM_2054223
818 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
820 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
822 Enable workaround for ARM Cortex-A710 erratum 2054223
824 Affected cores may fail to flush the trace data on a TSB instruction, when
825 the PE is in trace prohibited state. This will cause losing a few bytes
828 Workaround is to issue two TSB consecutively on affected cores.
832 config ARM64_ERRATUM_2067961
833 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
835 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
837 Enable workaround for ARM Neoverse-N2 erratum 2067961
839 Affected cores may fail to flush the trace data on a TSB instruction, when
840 the PE is in trace prohibited state. This will cause losing a few bytes
843 Workaround is to issue two TSB consecutively on affected cores.
847 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
850 config ARM64_ERRATUM_2253138
851 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
852 depends on CORESIGHT_TRBE
854 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
856 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
858 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
859 for TRBE. Under some conditions, the TRBE might generate a write to the next
860 virtually addressed page following the last page of the TRBE address space
861 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
863 Work around this in the driver by always making sure that there is a
864 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
868 config ARM64_ERRATUM_2224489
869 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
870 depends on CORESIGHT_TRBE
872 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
874 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
876 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
877 for TRBE. Under some conditions, the TRBE might generate a write to the next
878 virtually addressed page following the last page of the TRBE address space
879 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
881 Work around this in the driver by always making sure that there is a
882 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
886 config ARM64_ERRATUM_2441009
887 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
889 select ARM64_WORKAROUND_REPEAT_TLBI
891 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
893 Under very rare circumstances, affected Cortex-A510 CPUs
894 may not handle a race between a break-before-make sequence on one
895 CPU, and another CPU accessing the same page. This could allow a
896 store to a page that has been unmapped.
898 Work around this by adding the affected CPUs to the list that needs
899 TLB sequences to be done twice.
903 config ARM64_ERRATUM_2064142
904 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
905 depends on CORESIGHT_TRBE
908 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
910 Affected Cortex-A510 core might fail to write into system registers after the
911 TRBE has been disabled. Under some conditions after the TRBE has been disabled
912 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,
913 and TRBTRG_EL1 will be ignored and will not be effected.
915 Work around this in the driver by executing TSB CSYNC and DSB after collection
916 is stopped and before performing a system register write to one of the affected
921 config ARM64_ERRATUM_2038923
922 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
923 depends on CORESIGHT_TRBE
926 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
928 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
929 prohibited within the CPU. As a result, the trace buffer or trace buffer state
930 might be corrupted. This happens after TRBE buffer has been enabled by setting
931 TRBLIMITR_EL1.E, followed by just a single context synchronization event before
932 execution changes from a context, in which trace is prohibited to one where it
933 isn't, or vice versa. In these mentioned conditions, the view of whether trace
934 is prohibited is inconsistent between parts of the CPU, and the trace buffer or
935 the trace buffer state might be corrupted.
937 Work around this in the driver by preventing an inconsistent view of whether the
938 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
939 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
940 two ISB instructions if no ERET is to take place.
944 config ARM64_ERRATUM_1902691
945 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
946 depends on CORESIGHT_TRBE
949 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
951 Affected Cortex-A510 core might cause trace data corruption, when being written
952 into the memory. Effectively TRBE is broken and hence cannot be used to capture
955 Work around this problem in the driver by just preventing TRBE initialization on
956 affected cpus. The firmware must have disabled the access to TRBE for the kernel
957 on such implementations. This will cover the kernel for any firmware that doesn't
962 config ARM64_ERRATUM_2457168
963 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
964 depends on ARM64_AMU_EXTN
967 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
969 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate
970 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
971 incorrectly giving a significantly higher output value.
973 Work around this problem by returning 0 when reading the affected counter in
974 key locations that results in disabling all users of this counter. This effect
975 is the same to firmware disabling affected counters.
979 config CAVIUM_ERRATUM_22375
980 bool "Cavium erratum 22375, 24313"
983 Enable workaround for errata 22375 and 24313.
985 This implements two gicv3-its errata workarounds for ThunderX. Both
986 with a small impact affecting only ITS table allocation.
988 erratum 22375: only alloc 8MB table size
989 erratum 24313: ignore memory access type
991 The fixes are in ITS initialization and basically ignore memory access
992 type and table size provided by the TYPER and BASER registers.
996 config CAVIUM_ERRATUM_23144
997 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
1001 ITS SYNC command hang for cross node io and collections/cpu mapping.
1005 config CAVIUM_ERRATUM_23154
1006 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"
1009 The ThunderX GICv3 implementation requires a modified version for
1010 reading the IAR status to ensure data synchronization
1011 (access to icc_iar1_el1 is not sync'ed before and after).
1013 It also suffers from erratum 38545 (also present on Marvell's
1014 OcteonTX and OcteonTX2), resulting in deactivated interrupts being
1015 spuriously presented to the CPU interface.
1019 config CAVIUM_ERRATUM_27456
1020 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
1023 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
1024 instructions may cause the icache to become corrupted if it
1025 contains data for a non-current ASID. The fix is to
1026 invalidate the icache when changing the mm context.
1030 config CAVIUM_ERRATUM_30115
1031 bool "Cavium erratum 30115: Guest may disable interrupts in host"
1034 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
1035 1.2, and T83 Pass 1.0, KVM guest execution may disable
1036 interrupts in host. Trapping both GICv3 group-0 and group-1
1037 accesses sidesteps the issue.
1041 config CAVIUM_TX2_ERRATUM_219
1042 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
1045 On Cavium ThunderX2, a load, store or prefetch instruction between a
1046 TTBR update and the corresponding context synchronizing operation can
1047 cause a spurious Data Abort to be delivered to any hardware thread in
1050 Work around the issue by avoiding the problematic code sequence and
1051 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
1052 trap handler performs the corresponding register access, skips the
1053 instruction and ensures context synchronization by virtue of the
1058 config FUJITSU_ERRATUM_010001
1059 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1062 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1063 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1064 accesses may cause undefined fault (Data abort, DFSC=0b111111).
1065 This fault occurs under a specific hardware condition when a
1066 load/store instruction performs an address translation using:
1067 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1068 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1069 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1070 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1072 The workaround is to ensure these bits are clear in TCR_ELx.
1073 The workaround only affects the Fujitsu-A64FX.
1077 config HISILICON_ERRATUM_161600802
1078 bool "Hip07 161600802: Erroneous redistributor VLPI base"
1081 The HiSilicon Hip07 SoC uses the wrong redistributor base
1082 when issued ITS commands such as VMOVP and VMAPP, and requires
1083 a 128kB offset to be applied to the target address in this commands.
1087 config QCOM_FALKOR_ERRATUM_1003
1088 bool "Falkor E1003: Incorrect translation due to ASID change"
1091 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
1092 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
1093 in TTBR1_EL1, this situation only occurs in the entry trampoline and
1094 then only for entries in the walk cache, since the leaf translation
1095 is unchanged. Work around the erratum by invalidating the walk cache
1096 entries for the trampoline before entering the kernel proper.
1098 config QCOM_FALKOR_ERRATUM_1009
1099 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
1101 select ARM64_WORKAROUND_REPEAT_TLBI
1103 On Falkor v1, the CPU may prematurely complete a DSB following a
1104 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
1105 one more time to fix the issue.
1109 config QCOM_QDF2400_ERRATUM_0065
1110 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
1113 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
1114 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
1115 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
1119 config QCOM_FALKOR_ERRATUM_E1041
1120 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
1123 Falkor CPU may speculatively fetch instructions from an improper
1124 memory location when MMU translation is changed from SCTLR_ELn[M]=1
1125 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
1129 config NVIDIA_CARMEL_CNP_ERRATUM
1130 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
1133 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1134 invalidate shared TLB entries installed by a different core, as it would
1135 on standard ARM cores.
1139 config SOCIONEXT_SYNQUACER_PREITS
1140 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1143 Socionext Synquacer SoCs implement a separate h/w block to generate
1144 MSI doorbell writes with non-zero values for the device ID.
1148 endmenu # "ARM errata workarounds via the alternatives framework"
1152 default ARM64_4K_PAGES
1154 Page size (translation granule) configuration.
1156 config ARM64_4K_PAGES
1159 This feature enables 4KB pages support.
1161 config ARM64_16K_PAGES
1164 The system will use 16KB pages support. AArch32 emulation
1165 requires applications compiled with 16K (or a multiple of 16K)
1168 config ARM64_64K_PAGES
1171 This feature enables 64KB pages support (4KB by default)
1172 allowing only two levels of page tables and faster TLB
1173 look-up. AArch32 emulation requires applications compiled
1174 with 64K aligned segments.
1179 prompt "Virtual address space size"
1180 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
1181 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
1182 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
1184 Allows choosing one of multiple possible virtual address
1185 space sizes. The level of translation table is determined by
1186 a combination of page size and virtual address space size.
1188 config ARM64_VA_BITS_36
1189 bool "36-bit" if EXPERT
1190 depends on ARM64_16K_PAGES
1192 config ARM64_VA_BITS_39
1194 depends on ARM64_4K_PAGES
1196 config ARM64_VA_BITS_42
1198 depends on ARM64_64K_PAGES
1200 config ARM64_VA_BITS_47
1202 depends on ARM64_16K_PAGES
1204 config ARM64_VA_BITS_48
1207 config ARM64_VA_BITS_52
1209 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
1211 Enable 52-bit virtual addressing for userspace when explicitly
1212 requested via a hint to mmap(). The kernel will also use 52-bit
1213 virtual addresses for its own mappings (provided HW support for
1214 this feature is available, otherwise it reverts to 48-bit).
1216 NOTE: Enabling 52-bit virtual addressing in conjunction with
1217 ARMv8.3 Pointer Authentication will result in the PAC being
1218 reduced from 7 bits to 3 bits, which may have a significant
1219 impact on its susceptibility to brute-force attacks.
1221 If unsure, select 48-bit virtual addressing instead.
1225 config ARM64_FORCE_52BIT
1226 bool "Force 52-bit virtual addresses for userspace"
1227 depends on ARM64_VA_BITS_52 && EXPERT
1229 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1230 to maintain compatibility with older software by providing 48-bit VAs
1231 unless a hint is supplied to mmap.
1233 This configuration option disables the 48-bit compatibility logic, and
1234 forces all userspace addresses to be 52-bit on HW that supports it. One
1235 should only enable this configuration option for stress testing userspace
1236 memory management code. If unsure say N here.
1238 config ARM64_VA_BITS
1240 default 36 if ARM64_VA_BITS_36
1241 default 39 if ARM64_VA_BITS_39
1242 default 42 if ARM64_VA_BITS_42
1243 default 47 if ARM64_VA_BITS_47
1244 default 48 if ARM64_VA_BITS_48
1245 default 52 if ARM64_VA_BITS_52
1248 prompt "Physical address space size"
1249 default ARM64_PA_BITS_48
1251 Choose the maximum physical address range that the kernel will
1254 config ARM64_PA_BITS_48
1257 config ARM64_PA_BITS_52
1258 bool "52-bit (ARMv8.2)"
1259 depends on ARM64_64K_PAGES
1260 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1262 Enable support for a 52-bit physical address space, introduced as
1263 part of the ARMv8.2-LPA extension.
1265 With this enabled, the kernel will also continue to work on CPUs that
1266 do not support ARMv8.2-LPA, but with some added memory overhead (and
1267 minor performance overhead).
1271 config ARM64_PA_BITS
1273 default 48 if ARM64_PA_BITS_48
1274 default 52 if ARM64_PA_BITS_52
1278 default CPU_LITTLE_ENDIAN
1280 Select the endianness of data accesses performed by the CPU. Userspace
1281 applications will need to be compiled and linked for the endianness
1282 that is selected here.
1284 config CPU_BIG_ENDIAN
1285 bool "Build big-endian kernel"
1286 depends on !LD_IS_LLD || LLD_VERSION >= 130000
1288 Say Y if you plan on running a kernel with a big-endian userspace.
1290 config CPU_LITTLE_ENDIAN
1291 bool "Build little-endian kernel"
1293 Say Y if you plan on running a kernel with a little-endian userspace.
1294 This is usually the case for distributions targeting arm64.
1299 bool "Multi-core scheduler support"
1301 Multi-core scheduler support improves the CPU scheduler's decision
1302 making when dealing with multi-core CPU chips at a cost of slightly
1303 increased overhead in some places. If unsure say N here.
1305 config SCHED_CLUSTER
1306 bool "Cluster scheduler support"
1308 Cluster scheduler support improves the CPU scheduler's decision
1309 making when dealing with machines that have clusters of CPUs.
1310 Cluster usually means a couple of CPUs which are placed closely
1311 by sharing mid-level caches, last-level cache tags or internal
1315 bool "SMT scheduler support"
1317 Improves the CPU scheduler's decision making when dealing with
1318 MultiThreading at a cost of slightly increased overhead in some
1319 places. If unsure say N here.
1322 int "Maximum number of CPUs (2-4096)"
1327 bool "Support for hot-pluggable CPUs"
1328 select GENERIC_IRQ_MIGRATION
1330 Say Y here to experiment with turning CPUs off and on. CPUs
1331 can be controlled through /sys/devices/system/cpu.
1333 # Common NUMA Features
1335 bool "NUMA Memory Allocation and Scheduler Support"
1336 select GENERIC_ARCH_NUMA
1337 select ACPI_NUMA if ACPI
1339 select HAVE_SETUP_PER_CPU_AREA
1340 select NEED_PER_CPU_EMBED_FIRST_CHUNK
1341 select NEED_PER_CPU_PAGE_FIRST_CHUNK
1342 select USE_PERCPU_NUMA_NODE_ID
1344 Enable NUMA (Non-Uniform Memory Access) support.
1346 The kernel will try to allocate memory used by a CPU on the
1347 local memory of the CPU and add some more
1348 NUMA awareness to the kernel.
1351 int "Maximum NUMA Nodes (as a power of 2)"
1356 Specify the maximum number of NUMA Nodes available on the target
1357 system. Increases memory reserved to accommodate various tables.
1359 source "kernel/Kconfig.hz"
1361 config ARCH_SPARSEMEM_ENABLE
1363 select SPARSEMEM_VMEMMAP_ENABLE
1364 select SPARSEMEM_VMEMMAP
1366 config HW_PERF_EVENTS
1370 # Supported by clang >= 7.0 or GCC >= 12.0.0
1371 config CC_HAVE_SHADOW_CALL_STACK
1372 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1375 bool "Enable paravirtualization code"
1377 This changes the kernel so it can modify itself when it is run
1378 under a hypervisor, potentially improving performance significantly
1379 over full virtualization.
1381 config PARAVIRT_TIME_ACCOUNTING
1382 bool "Paravirtual steal time accounting"
1385 Select this option to enable fine granularity task steal time
1386 accounting. Time spent executing other tasks in parallel with
1387 the current vCPU is discounted from the vCPU power. To account for
1388 that, there can be a small performance impact.
1390 If in doubt, say N here.
1393 depends on PM_SLEEP_SMP
1395 bool "kexec system call"
1397 kexec is a system call that implements the ability to shutdown your
1398 current kernel, and to start another kernel. It is like a reboot
1399 but it is independent of the system firmware. And like a reboot
1400 you can start any kernel with it, not just Linux.
1403 bool "kexec file based system call"
1405 select HAVE_IMA_KEXEC if IMA
1407 This is new version of kexec system call. This system call is
1408 file based and takes file descriptors as system call argument
1409 for kernel and initramfs as opposed to list of segments as
1410 accepted by previous system call.
1413 bool "Verify kernel signature during kexec_file_load() syscall"
1414 depends on KEXEC_FILE
1416 Select this option to verify a signature with loaded kernel
1417 image. If configured, any attempt of loading a image without
1418 valid signature will fail.
1420 In addition to that option, you need to enable signature
1421 verification for the corresponding kernel image type being
1422 loaded in order for this to work.
1424 config KEXEC_IMAGE_VERIFY_SIG
1425 bool "Enable Image signature verification support"
1427 depends on KEXEC_SIG
1428 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1430 Enable Image signature verification support.
1432 comment "Support for PE file signature verification disabled"
1433 depends on KEXEC_SIG
1434 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1437 bool "Build kdump crash kernel"
1439 Generate crash dump after being started by kexec. This should
1440 be normally only set in special crash dump kernels which are
1441 loaded in the main kernel with kexec-tools into a specially
1442 reserved region and then later executed after a crash by
1445 For more details see Documentation/admin-guide/kdump/kdump.rst
1449 depends on HIBERNATION || KEXEC_CORE
1456 bool "Xen guest support on ARM64"
1457 depends on ARM64 && OF
1461 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1463 # include/linux/mmzone.h requires the following to be true:
1465 # MAX_ORDER - 1 + PAGE_SHIFT <= SECTION_SIZE_BITS
1467 # so the maximum value of MAX_ORDER is SECTION_SIZE_BITS + 1 - PAGE_SHIFT:
1469 # | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_ORDER | default MAX_ORDER |
1470 # ----+-------------------+--------------+-----------------+--------------------+
1471 # 4K | 27 | 12 | 16 | 11 |
1472 # 16K | 27 | 14 | 14 | 12 |
1473 # 64K | 29 | 16 | 14 | 14 |
1474 config ARCH_FORCE_MAX_ORDER
1475 int "Maximum zone order" if ARM64_4K_PAGES || ARM64_16K_PAGES
1476 default "14" if ARM64_64K_PAGES
1477 range 12 14 if ARM64_16K_PAGES
1478 default "12" if ARM64_16K_PAGES
1479 range 11 16 if ARM64_4K_PAGES
1482 The kernel memory allocator divides physically contiguous memory
1483 blocks into "zones", where each zone is a power of two number of
1484 pages. This option selects the largest power of two that the kernel
1485 keeps in the memory allocator. If you need to allocate very large
1486 blocks of physically contiguous memory, then you may need to
1487 increase this value.
1489 This config option is actually maximum order plus one. For example,
1490 a value of 11 means that the largest free memory block is 2^10 pages.
1492 We make sure that we can allocate up to a HugePage size for each configuration.
1494 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1496 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1497 4M allocations matching the default size used by generic code.
1499 config UNMAP_KERNEL_AT_EL0
1500 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1503 Speculation attacks against some high-performance processors can
1504 be used to bypass MMU permission checks and leak kernel data to
1505 userspace. This can be defended against by unmapping the kernel
1506 when running in userspace, mapping it back in on exception entry
1507 via a trampoline page in the vector table.
1511 config MITIGATE_SPECTRE_BRANCH_HISTORY
1512 bool "Mitigate Spectre style attacks against branch history" if EXPERT
1515 Speculation attacks against some high-performance processors can
1516 make use of branch history to influence future speculation.
1517 When taking an exception from user-space, a sequence of branches
1518 or a firmware call overwrites the branch history.
1520 config RODATA_FULL_DEFAULT_ENABLED
1521 bool "Apply r/o permissions of VM areas also to their linear aliases"
1524 Apply read-only attributes of VM areas to the linear alias of
1525 the backing pages as well. This prevents code or read-only data
1526 from being modified (inadvertently or intentionally) via another
1527 mapping of the same memory page. This additional enhancement can
1528 be turned off at runtime by passing rodata=[off|on] (and turned on
1529 with rodata=full if this option is set to 'n')
1531 This requires the linear region to be mapped down to pages,
1532 which may adversely affect performance in some cases.
1534 config ARM64_SW_TTBR0_PAN
1535 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1537 Enabling this option prevents the kernel from accessing
1538 user-space memory directly by pointing TTBR0_EL1 to a reserved
1539 zeroed area and reserved ASID. The user access routines
1540 restore the valid TTBR0_EL1 temporarily.
1542 config ARM64_TAGGED_ADDR_ABI
1543 bool "Enable the tagged user addresses syscall ABI"
1546 When this option is enabled, user applications can opt in to a
1547 relaxed ABI via prctl() allowing tagged addresses to be passed
1548 to system calls as pointer arguments. For details, see
1549 Documentation/arm64/tagged-address-abi.rst.
1552 bool "Kernel support for 32-bit EL0"
1553 depends on ARM64_4K_PAGES || EXPERT
1555 select OLD_SIGSUSPEND3
1556 select COMPAT_OLD_SIGACTION
1558 This option enables support for a 32-bit EL0 running under a 64-bit
1559 kernel at EL1. AArch32-specific components such as system calls,
1560 the user helper functions, VFP support and the ptrace interface are
1561 handled appropriately by the kernel.
1563 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1564 that you will only be able to execute AArch32 binaries that were compiled
1565 with page size aligned segments.
1567 If you want to execute 32-bit userspace applications, say Y.
1571 config KUSER_HELPERS
1572 bool "Enable kuser helpers page for 32-bit applications"
1575 Warning: disabling this option may break 32-bit user programs.
1577 Provide kuser helpers to compat tasks. The kernel provides
1578 helper code to userspace in read only form at a fixed location
1579 to allow userspace to be independent of the CPU type fitted to
1580 the system. This permits binaries to be run on ARMv4 through
1581 to ARMv8 without modification.
1583 See Documentation/arm/kernel_user_helpers.rst for details.
1585 However, the fixed address nature of these helpers can be used
1586 by ROP (return orientated programming) authors when creating
1589 If all of the binaries and libraries which run on your platform
1590 are built specifically for your platform, and make no use of
1591 these helpers, then you can turn this option off to hinder
1592 such exploits. However, in that case, if a binary or library
1593 relying on those helpers is run, it will not function correctly.
1595 Say N here only if you are absolutely certain that you do not
1596 need these helpers; otherwise, the safe option is to say Y.
1599 bool "Enable vDSO for 32-bit applications"
1600 depends on !CPU_BIG_ENDIAN
1601 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1602 select GENERIC_COMPAT_VDSO
1605 Place in the process address space of 32-bit applications an
1606 ELF shared object providing fast implementations of gettimeofday
1609 You must have a 32-bit build of glibc 2.22 or later for programs
1610 to seamlessly take advantage of this.
1612 config THUMB2_COMPAT_VDSO
1613 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1614 depends on COMPAT_VDSO
1617 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1618 otherwise with '-marm'.
1620 config COMPAT_ALIGNMENT_FIXUPS
1621 bool "Fix up misaligned multi-word loads and stores in user space"
1623 menuconfig ARMV8_DEPRECATED
1624 bool "Emulate deprecated/obsolete ARMv8 instructions"
1627 Legacy software support may require certain instructions
1628 that have been deprecated or obsoleted in the architecture.
1630 Enable this config to enable selective emulation of these
1637 config SWP_EMULATION
1638 bool "Emulate SWP/SWPB instructions"
1640 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1641 they are always undefined. Say Y here to enable software
1642 emulation of these instructions for userspace using LDXR/STXR.
1643 This feature can be controlled at runtime with the abi.swp
1644 sysctl which is disabled by default.
1646 In some older versions of glibc [<=2.8] SWP is used during futex
1647 trylock() operations with the assumption that the code will not
1648 be preempted. This invalid assumption may be more likely to fail
1649 with SWP emulation enabled, leading to deadlock of the user
1652 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1653 on an external transaction monitoring block called a global
1654 monitor to maintain update atomicity. If your system does not
1655 implement a global monitor, this option can cause programs that
1656 perform SWP operations to uncached memory to deadlock.
1660 config CP15_BARRIER_EMULATION
1661 bool "Emulate CP15 Barrier instructions"
1663 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1664 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1665 strongly recommended to use the ISB, DSB, and DMB
1666 instructions instead.
1668 Say Y here to enable software emulation of these
1669 instructions for AArch32 userspace code. When this option is
1670 enabled, CP15 barrier usage is traced which can help
1671 identify software that needs updating. This feature can be
1672 controlled at runtime with the abi.cp15_barrier sysctl.
1676 config SETEND_EMULATION
1677 bool "Emulate SETEND instruction"
1679 The SETEND instruction alters the data-endianness of the
1680 AArch32 EL0, and is deprecated in ARMv8.
1682 Say Y here to enable software emulation of the instruction
1683 for AArch32 userspace code. This feature can be controlled
1684 at runtime with the abi.setend sysctl.
1686 Note: All the cpus on the system must have mixed endian support at EL0
1687 for this feature to be enabled. If a new CPU - which doesn't support mixed
1688 endian - is hotplugged in after this feature has been enabled, there could
1689 be unexpected results in the applications.
1692 endif # ARMV8_DEPRECATED
1696 menu "ARMv8.1 architectural features"
1698 config ARM64_HW_AFDBM
1699 bool "Support for hardware updates of the Access and Dirty page flags"
1702 The ARMv8.1 architecture extensions introduce support for
1703 hardware updates of the access and dirty information in page
1704 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1705 capable processors, accesses to pages with PTE_AF cleared will
1706 set this bit instead of raising an access flag fault.
1707 Similarly, writes to read-only pages with the DBM bit set will
1708 clear the read-only bit (AP[2]) instead of raising a
1711 Kernels built with this configuration option enabled continue
1712 to work on pre-ARMv8.1 hardware and the performance impact is
1713 minimal. If unsure, say Y.
1716 bool "Enable support for Privileged Access Never (PAN)"
1719 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1720 prevents the kernel or hypervisor from accessing user-space (EL0)
1723 Choosing this option will cause any unprotected (not using
1724 copy_to_user et al) memory access to fail with a permission fault.
1726 The feature is detected at runtime, and will remain as a 'nop'
1727 instruction if the cpu does not implement the feature.
1730 def_bool $(as-instr,.arch_extension rcpc)
1732 config AS_HAS_LSE_ATOMICS
1733 def_bool $(as-instr,.arch_extension lse)
1735 config ARM64_LSE_ATOMICS
1737 default ARM64_USE_LSE_ATOMICS
1738 depends on AS_HAS_LSE_ATOMICS
1740 config ARM64_USE_LSE_ATOMICS
1741 bool "Atomic instructions"
1744 As part of the Large System Extensions, ARMv8.1 introduces new
1745 atomic instructions that are designed specifically to scale in
1748 Say Y here to make use of these instructions for the in-kernel
1749 atomic routines. This incurs a small overhead on CPUs that do
1750 not support these instructions and requires the kernel to be
1751 built with binutils >= 2.25 in order for the new instructions
1754 endmenu # "ARMv8.1 architectural features"
1756 menu "ARMv8.2 architectural features"
1758 config AS_HAS_ARMV8_2
1759 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1762 def_bool $(as-instr,.arch armv8.2-a+sha3)
1765 bool "Enable support for persistent memory"
1766 select ARCH_HAS_PMEM_API
1767 select ARCH_HAS_UACCESS_FLUSHCACHE
1769 Say Y to enable support for the persistent memory API based on the
1770 ARMv8.2 DCPoP feature.
1772 The feature is detected at runtime, and the kernel will use DC CVAC
1773 operations if DC CVAP is not supported (following the behaviour of
1774 DC CVAP itself if the system does not define a point of persistence).
1776 config ARM64_RAS_EXTN
1777 bool "Enable support for RAS CPU Extensions"
1780 CPUs that support the Reliability, Availability and Serviceability
1781 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1782 errors, classify them and report them to software.
1784 On CPUs with these extensions system software can use additional
1785 barriers to determine if faults are pending and read the
1786 classification from a new set of registers.
1788 Selecting this feature will allow the kernel to use these barriers
1789 and access the new registers if the system supports the extension.
1790 Platform RAS features may additionally depend on firmware support.
1793 bool "Enable support for Common Not Private (CNP) translations"
1795 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1797 Common Not Private (CNP) allows translation table entries to
1798 be shared between different PEs in the same inner shareable
1799 domain, so the hardware can use this fact to optimise the
1800 caching of such entries in the TLB.
1802 Selecting this option allows the CNP feature to be detected
1803 at runtime, and does not affect PEs that do not implement
1806 endmenu # "ARMv8.2 architectural features"
1808 menu "ARMv8.3 architectural features"
1810 config ARM64_PTR_AUTH
1811 bool "Enable support for pointer authentication"
1814 Pointer authentication (part of the ARMv8.3 Extensions) provides
1815 instructions for signing and authenticating pointers against secret
1816 keys, which can be used to mitigate Return Oriented Programming (ROP)
1819 This option enables these instructions at EL0 (i.e. for userspace).
1820 Choosing this option will cause the kernel to initialise secret keys
1821 for each process at exec() time, with these keys being
1822 context-switched along with the process.
1824 The feature is detected at runtime. If the feature is not present in
1825 hardware it will not be advertised to userspace/KVM guest nor will it
1828 If the feature is present on the boot CPU but not on a late CPU, then
1829 the late CPU will be parked. Also, if the boot CPU does not have
1830 address auth and the late CPU has then the late CPU will still boot
1831 but with the feature disabled. On such a system, this option should
1834 config ARM64_PTR_AUTH_KERNEL
1835 bool "Use pointer authentication for kernel"
1837 depends on ARM64_PTR_AUTH
1838 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3
1839 # Modern compilers insert a .note.gnu.property section note for PAC
1840 # which is only understood by binutils starting with version 2.33.1.
1841 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1842 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1843 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
1845 If the compiler supports the -mbranch-protection or
1846 -msign-return-address flag (e.g. GCC 7 or later), then this option
1847 will cause the kernel itself to be compiled with return address
1848 protection. In this case, and if the target hardware is known to
1849 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1850 disabled with minimal loss of protection.
1852 This feature works with FUNCTION_GRAPH_TRACER option only if
1853 DYNAMIC_FTRACE_WITH_ARGS is enabled.
1855 config CC_HAS_BRANCH_PROT_PAC_RET
1856 # GCC 9 or later, clang 8 or later
1857 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1859 config CC_HAS_SIGN_RETURN_ADDRESS
1861 def_bool $(cc-option,-msign-return-address=all)
1863 config AS_HAS_ARMV8_3
1864 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1866 config AS_HAS_CFI_NEGATE_RA_STATE
1867 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1869 endmenu # "ARMv8.3 architectural features"
1871 menu "ARMv8.4 architectural features"
1873 config ARM64_AMU_EXTN
1874 bool "Enable support for the Activity Monitors Unit CPU extension"
1877 The activity monitors extension is an optional extension introduced
1878 by the ARMv8.4 CPU architecture. This enables support for version 1
1879 of the activity monitors architecture, AMUv1.
1881 To enable the use of this extension on CPUs that implement it, say Y.
1883 Note that for architectural reasons, firmware _must_ implement AMU
1884 support when running on CPUs that present the activity monitors
1885 extension. The required support is present in:
1886 * Version 1.5 and later of the ARM Trusted Firmware
1888 For kernels that have this configuration enabled but boot with broken
1889 firmware, you may need to say N here until the firmware is fixed.
1890 Otherwise you may experience firmware panics or lockups when
1891 accessing the counter registers. Even if you are not observing these
1892 symptoms, the values returned by the register reads might not
1893 correctly reflect reality. Most commonly, the value read will be 0,
1894 indicating that the counter is not enabled.
1896 config AS_HAS_ARMV8_4
1897 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1899 config ARM64_TLB_RANGE
1900 bool "Enable support for tlbi range feature"
1902 depends on AS_HAS_ARMV8_4
1904 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1905 range of input addresses.
1907 The feature introduces new assembly instructions, and they were
1908 support when binutils >= 2.30.
1910 endmenu # "ARMv8.4 architectural features"
1912 menu "ARMv8.5 architectural features"
1914 config AS_HAS_ARMV8_5
1915 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1918 bool "Branch Target Identification support"
1921 Branch Target Identification (part of the ARMv8.5 Extensions)
1922 provides a mechanism to limit the set of locations to which computed
1923 branch instructions such as BR or BLR can jump.
1925 To make use of BTI on CPUs that support it, say Y.
1927 BTI is intended to provide complementary protection to other control
1928 flow integrity protection mechanisms, such as the Pointer
1929 authentication mechanism provided as part of the ARMv8.3 Extensions.
1930 For this reason, it does not make sense to enable this option without
1931 also enabling support for pointer authentication. Thus, when
1932 enabling this option you should also select ARM64_PTR_AUTH=y.
1934 Userspace binaries must also be specifically compiled to make use of
1935 this mechanism. If you say N here or the hardware does not support
1936 BTI, such binaries can still run, but you get no additional
1937 enforcement of branch destinations.
1939 config ARM64_BTI_KERNEL
1940 bool "Use Branch Target Identification for kernel"
1942 depends on ARM64_BTI
1943 depends on ARM64_PTR_AUTH_KERNEL
1944 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1945 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1946 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1947 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671
1948 depends on !CC_IS_GCC
1949 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1950 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
1951 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
1953 Build the kernel with Branch Target Identification annotations
1954 and enable enforcement of this for kernel code. When this option
1955 is enabled and the system supports BTI all kernel code including
1956 modular code must have BTI enabled.
1958 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1959 # GCC 9 or later, clang 8 or later
1960 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1963 bool "Enable support for E0PD"
1966 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1967 that EL0 accesses made via TTBR1 always fault in constant time,
1968 providing similar benefits to KASLR as those provided by KPTI, but
1969 with lower overhead and without disrupting legitimate access to
1970 kernel memory such as SPE.
1972 This option enables E0PD for TTBR1 where available.
1974 config ARM64_AS_HAS_MTE
1975 # Initial support for MTE went in binutils 2.32.0, checked with
1976 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1977 # as a late addition to the final architecture spec (LDGM/STGM)
1978 # is only supported in the newer 2.32.x and 2.33 binutils
1979 # versions, hence the extra "stgm" instruction check below.
1980 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1983 bool "Memory Tagging Extension support"
1985 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1986 depends on AS_HAS_ARMV8_5
1987 depends on AS_HAS_LSE_ATOMICS
1988 # Required for tag checking in the uaccess routines
1989 depends on ARM64_PAN
1990 select ARCH_HAS_SUBPAGE_FAULTS
1991 select ARCH_USES_HIGH_VMA_FLAGS
1992 select ARCH_USES_PG_ARCH_X
1994 Memory Tagging (part of the ARMv8.5 Extensions) provides
1995 architectural support for run-time, always-on detection of
1996 various classes of memory error to aid with software debugging
1997 to eliminate vulnerabilities arising from memory-unsafe
2000 This option enables the support for the Memory Tagging
2001 Extension at EL0 (i.e. for userspace).
2003 Selecting this option allows the feature to be detected at
2004 runtime. Any secondary CPU not implementing this feature will
2005 not be allowed a late bring-up.
2007 Userspace binaries that want to use this feature must
2008 explicitly opt in. The mechanism for the userspace is
2011 Documentation/arm64/memory-tagging-extension.rst.
2013 endmenu # "ARMv8.5 architectural features"
2015 menu "ARMv8.7 architectural features"
2018 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
2020 depends on ARM64_PAN
2022 Enhanced Privileged Access Never (EPAN) allows Privileged
2023 Access Never to be used with Execute-only mappings.
2025 The feature is detected at runtime, and will remain disabled
2026 if the cpu does not implement the feature.
2027 endmenu # "ARMv8.7 architectural features"
2030 bool "ARM Scalable Vector Extension support"
2033 The Scalable Vector Extension (SVE) is an extension to the AArch64
2034 execution state which complements and extends the SIMD functionality
2035 of the base architecture to support much larger vectors and to enable
2036 additional vectorisation opportunities.
2038 To enable use of this extension on CPUs that implement it, say Y.
2040 On CPUs that support the SVE2 extensions, this option will enable
2043 Note that for architectural reasons, firmware _must_ implement SVE
2044 support when running on SVE capable hardware. The required support
2047 * version 1.5 and later of the ARM Trusted Firmware
2048 * the AArch64 boot wrapper since commit 5e1261e08abf
2049 ("bootwrapper: SVE: Enable SVE for EL2 and below").
2051 For other firmware implementations, consult the firmware documentation
2054 If you need the kernel to boot on SVE-capable hardware with broken
2055 firmware, you may need to say N here until you get your firmware
2056 fixed. Otherwise, you may experience firmware panics or lockups when
2057 booting the kernel. If unsure and you are not observing these
2058 symptoms, you should assume that it is safe to say Y.
2061 bool "ARM Scalable Matrix Extension support"
2063 depends on ARM64_SVE
2065 The Scalable Matrix Extension (SME) is an extension to the AArch64
2066 execution state which utilises a substantial subset of the SVE
2067 instruction set, together with the addition of new architectural
2068 register state capable of holding two dimensional matrix tiles to
2069 enable various matrix operations.
2071 config ARM64_MODULE_PLTS
2072 bool "Use PLTs to allow module memory to spill over into vmalloc area"
2074 select HAVE_MOD_ARCH_SPECIFIC
2076 Allocate PLTs when loading modules so that jumps and calls whose
2077 targets are too far away for their relative offsets to be encoded
2078 in the instructions themselves can be bounced via veneers in the
2079 module's PLT. This allows modules to be allocated in the generic
2080 vmalloc area after the dedicated module memory area has been
2083 When running with address space randomization (KASLR), the module
2084 region itself may be too far away for ordinary relative jumps and
2085 calls, and so in that case, module PLTs are required and cannot be
2088 Specific errata workaround(s) might also force module PLTs to be
2089 enabled (ARM64_ERRATUM_843419).
2091 config ARM64_PSEUDO_NMI
2092 bool "Support for NMI-like interrupts"
2095 Adds support for mimicking Non-Maskable Interrupts through the use of
2096 GIC interrupt priority. This support requires version 3 or later of
2099 This high priority configuration for interrupts needs to be
2100 explicitly enabled by setting the kernel parameter
2101 "irqchip.gicv3_pseudo_nmi" to 1.
2106 config ARM64_DEBUG_PRIORITY_MASKING
2107 bool "Debug interrupt priority masking"
2109 This adds runtime checks to functions enabling/disabling
2110 interrupts when using priority masking. The additional checks verify
2111 the validity of ICC_PMR_EL1 when calling concerned functions.
2114 endif # ARM64_PSEUDO_NMI
2117 bool "Build a relocatable kernel image" if EXPERT
2118 select ARCH_HAS_RELR
2121 This builds the kernel as a Position Independent Executable (PIE),
2122 which retains all relocation metadata required to relocate the
2123 kernel binary at runtime to a different virtual address than the
2124 address it was linked at.
2125 Since AArch64 uses the RELA relocation format, this requires a
2126 relocation pass at runtime even if the kernel is loaded at the
2127 same address it was linked at.
2129 config RANDOMIZE_BASE
2130 bool "Randomize the address of the kernel image"
2131 select ARM64_MODULE_PLTS if MODULES
2134 Randomizes the virtual address at which the kernel image is
2135 loaded, as a security feature that deters exploit attempts
2136 relying on knowledge of the location of kernel internals.
2138 It is the bootloader's job to provide entropy, by passing a
2139 random u64 value in /chosen/kaslr-seed at kernel entry.
2141 When booting via the UEFI stub, it will invoke the firmware's
2142 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
2143 to the kernel proper. In addition, it will randomise the physical
2144 location of the kernel Image as well.
2148 config RANDOMIZE_MODULE_REGION_FULL
2149 bool "Randomize the module region over a 2 GB range"
2150 depends on RANDOMIZE_BASE
2153 Randomizes the location of the module region inside a 2 GB window
2154 covering the core kernel. This way, it is less likely for modules
2155 to leak information about the location of core kernel data structures
2156 but it does imply that function calls between modules and the core
2157 kernel will need to be resolved via veneers in the module PLT.
2159 When this option is not set, the module region will be randomized over
2160 a limited range that contains the [_stext, _etext] interval of the
2161 core kernel, so branch relocations are almost always in range unless
2162 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this
2163 particular case of region exhaustion, modules might be able to fall
2164 back to a larger 2GB area.
2166 config CC_HAVE_STACKPROTECTOR_SYSREG
2167 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
2169 config STACKPROTECTOR_PER_TASK
2171 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
2173 config UNWIND_PATCH_PAC_INTO_SCS
2174 bool "Enable shadow call stack dynamically using code patching"
2175 # needs Clang with https://reviews.llvm.org/D111780 incorporated
2176 depends on CC_IS_CLANG && CLANG_VERSION >= 150000
2177 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET
2178 depends on SHADOW_CALL_STACK
2179 select UNWIND_TABLES
2182 endmenu # "Kernel Features"
2186 config ARM64_ACPI_PARKING_PROTOCOL
2187 bool "Enable support for the ARM64 ACPI parking protocol"
2190 Enable support for the ARM64 ACPI parking protocol. If disabled
2191 the kernel will not allow booting through the ARM64 ACPI parking
2192 protocol even if the corresponding data is present in the ACPI
2196 string "Default kernel command string"
2199 Provide a set of default command-line options at build time by
2200 entering them here. As a minimum, you should specify the the
2201 root device (e.g. root=/dev/nfs).
2204 prompt "Kernel command line type" if CMDLINE != ""
2205 default CMDLINE_FROM_BOOTLOADER
2207 Choose how the kernel will handle the provided default kernel
2208 command line string.
2210 config CMDLINE_FROM_BOOTLOADER
2211 bool "Use bootloader kernel arguments if available"
2213 Uses the command-line options passed by the boot loader. If
2214 the boot loader doesn't provide any, the default kernel command
2215 string provided in CMDLINE will be used.
2217 config CMDLINE_FORCE
2218 bool "Always use the default kernel command string"
2220 Always use the default kernel command string, even if the boot
2221 loader passes other arguments to the kernel.
2222 This is useful if you cannot or don't want to change the
2223 command-line options your boot loader passes to the kernel.
2231 bool "UEFI runtime support"
2232 depends on OF && !CPU_BIG_ENDIAN
2233 depends on KERNEL_MODE_NEON
2234 select ARCH_SUPPORTS_ACPI
2237 select EFI_PARAMS_FROM_FDT
2238 select EFI_RUNTIME_WRAPPERS
2240 select EFI_GENERIC_STUB
2241 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
2244 This option provides support for runtime services provided
2245 by UEFI firmware (such as non-volatile variables, realtime
2246 clock, and platform reset). A UEFI stub is also provided to
2247 allow the kernel to be booted as an EFI application. This
2248 is only useful on systems that have UEFI firmware.
2251 bool "Enable support for SMBIOS (DMI) tables"
2255 This enables SMBIOS/DMI feature for systems.
2257 This option is only useful on systems that have UEFI firmware.
2258 However, even with this option, the resultant kernel should
2259 continue to boot on existing non-UEFI platforms.
2261 endmenu # "Boot options"
2263 menu "Power management options"
2265 source "kernel/power/Kconfig"
2267 config ARCH_HIBERNATION_POSSIBLE
2271 config ARCH_HIBERNATION_HEADER
2273 depends on HIBERNATION
2275 config ARCH_SUSPEND_POSSIBLE
2278 endmenu # "Power management options"
2280 menu "CPU Power Management"
2282 source "drivers/cpuidle/Kconfig"
2284 source "drivers/cpufreq/Kconfig"
2286 endmenu # "CPU Power Management"
2288 source "drivers/acpi/Kconfig"
2290 source "arch/arm64/kvm/Kconfig"