1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_CLOCKSOURCE_DATA
13 select ARCH_HAS_DEBUG_VIRTUAL
14 select ARCH_HAS_DEVMEM_IS_ALLOWED
15 select ARCH_HAS_DMA_PREP_COHERENT
16 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
17 select ARCH_HAS_FAST_MULTIPLIER
18 select ARCH_HAS_FORTIFY_SOURCE
19 select ARCH_HAS_GCOV_PROFILE_ALL
20 select ARCH_HAS_GIGANTIC_PAGE
22 select ARCH_HAS_KEEPINITRD
23 select ARCH_HAS_MEMBARRIER_SYNC_CORE
24 select ARCH_HAS_PTE_DEVMAP
25 select ARCH_HAS_PTE_SPECIAL
26 select ARCH_HAS_SETUP_DMA_OPS
27 select ARCH_HAS_SET_DIRECT_MAP
28 select ARCH_HAS_SET_MEMORY
29 select ARCH_HAS_STRICT_KERNEL_RWX
30 select ARCH_HAS_STRICT_MODULE_RWX
31 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
32 select ARCH_HAS_SYNC_DMA_FOR_CPU
33 select ARCH_HAS_SYSCALL_WRAPPER
34 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
35 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
36 select ARCH_HAVE_NMI_SAFE_CMPXCHG
37 select ARCH_INLINE_READ_LOCK if !PREEMPT
38 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
39 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
40 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
41 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
42 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
43 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
44 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
45 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
46 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
47 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
48 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
49 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
50 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
51 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
52 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
53 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
54 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
55 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
56 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
57 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
58 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
59 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
60 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
61 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
62 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
63 select ARCH_KEEP_MEMBLOCK
64 select ARCH_USE_CMPXCHG_LOCKREF
65 select ARCH_USE_QUEUED_RWLOCKS
66 select ARCH_USE_QUEUED_SPINLOCKS
67 select ARCH_SUPPORTS_MEMORY_FAILURE
68 select ARCH_SUPPORTS_ATOMIC_RMW
69 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG)
70 select ARCH_SUPPORTS_NUMA_BALANCING
71 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
72 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
73 select ARCH_WANT_FRAME_POINTERS
74 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
75 select ARCH_HAS_UBSAN_SANITIZE_ALL
79 select AUDIT_ARCH_COMPAT_GENERIC
80 select ARM_GIC_V2M if PCI
82 select ARM_GIC_V3_ITS if PCI
84 select BUILDTIME_EXTABLE_SORT
85 select CLONE_BACKWARDS
87 select CPU_PM if (SUSPEND || CPU_IDLE)
89 select DCACHE_WORD_ACCESS
90 select DMA_DIRECT_REMAP
93 select GENERIC_ALLOCATOR
94 select GENERIC_ARCH_TOPOLOGY
95 select GENERIC_CLOCKEVENTS
96 select GENERIC_CLOCKEVENTS_BROADCAST
97 select GENERIC_CPU_AUTOPROBE
98 select GENERIC_CPU_VULNERABILITIES
99 select GENERIC_EARLY_IOREMAP
100 select GENERIC_IDLE_POLL_SETUP
101 select GENERIC_IRQ_MULTI_HANDLER
102 select GENERIC_IRQ_PROBE
103 select GENERIC_IRQ_SHOW
104 select GENERIC_IRQ_SHOW_LEVEL
105 select GENERIC_PCI_IOMAP
106 select GENERIC_SCHED_CLOCK
107 select GENERIC_SMP_IDLE_THREAD
108 select GENERIC_STRNCPY_FROM_USER
109 select GENERIC_STRNLEN_USER
110 select GENERIC_TIME_VSYSCALL
111 select GENERIC_GETTIMEOFDAY
112 select HANDLE_DOMAIN_IRQ
113 select HARDIRQS_SW_RESEND
115 select HAVE_ACPI_APEI if (ACPI && EFI)
116 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
117 select HAVE_ARCH_AUDITSYSCALL
118 select HAVE_ARCH_BITREVERSE
119 select HAVE_ARCH_HUGE_VMAP
120 select HAVE_ARCH_JUMP_LABEL
121 select HAVE_ARCH_JUMP_LABEL_RELATIVE
122 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
123 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
124 select HAVE_ARCH_KGDB
125 select HAVE_ARCH_MMAP_RND_BITS
126 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
127 select HAVE_ARCH_PREL32_RELOCATIONS
128 select HAVE_ARCH_SECCOMP_FILTER
129 select HAVE_ARCH_STACKLEAK
130 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
131 select HAVE_ARCH_TRACEHOOK
132 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
133 select HAVE_ARCH_VMAP_STACK
134 select HAVE_ARM_SMCCC
135 select HAVE_ASM_MODVERSIONS
137 select HAVE_C_RECORDMCOUNT
138 select HAVE_CMPXCHG_DOUBLE
139 select HAVE_CMPXCHG_LOCAL
140 select HAVE_CONTEXT_TRACKING
141 select HAVE_COPY_THREAD_TLS
142 select HAVE_DEBUG_BUGVERBOSE
143 select HAVE_DEBUG_KMEMLEAK
144 select HAVE_DMA_CONTIGUOUS
145 select HAVE_DYNAMIC_FTRACE
146 select HAVE_DYNAMIC_FTRACE_WITH_REGS \
147 if $(cc-option,-fpatchable-function-entry=2)
148 select HAVE_EFFICIENT_UNALIGNED_ACCESS
150 select HAVE_FTRACE_MCOUNT_RECORD
151 select HAVE_FUNCTION_TRACER
152 select HAVE_FUNCTION_ERROR_INJECTION
153 select HAVE_FUNCTION_GRAPH_TRACER
154 select HAVE_GCC_PLUGINS
155 select HAVE_HW_BREAKPOINT if PERF_EVENTS
156 select HAVE_IRQ_TIME_ACCOUNTING
157 select HAVE_MEMBLOCK_NODE_MAP if NUMA
159 select HAVE_PATA_PLATFORM
160 select HAVE_PERF_EVENTS
161 select HAVE_PERF_REGS
162 select HAVE_PERF_USER_STACK_DUMP
163 select HAVE_REGS_AND_STACK_ACCESS_API
164 select HAVE_FUNCTION_ARG_ACCESS_API
165 select HAVE_FUTEX_CMPXCHG if FUTEX
166 select HAVE_RCU_TABLE_FREE
168 select HAVE_STACKPROTECTOR
169 select HAVE_SYSCALL_TRACEPOINTS
171 select HAVE_KRETPROBES
172 select HAVE_GENERIC_VDSO
173 select IOMMU_DMA if IOMMU_SUPPORT
175 select IRQ_FORCED_THREADING
176 select MODULES_USE_ELF_RELA
177 select NEED_DMA_MAP_STATE
178 select NEED_SG_DMA_LENGTH
180 select OF_EARLY_FLATTREE
181 select PCI_DOMAINS_GENERIC if PCI
182 select PCI_ECAM if (ACPI && PCI)
183 select PCI_SYSCALL if PCI
188 select SYSCTL_EXCEPTION_TRACE
189 select THREAD_INFO_IN_TASK
191 ARM 64-bit (AArch64) Linux support.
199 config ARM64_PAGE_SHIFT
201 default 16 if ARM64_64K_PAGES
202 default 14 if ARM64_16K_PAGES
205 config ARM64_CONT_SHIFT
207 default 5 if ARM64_64K_PAGES
208 default 7 if ARM64_16K_PAGES
211 config ARCH_MMAP_RND_BITS_MIN
212 default 14 if ARM64_64K_PAGES
213 default 16 if ARM64_16K_PAGES
216 # max bits determined by the following formula:
217 # VA_BITS - PAGE_SHIFT - 3
218 config ARCH_MMAP_RND_BITS_MAX
219 default 19 if ARM64_VA_BITS=36
220 default 24 if ARM64_VA_BITS=39
221 default 27 if ARM64_VA_BITS=42
222 default 30 if ARM64_VA_BITS=47
223 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
224 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
225 default 33 if ARM64_VA_BITS=48
226 default 14 if ARM64_64K_PAGES
227 default 16 if ARM64_16K_PAGES
230 config ARCH_MMAP_RND_COMPAT_BITS_MIN
231 default 7 if ARM64_64K_PAGES
232 default 9 if ARM64_16K_PAGES
235 config ARCH_MMAP_RND_COMPAT_BITS_MAX
241 config STACKTRACE_SUPPORT
244 config ILLEGAL_POINTER_VALUE
246 default 0xdead000000000000
248 config LOCKDEP_SUPPORT
251 config TRACE_IRQFLAGS_SUPPORT
258 config GENERIC_BUG_RELATIVE_POINTERS
260 depends on GENERIC_BUG
262 config GENERIC_HWEIGHT
268 config GENERIC_CALIBRATE_DELAY
272 bool "Support DMA zone" if EXPERT
276 bool "Support DMA32 zone" if EXPERT
279 config ARCH_ENABLE_MEMORY_HOTPLUG
285 config KERNEL_MODE_NEON
288 config FIX_EARLYCON_MEM
291 config PGTABLE_LEVELS
293 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
294 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
295 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
296 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
297 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
298 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
300 config ARCH_SUPPORTS_UPROBES
303 config ARCH_PROC_KCORE_TEXT
306 config BROKEN_GAS_INST
307 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
309 config KASAN_SHADOW_OFFSET
312 default 0xdfffa00000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
313 default 0xdfffd00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
314 default 0xdffffe8000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
315 default 0xdfffffd000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
316 default 0xdffffffa00000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
317 default 0xefff900000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
318 default 0xefffc80000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
319 default 0xeffffe4000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
320 default 0xefffffc800000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
321 default 0xeffffff900000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
322 default 0xffffffffffffffff
324 source "arch/arm64/Kconfig.platforms"
326 menu "Kernel Features"
328 menu "ARM errata workarounds via the alternatives framework"
330 config ARM64_WORKAROUND_CLEAN_CACHE
333 config ARM64_ERRATUM_826319
334 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
336 select ARM64_WORKAROUND_CLEAN_CACHE
338 This option adds an alternative code sequence to work around ARM
339 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
340 AXI master interface and an L2 cache.
342 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
343 and is unable to accept a certain write via this interface, it will
344 not progress on read data presented on the read data channel and the
347 The workaround promotes data cache clean instructions to
348 data cache clean-and-invalidate.
349 Please note that this does not necessarily enable the workaround,
350 as it depends on the alternative framework, which will only patch
351 the kernel if an affected CPU is detected.
355 config ARM64_ERRATUM_827319
356 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
358 select ARM64_WORKAROUND_CLEAN_CACHE
360 This option adds an alternative code sequence to work around ARM
361 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
362 master interface and an L2 cache.
364 Under certain conditions this erratum can cause a clean line eviction
365 to occur at the same time as another transaction to the same address
366 on the AMBA 5 CHI interface, which can cause data corruption if the
367 interconnect reorders the two transactions.
369 The workaround promotes data cache clean instructions to
370 data cache clean-and-invalidate.
371 Please note that this does not necessarily enable the workaround,
372 as it depends on the alternative framework, which will only patch
373 the kernel if an affected CPU is detected.
377 config ARM64_ERRATUM_824069
378 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
380 select ARM64_WORKAROUND_CLEAN_CACHE
382 This option adds an alternative code sequence to work around ARM
383 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
384 to a coherent interconnect.
386 If a Cortex-A53 processor is executing a store or prefetch for
387 write instruction at the same time as a processor in another
388 cluster is executing a cache maintenance operation to the same
389 address, then this erratum might cause a clean cache line to be
390 incorrectly marked as dirty.
392 The workaround promotes data cache clean instructions to
393 data cache clean-and-invalidate.
394 Please note that this option does not necessarily enable the
395 workaround, as it depends on the alternative framework, which will
396 only patch the kernel if an affected CPU is detected.
400 config ARM64_ERRATUM_819472
401 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
403 select ARM64_WORKAROUND_CLEAN_CACHE
405 This option adds an alternative code sequence to work around ARM
406 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
407 present when it is connected to a coherent interconnect.
409 If the processor is executing a load and store exclusive sequence at
410 the same time as a processor in another cluster is executing a cache
411 maintenance operation to the same address, then this erratum might
412 cause data corruption.
414 The workaround promotes data cache clean instructions to
415 data cache clean-and-invalidate.
416 Please note that this does not necessarily enable the workaround,
417 as it depends on the alternative framework, which will only patch
418 the kernel if an affected CPU is detected.
422 config ARM64_ERRATUM_832075
423 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
426 This option adds an alternative code sequence to work around ARM
427 erratum 832075 on Cortex-A57 parts up to r1p2.
429 Affected Cortex-A57 parts might deadlock when exclusive load/store
430 instructions to Write-Back memory are mixed with Device loads.
432 The workaround is to promote device loads to use Load-Acquire
434 Please note that this does not necessarily enable the workaround,
435 as it depends on the alternative framework, which will only patch
436 the kernel if an affected CPU is detected.
440 config ARM64_ERRATUM_834220
441 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
445 This option adds an alternative code sequence to work around ARM
446 erratum 834220 on Cortex-A57 parts up to r1p2.
448 Affected Cortex-A57 parts might report a Stage 2 translation
449 fault as the result of a Stage 1 fault for load crossing a
450 page boundary when there is a permission or device memory
451 alignment fault at Stage 1 and a translation fault at Stage 2.
453 The workaround is to verify that the Stage 1 translation
454 doesn't generate a fault before handling the Stage 2 fault.
455 Please note that this does not necessarily enable the workaround,
456 as it depends on the alternative framework, which will only patch
457 the kernel if an affected CPU is detected.
461 config ARM64_ERRATUM_845719
462 bool "Cortex-A53: 845719: a load might read incorrect data"
466 This option adds an alternative code sequence to work around ARM
467 erratum 845719 on Cortex-A53 parts up to r0p4.
469 When running a compat (AArch32) userspace on an affected Cortex-A53
470 part, a load at EL0 from a virtual address that matches the bottom 32
471 bits of the virtual address used by a recent load at (AArch64) EL1
472 might return incorrect data.
474 The workaround is to write the contextidr_el1 register on exception
475 return to a 32-bit task.
476 Please note that this does not necessarily enable the workaround,
477 as it depends on the alternative framework, which will only patch
478 the kernel if an affected CPU is detected.
482 config ARM64_ERRATUM_843419
483 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
485 select ARM64_MODULE_PLTS if MODULES
487 This option links the kernel with '--fix-cortex-a53-843419' and
488 enables PLT support to replace certain ADRP instructions, which can
489 cause subsequent memory accesses to use an incorrect address on
490 Cortex-A53 parts up to r0p4.
494 config ARM64_ERRATUM_1024718
495 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
498 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
500 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
501 update of the hardware dirty bit when the DBM/AP bits are updated
502 without a break-before-make. The workaround is to disable the usage
503 of hardware DBM locally on the affected cores. CPUs not affected by
504 this erratum will continue to use the feature.
508 config ARM64_ERRATUM_1418040
509 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
513 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
514 errata 1188873 and 1418040.
516 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
517 cause register corruption when accessing the timer registers
518 from AArch32 userspace.
522 config ARM64_WORKAROUND_SPECULATIVE_AT_VHE
525 config ARM64_ERRATUM_1165522
526 bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
528 select ARM64_WORKAROUND_SPECULATIVE_AT_VHE
530 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
532 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
533 corrupted TLBs by speculating an AT instruction during a guest
538 config ARM64_ERRATUM_1530923
539 bool "Cortex-A55: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
541 select ARM64_WORKAROUND_SPECULATIVE_AT_VHE
543 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
545 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
546 corrupted TLBs by speculating an AT instruction during a guest
551 config ARM64_ERRATUM_1286807
552 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
554 select ARM64_WORKAROUND_REPEAT_TLBI
556 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
558 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
559 address for a cacheable mapping of a location is being
560 accessed by a core while another core is remapping the virtual
561 address to a new physical page using the recommended
562 break-before-make sequence, then under very rare circumstances
563 TLBI+DSB completes before a read using the translation being
564 invalidated has been observed by other observers. The
565 workaround repeats the TLBI+DSB operation.
567 config ARM64_WORKAROUND_SPECULATIVE_AT_NVHE
570 config ARM64_ERRATUM_1319367
571 bool "Cortex-A57/A72: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
573 select ARM64_WORKAROUND_SPECULATIVE_AT_NVHE
575 This option adds work arounds for ARM Cortex-A57 erratum 1319537
576 and A72 erratum 1319367
578 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
579 speculating an AT instruction during a guest context switch.
583 config ARM64_ERRATUM_1463225
584 bool "Cortex-A76: Software Step might prevent interrupt recognition"
587 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
589 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
590 of a system call instruction (SVC) can prevent recognition of
591 subsequent interrupts when software stepping is disabled in the
592 exception handler of the system call and either kernel debugging
593 is enabled or VHE is in use.
595 Work around the erratum by triggering a dummy step exception
596 when handling a system call from a task that is being stepped
597 in a VHE configuration of the kernel.
601 config ARM64_ERRATUM_1542419
602 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
605 This option adds a workaround for ARM Neoverse-N1 erratum
608 Affected Neoverse-N1 cores could execute a stale instruction when
609 modified by another CPU. The workaround depends on a firmware
612 Workaround the issue by hiding the DIC feature from EL0. This
613 forces user-space to perform cache maintenance.
617 config CAVIUM_ERRATUM_22375
618 bool "Cavium erratum 22375, 24313"
621 Enable workaround for errata 22375 and 24313.
623 This implements two gicv3-its errata workarounds for ThunderX. Both
624 with a small impact affecting only ITS table allocation.
626 erratum 22375: only alloc 8MB table size
627 erratum 24313: ignore memory access type
629 The fixes are in ITS initialization and basically ignore memory access
630 type and table size provided by the TYPER and BASER registers.
634 config CAVIUM_ERRATUM_23144
635 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
639 ITS SYNC command hang for cross node io and collections/cpu mapping.
643 config CAVIUM_ERRATUM_23154
644 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
647 The gicv3 of ThunderX requires a modified version for
648 reading the IAR status to ensure data synchronization
649 (access to icc_iar1_el1 is not sync'ed before and after).
653 config CAVIUM_ERRATUM_27456
654 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
657 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
658 instructions may cause the icache to become corrupted if it
659 contains data for a non-current ASID. The fix is to
660 invalidate the icache when changing the mm context.
664 config CAVIUM_ERRATUM_30115
665 bool "Cavium erratum 30115: Guest may disable interrupts in host"
668 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
669 1.2, and T83 Pass 1.0, KVM guest execution may disable
670 interrupts in host. Trapping both GICv3 group-0 and group-1
671 accesses sidesteps the issue.
675 config CAVIUM_TX2_ERRATUM_219
676 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
679 On Cavium ThunderX2, a load, store or prefetch instruction between a
680 TTBR update and the corresponding context synchronizing operation can
681 cause a spurious Data Abort to be delivered to any hardware thread in
684 Work around the issue by avoiding the problematic code sequence and
685 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
686 trap handler performs the corresponding register access, skips the
687 instruction and ensures context synchronization by virtue of the
692 config QCOM_FALKOR_ERRATUM_1003
693 bool "Falkor E1003: Incorrect translation due to ASID change"
696 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
697 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
698 in TTBR1_EL1, this situation only occurs in the entry trampoline and
699 then only for entries in the walk cache, since the leaf translation
700 is unchanged. Work around the erratum by invalidating the walk cache
701 entries for the trampoline before entering the kernel proper.
703 config ARM64_WORKAROUND_REPEAT_TLBI
706 config QCOM_FALKOR_ERRATUM_1009
707 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
709 select ARM64_WORKAROUND_REPEAT_TLBI
711 On Falkor v1, the CPU may prematurely complete a DSB following a
712 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
713 one more time to fix the issue.
717 config QCOM_QDF2400_ERRATUM_0065
718 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
721 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
722 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
723 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
727 config SOCIONEXT_SYNQUACER_PREITS
728 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
731 Socionext Synquacer SoCs implement a separate h/w block to generate
732 MSI doorbell writes with non-zero values for the device ID.
736 config HISILICON_ERRATUM_161600802
737 bool "Hip07 161600802: Erroneous redistributor VLPI base"
740 The HiSilicon Hip07 SoC uses the wrong redistributor base
741 when issued ITS commands such as VMOVP and VMAPP, and requires
742 a 128kB offset to be applied to the target address in this commands.
746 config QCOM_FALKOR_ERRATUM_E1041
747 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
750 Falkor CPU may speculatively fetch instructions from an improper
751 memory location when MMU translation is changed from SCTLR_ELn[M]=1
752 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
756 config FUJITSU_ERRATUM_010001
757 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
760 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
761 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
762 accesses may cause undefined fault (Data abort, DFSC=0b111111).
763 This fault occurs under a specific hardware condition when a
764 load/store instruction performs an address translation using:
765 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
766 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
767 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
768 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
770 The workaround is to ensure these bits are clear in TCR_ELx.
771 The workaround only affects the Fujitsu-A64FX.
780 default ARM64_4K_PAGES
782 Page size (translation granule) configuration.
784 config ARM64_4K_PAGES
787 This feature enables 4KB pages support.
789 config ARM64_16K_PAGES
792 The system will use 16KB pages support. AArch32 emulation
793 requires applications compiled with 16K (or a multiple of 16K)
796 config ARM64_64K_PAGES
799 This feature enables 64KB pages support (4KB by default)
800 allowing only two levels of page tables and faster TLB
801 look-up. AArch32 emulation requires applications compiled
802 with 64K aligned segments.
807 prompt "Virtual address space size"
808 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
809 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
810 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
812 Allows choosing one of multiple possible virtual address
813 space sizes. The level of translation table is determined by
814 a combination of page size and virtual address space size.
816 config ARM64_VA_BITS_36
817 bool "36-bit" if EXPERT
818 depends on ARM64_16K_PAGES
820 config ARM64_VA_BITS_39
822 depends on ARM64_4K_PAGES
824 config ARM64_VA_BITS_42
826 depends on ARM64_64K_PAGES
828 config ARM64_VA_BITS_47
830 depends on ARM64_16K_PAGES
832 config ARM64_VA_BITS_48
835 config ARM64_VA_BITS_52
837 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
839 Enable 52-bit virtual addressing for userspace when explicitly
840 requested via a hint to mmap(). The kernel will also use 52-bit
841 virtual addresses for its own mappings (provided HW support for
842 this feature is available, otherwise it reverts to 48-bit).
844 NOTE: Enabling 52-bit virtual addressing in conjunction with
845 ARMv8.3 Pointer Authentication will result in the PAC being
846 reduced from 7 bits to 3 bits, which may have a significant
847 impact on its susceptibility to brute-force attacks.
849 If unsure, select 48-bit virtual addressing instead.
853 config ARM64_FORCE_52BIT
854 bool "Force 52-bit virtual addresses for userspace"
855 depends on ARM64_VA_BITS_52 && EXPERT
857 For systems with 52-bit userspace VAs enabled, the kernel will attempt
858 to maintain compatibility with older software by providing 48-bit VAs
859 unless a hint is supplied to mmap.
861 This configuration option disables the 48-bit compatibility logic, and
862 forces all userspace addresses to be 52-bit on HW that supports it. One
863 should only enable this configuration option for stress testing userspace
864 memory management code. If unsure say N here.
868 default 36 if ARM64_VA_BITS_36
869 default 39 if ARM64_VA_BITS_39
870 default 42 if ARM64_VA_BITS_42
871 default 47 if ARM64_VA_BITS_47
872 default 48 if ARM64_VA_BITS_48
873 default 52 if ARM64_VA_BITS_52
876 prompt "Physical address space size"
877 default ARM64_PA_BITS_48
879 Choose the maximum physical address range that the kernel will
882 config ARM64_PA_BITS_48
885 config ARM64_PA_BITS_52
886 bool "52-bit (ARMv8.2)"
887 depends on ARM64_64K_PAGES
888 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
890 Enable support for a 52-bit physical address space, introduced as
891 part of the ARMv8.2-LPA extension.
893 With this enabled, the kernel will also continue to work on CPUs that
894 do not support ARMv8.2-LPA, but with some added memory overhead (and
895 minor performance overhead).
901 default 48 if ARM64_PA_BITS_48
902 default 52 if ARM64_PA_BITS_52
906 default CPU_LITTLE_ENDIAN
908 Select the endianness of data accesses performed by the CPU. Userspace
909 applications will need to be compiled and linked for the endianness
910 that is selected here.
912 config CPU_BIG_ENDIAN
913 bool "Build big-endian kernel"
915 Say Y if you plan on running a kernel with a big-endian userspace.
917 config CPU_LITTLE_ENDIAN
918 bool "Build little-endian kernel"
920 Say Y if you plan on running a kernel with a little-endian userspace.
921 This is usually the case for distributions targeting arm64.
926 bool "Multi-core scheduler support"
928 Multi-core scheduler support improves the CPU scheduler's decision
929 making when dealing with multi-core CPU chips at a cost of slightly
930 increased overhead in some places. If unsure say N here.
933 bool "SMT scheduler support"
935 Improves the CPU scheduler's decision making when dealing with
936 MultiThreading at a cost of slightly increased overhead in some
937 places. If unsure say N here.
940 int "Maximum number of CPUs (2-4096)"
945 bool "Support for hot-pluggable CPUs"
946 select GENERIC_IRQ_MIGRATION
948 Say Y here to experiment with turning CPUs off and on. CPUs
949 can be controlled through /sys/devices/system/cpu.
951 # Common NUMA Features
953 bool "Numa Memory Allocation and Scheduler Support"
954 select ACPI_NUMA if ACPI
957 Enable NUMA (Non Uniform Memory Access) support.
959 The kernel will try to allocate memory used by a CPU on the
960 local memory of the CPU and add some more
961 NUMA awareness to the kernel.
964 int "Maximum NUMA Nodes (as a power of 2)"
967 depends on NEED_MULTIPLE_NODES
969 Specify the maximum number of NUMA Nodes available on the target
970 system. Increases memory reserved to accommodate various tables.
972 config USE_PERCPU_NUMA_NODE_ID
976 config HAVE_SETUP_PER_CPU_AREA
980 config NEED_PER_CPU_EMBED_FIRST_CHUNK
987 source "kernel/Kconfig.hz"
989 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
992 config ARCH_SPARSEMEM_ENABLE
994 select SPARSEMEM_VMEMMAP_ENABLE
996 config ARCH_SPARSEMEM_DEFAULT
997 def_bool ARCH_SPARSEMEM_ENABLE
999 config ARCH_SELECT_MEMORY_MODEL
1000 def_bool ARCH_SPARSEMEM_ENABLE
1002 config ARCH_FLATMEM_ENABLE
1005 config HAVE_ARCH_PFN_VALID
1008 config HW_PERF_EVENTS
1012 config SYS_SUPPORTS_HUGETLBFS
1015 config ARCH_WANT_HUGE_PMD_SHARE
1017 config ARCH_HAS_CACHE_LINE_SIZE
1020 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
1021 def_bool y if PGTABLE_LEVELS > 2
1024 bool "Enable seccomp to safely compute untrusted bytecode"
1026 This kernel feature is useful for number crunching applications
1027 that may need to compute untrusted bytecode during their
1028 execution. By using pipes or other transports made available to
1029 the process as file descriptors supporting the read/write
1030 syscalls, it's possible to isolate those applications in
1031 their own address space using seccomp. Once seccomp is
1032 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1033 and the task is only allowed to execute a few safe syscalls
1034 defined by each seccomp mode.
1037 bool "Enable paravirtualization code"
1039 This changes the kernel so it can modify itself when it is run
1040 under a hypervisor, potentially improving performance significantly
1041 over full virtualization.
1043 config PARAVIRT_TIME_ACCOUNTING
1044 bool "Paravirtual steal time accounting"
1047 Select this option to enable fine granularity task steal time
1048 accounting. Time spent executing other tasks in parallel with
1049 the current vCPU is discounted from the vCPU power. To account for
1050 that, there can be a small performance impact.
1052 If in doubt, say N here.
1055 depends on PM_SLEEP_SMP
1057 bool "kexec system call"
1059 kexec is a system call that implements the ability to shutdown your
1060 current kernel, and to start another kernel. It is like a reboot
1061 but it is independent of the system firmware. And like a reboot
1062 you can start any kernel with it, not just Linux.
1065 bool "kexec file based system call"
1068 This is new version of kexec system call. This system call is
1069 file based and takes file descriptors as system call argument
1070 for kernel and initramfs as opposed to list of segments as
1071 accepted by previous system call.
1074 bool "Verify kernel signature during kexec_file_load() syscall"
1075 depends on KEXEC_FILE
1077 Select this option to verify a signature with loaded kernel
1078 image. If configured, any attempt of loading a image without
1079 valid signature will fail.
1081 In addition to that option, you need to enable signature
1082 verification for the corresponding kernel image type being
1083 loaded in order for this to work.
1085 config KEXEC_IMAGE_VERIFY_SIG
1086 bool "Enable Image signature verification support"
1088 depends on KEXEC_SIG
1089 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1091 Enable Image signature verification support.
1093 comment "Support for PE file signature verification disabled"
1094 depends on KEXEC_SIG
1095 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1098 bool "Build kdump crash kernel"
1100 Generate crash dump after being started by kexec. This should
1101 be normally only set in special crash dump kernels which are
1102 loaded in the main kernel with kexec-tools into a specially
1103 reserved region and then later executed after a crash by
1106 For more details see Documentation/admin-guide/kdump/kdump.rst
1113 bool "Xen guest support on ARM64"
1114 depends on ARM64 && OF
1118 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1120 config FORCE_MAX_ZONEORDER
1122 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1123 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1126 The kernel memory allocator divides physically contiguous memory
1127 blocks into "zones", where each zone is a power of two number of
1128 pages. This option selects the largest power of two that the kernel
1129 keeps in the memory allocator. If you need to allocate very large
1130 blocks of physically contiguous memory, then you may need to
1131 increase this value.
1133 This config option is actually maximum order plus one. For example,
1134 a value of 11 means that the largest free memory block is 2^10 pages.
1136 We make sure that we can allocate upto a HugePage size for each configuration.
1138 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1140 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1141 4M allocations matching the default size used by generic code.
1143 config UNMAP_KERNEL_AT_EL0
1144 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1147 Speculation attacks against some high-performance processors can
1148 be used to bypass MMU permission checks and leak kernel data to
1149 userspace. This can be defended against by unmapping the kernel
1150 when running in userspace, mapping it back in on exception entry
1151 via a trampoline page in the vector table.
1155 config HARDEN_BRANCH_PREDICTOR
1156 bool "Harden the branch predictor against aliasing attacks" if EXPERT
1159 Speculation attacks against some high-performance processors rely on
1160 being able to manipulate the branch predictor for a victim context by
1161 executing aliasing branches in the attacker context. Such attacks
1162 can be partially mitigated against by clearing internal branch
1163 predictor state and limiting the prediction logic in some situations.
1165 This config option will take CPU-specific actions to harden the
1166 branch predictor against aliasing attacks and may rely on specific
1167 instruction sequences or control bits being set by the system
1172 config HARDEN_EL2_VECTORS
1173 bool "Harden EL2 vector mapping against system register leak" if EXPERT
1176 Speculation attacks against some high-performance processors can
1177 be used to leak privileged information such as the vector base
1178 register, resulting in a potential defeat of the EL2 layout
1181 This config option will map the vectors to a fixed location,
1182 independent of the EL2 code mapping, so that revealing VBAR_EL2
1183 to an attacker does not give away any extra information. This
1184 only gets enabled on affected CPUs.
1189 bool "Speculative Store Bypass Disable" if EXPERT
1192 This enables mitigation of the bypassing of previous stores
1193 by speculative loads.
1197 config RODATA_FULL_DEFAULT_ENABLED
1198 bool "Apply r/o permissions of VM areas also to their linear aliases"
1201 Apply read-only attributes of VM areas to the linear alias of
1202 the backing pages as well. This prevents code or read-only data
1203 from being modified (inadvertently or intentionally) via another
1204 mapping of the same memory page. This additional enhancement can
1205 be turned off at runtime by passing rodata=[off|on] (and turned on
1206 with rodata=full if this option is set to 'n')
1208 This requires the linear region to be mapped down to pages,
1209 which may adversely affect performance in some cases.
1211 config ARM64_SW_TTBR0_PAN
1212 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1214 Enabling this option prevents the kernel from accessing
1215 user-space memory directly by pointing TTBR0_EL1 to a reserved
1216 zeroed area and reserved ASID. The user access routines
1217 restore the valid TTBR0_EL1 temporarily.
1219 config ARM64_TAGGED_ADDR_ABI
1220 bool "Enable the tagged user addresses syscall ABI"
1223 When this option is enabled, user applications can opt in to a
1224 relaxed ABI via prctl() allowing tagged addresses to be passed
1225 to system calls as pointer arguments. For details, see
1226 Documentation/arm64/tagged-address-abi.rst.
1229 bool "Kernel support for 32-bit EL0"
1230 depends on ARM64_4K_PAGES || EXPERT
1231 select COMPAT_BINFMT_ELF if BINFMT_ELF
1233 select OLD_SIGSUSPEND3
1234 select COMPAT_OLD_SIGACTION
1236 This option enables support for a 32-bit EL0 running under a 64-bit
1237 kernel at EL1. AArch32-specific components such as system calls,
1238 the user helper functions, VFP support and the ptrace interface are
1239 handled appropriately by the kernel.
1241 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1242 that you will only be able to execute AArch32 binaries that were compiled
1243 with page size aligned segments.
1245 If you want to execute 32-bit userspace applications, say Y.
1249 config KUSER_HELPERS
1250 bool "Enable kuser helpers page for 32-bit applications"
1253 Warning: disabling this option may break 32-bit user programs.
1255 Provide kuser helpers to compat tasks. The kernel provides
1256 helper code to userspace in read only form at a fixed location
1257 to allow userspace to be independent of the CPU type fitted to
1258 the system. This permits binaries to be run on ARMv4 through
1259 to ARMv8 without modification.
1261 See Documentation/arm/kernel_user_helpers.rst for details.
1263 However, the fixed address nature of these helpers can be used
1264 by ROP (return orientated programming) authors when creating
1267 If all of the binaries and libraries which run on your platform
1268 are built specifically for your platform, and make no use of
1269 these helpers, then you can turn this option off to hinder
1270 such exploits. However, in that case, if a binary or library
1271 relying on those helpers is run, it will not function correctly.
1273 Say N here only if you are absolutely certain that you do not
1274 need these helpers; otherwise, the safe option is to say Y.
1277 bool "Enable vDSO for 32-bit applications"
1278 depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1279 select GENERIC_COMPAT_VDSO
1282 Place in the process address space of 32-bit applications an
1283 ELF shared object providing fast implementations of gettimeofday
1286 You must have a 32-bit build of glibc 2.22 or later for programs
1287 to seamlessly take advantage of this.
1289 menuconfig ARMV8_DEPRECATED
1290 bool "Emulate deprecated/obsolete ARMv8 instructions"
1293 Legacy software support may require certain instructions
1294 that have been deprecated or obsoleted in the architecture.
1296 Enable this config to enable selective emulation of these
1303 config SWP_EMULATION
1304 bool "Emulate SWP/SWPB instructions"
1306 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1307 they are always undefined. Say Y here to enable software
1308 emulation of these instructions for userspace using LDXR/STXR.
1310 In some older versions of glibc [<=2.8] SWP is used during futex
1311 trylock() operations with the assumption that the code will not
1312 be preempted. This invalid assumption may be more likely to fail
1313 with SWP emulation enabled, leading to deadlock of the user
1316 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1317 on an external transaction monitoring block called a global
1318 monitor to maintain update atomicity. If your system does not
1319 implement a global monitor, this option can cause programs that
1320 perform SWP operations to uncached memory to deadlock.
1324 config CP15_BARRIER_EMULATION
1325 bool "Emulate CP15 Barrier instructions"
1327 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1328 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1329 strongly recommended to use the ISB, DSB, and DMB
1330 instructions instead.
1332 Say Y here to enable software emulation of these
1333 instructions for AArch32 userspace code. When this option is
1334 enabled, CP15 barrier usage is traced which can help
1335 identify software that needs updating.
1339 config SETEND_EMULATION
1340 bool "Emulate SETEND instruction"
1342 The SETEND instruction alters the data-endianness of the
1343 AArch32 EL0, and is deprecated in ARMv8.
1345 Say Y here to enable software emulation of the instruction
1346 for AArch32 userspace code.
1348 Note: All the cpus on the system must have mixed endian support at EL0
1349 for this feature to be enabled. If a new CPU - which doesn't support mixed
1350 endian - is hotplugged in after this feature has been enabled, there could
1351 be unexpected results in the applications.
1358 menu "ARMv8.1 architectural features"
1360 config ARM64_HW_AFDBM
1361 bool "Support for hardware updates of the Access and Dirty page flags"
1364 The ARMv8.1 architecture extensions introduce support for
1365 hardware updates of the access and dirty information in page
1366 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1367 capable processors, accesses to pages with PTE_AF cleared will
1368 set this bit instead of raising an access flag fault.
1369 Similarly, writes to read-only pages with the DBM bit set will
1370 clear the read-only bit (AP[2]) instead of raising a
1373 Kernels built with this configuration option enabled continue
1374 to work on pre-ARMv8.1 hardware and the performance impact is
1375 minimal. If unsure, say Y.
1378 bool "Enable support for Privileged Access Never (PAN)"
1381 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1382 prevents the kernel or hypervisor from accessing user-space (EL0)
1385 Choosing this option will cause any unprotected (not using
1386 copy_to_user et al) memory access to fail with a permission fault.
1388 The feature is detected at runtime, and will remain as a 'nop'
1389 instruction if the cpu does not implement the feature.
1391 config ARM64_LSE_ATOMICS
1393 default ARM64_USE_LSE_ATOMICS
1394 depends on $(as-instr,.arch_extension lse)
1396 config ARM64_USE_LSE_ATOMICS
1397 bool "Atomic instructions"
1398 depends on JUMP_LABEL
1401 As part of the Large System Extensions, ARMv8.1 introduces new
1402 atomic instructions that are designed specifically to scale in
1405 Say Y here to make use of these instructions for the in-kernel
1406 atomic routines. This incurs a small overhead on CPUs that do
1407 not support these instructions and requires the kernel to be
1408 built with binutils >= 2.25 in order for the new instructions
1412 bool "Enable support for Virtualization Host Extensions (VHE)"
1415 Virtualization Host Extensions (VHE) allow the kernel to run
1416 directly at EL2 (instead of EL1) on processors that support
1417 it. This leads to better performance for KVM, as they reduce
1418 the cost of the world switch.
1420 Selecting this option allows the VHE feature to be detected
1421 at runtime, and does not affect processors that do not
1422 implement this feature.
1426 menu "ARMv8.2 architectural features"
1429 bool "Enable support for User Access Override (UAO)"
1432 User Access Override (UAO; part of the ARMv8.2 Extensions)
1433 causes the 'unprivileged' variant of the load/store instructions to
1434 be overridden to be privileged.
1436 This option changes get_user() and friends to use the 'unprivileged'
1437 variant of the load/store instructions. This ensures that user-space
1438 really did have access to the supplied memory. When addr_limit is
1439 set to kernel memory the UAO bit will be set, allowing privileged
1440 access to kernel memory.
1442 Choosing this option will cause copy_to_user() et al to use user-space
1445 The feature is detected at runtime, the kernel will use the
1446 regular load/store instructions if the cpu does not implement the
1450 bool "Enable support for persistent memory"
1451 select ARCH_HAS_PMEM_API
1452 select ARCH_HAS_UACCESS_FLUSHCACHE
1454 Say Y to enable support for the persistent memory API based on the
1455 ARMv8.2 DCPoP feature.
1457 The feature is detected at runtime, and the kernel will use DC CVAC
1458 operations if DC CVAP is not supported (following the behaviour of
1459 DC CVAP itself if the system does not define a point of persistence).
1461 config ARM64_RAS_EXTN
1462 bool "Enable support for RAS CPU Extensions"
1465 CPUs that support the Reliability, Availability and Serviceability
1466 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1467 errors, classify them and report them to software.
1469 On CPUs with these extensions system software can use additional
1470 barriers to determine if faults are pending and read the
1471 classification from a new set of registers.
1473 Selecting this feature will allow the kernel to use these barriers
1474 and access the new registers if the system supports the extension.
1475 Platform RAS features may additionally depend on firmware support.
1478 bool "Enable support for Common Not Private (CNP) translations"
1480 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1482 Common Not Private (CNP) allows translation table entries to
1483 be shared between different PEs in the same inner shareable
1484 domain, so the hardware can use this fact to optimise the
1485 caching of such entries in the TLB.
1487 Selecting this option allows the CNP feature to be detected
1488 at runtime, and does not affect PEs that do not implement
1493 menu "ARMv8.3 architectural features"
1495 config ARM64_PTR_AUTH
1496 bool "Enable support for pointer authentication"
1498 depends on !KVM || ARM64_VHE
1500 Pointer authentication (part of the ARMv8.3 Extensions) provides
1501 instructions for signing and authenticating pointers against secret
1502 keys, which can be used to mitigate Return Oriented Programming (ROP)
1505 This option enables these instructions at EL0 (i.e. for userspace).
1507 Choosing this option will cause the kernel to initialise secret keys
1508 for each process at exec() time, with these keys being
1509 context-switched along with the process.
1511 The feature is detected at runtime. If the feature is not present in
1512 hardware it will not be advertised to userspace/KVM guest nor will it
1513 be enabled. However, KVM guest also require VHE mode and hence
1514 CONFIG_ARM64_VHE=y option to use this feature.
1518 menu "ARMv8.5 architectural features"
1521 bool "Enable support for E0PD"
1524 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1525 that EL0 accesses made via TTBR1 always fault in constant time,
1526 providing similar benefits to KASLR as those provided by KPTI, but
1527 with lower overhead and without disrupting legitimate access to
1528 kernel memory such as SPE.
1530 This option enables E0PD for TTBR1 where available.
1533 bool "Enable support for random number generation"
1536 Random number generation (part of the ARMv8.5 Extensions)
1537 provides a high bandwidth, cryptographically secure
1538 hardware random number generator.
1543 bool "ARM Scalable Vector Extension support"
1545 depends on !KVM || ARM64_VHE
1547 The Scalable Vector Extension (SVE) is an extension to the AArch64
1548 execution state which complements and extends the SIMD functionality
1549 of the base architecture to support much larger vectors and to enable
1550 additional vectorisation opportunities.
1552 To enable use of this extension on CPUs that implement it, say Y.
1554 On CPUs that support the SVE2 extensions, this option will enable
1557 Note that for architectural reasons, firmware _must_ implement SVE
1558 support when running on SVE capable hardware. The required support
1561 * version 1.5 and later of the ARM Trusted Firmware
1562 * the AArch64 boot wrapper since commit 5e1261e08abf
1563 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1565 For other firmware implementations, consult the firmware documentation
1568 If you need the kernel to boot on SVE-capable hardware with broken
1569 firmware, you may need to say N here until you get your firmware
1570 fixed. Otherwise, you may experience firmware panics or lockups when
1571 booting the kernel. If unsure and you are not observing these
1572 symptoms, you should assume that it is safe to say Y.
1574 CPUs that support SVE are architecturally required to support the
1575 Virtualization Host Extensions (VHE), so the kernel makes no
1576 provision for supporting SVE alongside KVM without VHE enabled.
1577 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1578 KVM in the same kernel image.
1580 config ARM64_MODULE_PLTS
1581 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1583 select HAVE_MOD_ARCH_SPECIFIC
1585 Allocate PLTs when loading modules so that jumps and calls whose
1586 targets are too far away for their relative offsets to be encoded
1587 in the instructions themselves can be bounced via veneers in the
1588 module's PLT. This allows modules to be allocated in the generic
1589 vmalloc area after the dedicated module memory area has been
1592 When running with address space randomization (KASLR), the module
1593 region itself may be too far away for ordinary relative jumps and
1594 calls, and so in that case, module PLTs are required and cannot be
1597 Specific errata workaround(s) might also force module PLTs to be
1598 enabled (ARM64_ERRATUM_843419).
1600 config ARM64_PSEUDO_NMI
1601 bool "Support for NMI-like interrupts"
1604 Adds support for mimicking Non-Maskable Interrupts through the use of
1605 GIC interrupt priority. This support requires version 3 or later of
1608 This high priority configuration for interrupts needs to be
1609 explicitly enabled by setting the kernel parameter
1610 "irqchip.gicv3_pseudo_nmi" to 1.
1615 config ARM64_DEBUG_PRIORITY_MASKING
1616 bool "Debug interrupt priority masking"
1618 This adds runtime checks to functions enabling/disabling
1619 interrupts when using priority masking. The additional checks verify
1620 the validity of ICC_PMR_EL1 when calling concerned functions.
1627 select ARCH_HAS_RELR
1629 This builds the kernel as a Position Independent Executable (PIE),
1630 which retains all relocation metadata required to relocate the
1631 kernel binary at runtime to a different virtual address than the
1632 address it was linked at.
1633 Since AArch64 uses the RELA relocation format, this requires a
1634 relocation pass at runtime even if the kernel is loaded at the
1635 same address it was linked at.
1637 config RANDOMIZE_BASE
1638 bool "Randomize the address of the kernel image"
1639 select ARM64_MODULE_PLTS if MODULES
1642 Randomizes the virtual address at which the kernel image is
1643 loaded, as a security feature that deters exploit attempts
1644 relying on knowledge of the location of kernel internals.
1646 It is the bootloader's job to provide entropy, by passing a
1647 random u64 value in /chosen/kaslr-seed at kernel entry.
1649 When booting via the UEFI stub, it will invoke the firmware's
1650 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1651 to the kernel proper. In addition, it will randomise the physical
1652 location of the kernel Image as well.
1656 config RANDOMIZE_MODULE_REGION_FULL
1657 bool "Randomize the module region over a 4 GB range"
1658 depends on RANDOMIZE_BASE
1661 Randomizes the location of the module region inside a 4 GB window
1662 covering the core kernel. This way, it is less likely for modules
1663 to leak information about the location of core kernel data structures
1664 but it does imply that function calls between modules and the core
1665 kernel will need to be resolved via veneers in the module PLT.
1667 When this option is not set, the module region will be randomized over
1668 a limited range that contains the [_stext, _etext] interval of the
1669 core kernel, so branch relocations are always in range.
1671 config CC_HAVE_STACKPROTECTOR_SYSREG
1672 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1674 config STACKPROTECTOR_PER_TASK
1676 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1682 config ARM64_ACPI_PARKING_PROTOCOL
1683 bool "Enable support for the ARM64 ACPI parking protocol"
1686 Enable support for the ARM64 ACPI parking protocol. If disabled
1687 the kernel will not allow booting through the ARM64 ACPI parking
1688 protocol even if the corresponding data is present in the ACPI
1692 string "Default kernel command string"
1695 Provide a set of default command-line options at build time by
1696 entering them here. As a minimum, you should specify the the
1697 root device (e.g. root=/dev/nfs).
1699 config CMDLINE_FORCE
1700 bool "Always use the default kernel command string"
1701 depends on CMDLINE != ""
1703 Always use the default kernel command string, even if the boot
1704 loader passes other arguments to the kernel.
1705 This is useful if you cannot or don't want to change the
1706 command-line options your boot loader passes to the kernel.
1712 bool "UEFI runtime support"
1713 depends on OF && !CPU_BIG_ENDIAN
1714 depends on KERNEL_MODE_NEON
1715 select ARCH_SUPPORTS_ACPI
1718 select EFI_PARAMS_FROM_FDT
1719 select EFI_RUNTIME_WRAPPERS
1724 This option provides support for runtime services provided
1725 by UEFI firmware (such as non-volatile variables, realtime
1726 clock, and platform reset). A UEFI stub is also provided to
1727 allow the kernel to be booted as an EFI application. This
1728 is only useful on systems that have UEFI firmware.
1731 bool "Enable support for SMBIOS (DMI) tables"
1735 This enables SMBIOS/DMI feature for systems.
1737 This option is only useful on systems that have UEFI firmware.
1738 However, even with this option, the resultant kernel should
1739 continue to boot on existing non-UEFI platforms.
1743 config SYSVIPC_COMPAT
1745 depends on COMPAT && SYSVIPC
1747 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1749 depends on HUGETLB_PAGE && MIGRATION
1751 menu "Power management options"
1753 source "kernel/power/Kconfig"
1755 config ARCH_HIBERNATION_POSSIBLE
1759 config ARCH_HIBERNATION_HEADER
1761 depends on HIBERNATION
1763 config ARCH_SUSPEND_POSSIBLE
1768 menu "CPU Power Management"
1770 source "drivers/cpuidle/Kconfig"
1772 source "drivers/cpufreq/Kconfig"
1776 source "drivers/firmware/Kconfig"
1778 source "drivers/acpi/Kconfig"
1780 source "arch/arm64/kvm/Kconfig"
1783 source "arch/arm64/crypto/Kconfig"