3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if ACPI
9 select ACPI_SPCR_TABLE if ACPI
10 select ARCH_CLOCKSOURCE_DATA
11 select ARCH_HAS_DEBUG_VIRTUAL
12 select ARCH_HAS_DEVMEM_IS_ALLOWED
13 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
14 select ARCH_HAS_ELF_RANDOMIZE
15 select ARCH_HAS_FORTIFY_SOURCE
16 select ARCH_HAS_GCOV_PROFILE_ALL
17 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
19 select ARCH_HAS_SET_MEMORY
20 select ARCH_HAS_SG_CHAIN
21 select ARCH_HAS_STRICT_KERNEL_RWX
22 select ARCH_HAS_STRICT_MODULE_RWX
23 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
24 select ARCH_HAVE_NMI_SAFE_CMPXCHG
25 select ARCH_INLINE_READ_LOCK if !PREEMPT
26 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
27 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
28 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
29 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
30 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
31 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
32 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
33 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
34 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
35 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
36 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
37 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
38 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
39 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
40 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
41 select ARCH_USE_CMPXCHG_LOCKREF
42 select ARCH_USE_QUEUED_RWLOCKS
43 select ARCH_SUPPORTS_MEMORY_FAILURE
44 select ARCH_SUPPORTS_ATOMIC_RMW
45 select ARCH_SUPPORTS_NUMA_BALANCING
46 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
47 select ARCH_WANT_FRAME_POINTERS
48 select ARCH_HAS_UBSAN_SANITIZE_ALL
52 select AUDIT_ARCH_COMPAT_GENERIC
53 select ARM_GIC_V2M if PCI
55 select ARM_GIC_V3_ITS if PCI
57 select BUILDTIME_EXTABLE_SORT
58 select CLONE_BACKWARDS
60 select CPU_PM if (SUSPEND || CPU_IDLE)
61 select DCACHE_WORD_ACCESS
65 select GENERIC_ALLOCATOR
66 select GENERIC_ARCH_TOPOLOGY
67 select GENERIC_CLOCKEVENTS
68 select GENERIC_CLOCKEVENTS_BROADCAST
69 select GENERIC_CPU_AUTOPROBE
70 select GENERIC_EARLY_IOREMAP
71 select GENERIC_IDLE_POLL_SETUP
72 select GENERIC_IRQ_PROBE
73 select GENERIC_IRQ_SHOW
74 select GENERIC_IRQ_SHOW_LEVEL
75 select GENERIC_PCI_IOMAP
76 select GENERIC_SCHED_CLOCK
77 select GENERIC_SMP_IDLE_THREAD
78 select GENERIC_STRNCPY_FROM_USER
79 select GENERIC_STRNLEN_USER
80 select GENERIC_TIME_VSYSCALL
81 select HANDLE_DOMAIN_IRQ
82 select HARDIRQS_SW_RESEND
83 select HAVE_ACPI_APEI if (ACPI && EFI)
84 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
85 select HAVE_ARCH_AUDITSYSCALL
86 select HAVE_ARCH_BITREVERSE
87 select HAVE_ARCH_HUGE_VMAP
88 select HAVE_ARCH_JUMP_LABEL
89 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
91 select HAVE_ARCH_MMAP_RND_BITS
92 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
93 select HAVE_ARCH_SECCOMP_FILTER
94 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
95 select HAVE_ARCH_TRACEHOOK
96 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
97 select HAVE_ARCH_VMAP_STACK
100 select HAVE_C_RECORDMCOUNT
101 select HAVE_CC_STACKPROTECTOR
102 select HAVE_CMPXCHG_DOUBLE
103 select HAVE_CMPXCHG_LOCAL
104 select HAVE_CONTEXT_TRACKING
105 select HAVE_DEBUG_BUGVERBOSE
106 select HAVE_DEBUG_KMEMLEAK
107 select HAVE_DMA_API_DEBUG
108 select HAVE_DMA_CONTIGUOUS
109 select HAVE_DYNAMIC_FTRACE
110 select HAVE_EFFICIENT_UNALIGNED_ACCESS
111 select HAVE_FTRACE_MCOUNT_RECORD
112 select HAVE_FUNCTION_TRACER
113 select HAVE_FUNCTION_GRAPH_TRACER
114 select HAVE_GCC_PLUGINS
115 select HAVE_GENERIC_DMA_COHERENT
116 select HAVE_HW_BREAKPOINT if PERF_EVENTS
117 select HAVE_IRQ_TIME_ACCOUNTING
119 select HAVE_MEMBLOCK_NODE_MAP if NUMA
121 select HAVE_PATA_PLATFORM
122 select HAVE_PERF_EVENTS
123 select HAVE_PERF_REGS
124 select HAVE_PERF_USER_STACK_DUMP
125 select HAVE_REGS_AND_STACK_ACCESS_API
126 select HAVE_RCU_TABLE_FREE
127 select HAVE_SYSCALL_TRACEPOINTS
129 select HAVE_KRETPROBES
130 select IOMMU_DMA if IOMMU_SUPPORT
132 select IRQ_FORCED_THREADING
133 select MODULES_USE_ELF_RELA
136 select OF_EARLY_FLATTREE
137 select OF_RESERVED_MEM
138 select PCI_ECAM if ACPI
143 select SYSCTL_EXCEPTION_TRACE
144 select THREAD_INFO_IN_TASK
146 ARM 64-bit (AArch64) Linux support.
151 config ARCH_PHYS_ADDR_T_64BIT
157 config ARM64_PAGE_SHIFT
159 default 16 if ARM64_64K_PAGES
160 default 14 if ARM64_16K_PAGES
163 config ARM64_CONT_SHIFT
165 default 5 if ARM64_64K_PAGES
166 default 7 if ARM64_16K_PAGES
169 config ARCH_MMAP_RND_BITS_MIN
170 default 14 if ARM64_64K_PAGES
171 default 16 if ARM64_16K_PAGES
174 # max bits determined by the following formula:
175 # VA_BITS - PAGE_SHIFT - 3
176 config ARCH_MMAP_RND_BITS_MAX
177 default 19 if ARM64_VA_BITS=36
178 default 24 if ARM64_VA_BITS=39
179 default 27 if ARM64_VA_BITS=42
180 default 30 if ARM64_VA_BITS=47
181 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
182 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
183 default 33 if ARM64_VA_BITS=48
184 default 14 if ARM64_64K_PAGES
185 default 16 if ARM64_16K_PAGES
188 config ARCH_MMAP_RND_COMPAT_BITS_MIN
189 default 7 if ARM64_64K_PAGES
190 default 9 if ARM64_16K_PAGES
193 config ARCH_MMAP_RND_COMPAT_BITS_MAX
199 config STACKTRACE_SUPPORT
202 config ILLEGAL_POINTER_VALUE
204 default 0xdead000000000000
206 config LOCKDEP_SUPPORT
209 config TRACE_IRQFLAGS_SUPPORT
212 config RWSEM_XCHGADD_ALGORITHM
219 config GENERIC_BUG_RELATIVE_POINTERS
221 depends on GENERIC_BUG
223 config GENERIC_HWEIGHT
229 config GENERIC_CALIBRATE_DELAY
235 config HAVE_GENERIC_GUP
238 config ARCH_DMA_ADDR_T_64BIT
241 config NEED_DMA_MAP_STATE
244 config NEED_SG_DMA_LENGTH
256 config KERNEL_MODE_NEON
259 config FIX_EARLYCON_MEM
262 config PGTABLE_LEVELS
264 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
265 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
266 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
267 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
268 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
269 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
271 config ARCH_SUPPORTS_UPROBES
274 config ARCH_PROC_KCORE_TEXT
277 source "init/Kconfig"
279 source "kernel/Kconfig.freezer"
281 source "arch/arm64/Kconfig.platforms"
288 This feature enables support for PCI bus system. If you say Y
289 here, the kernel will include drivers and infrastructure code
290 to support PCI bus devices.
295 config PCI_DOMAINS_GENERIC
301 source "drivers/pci/Kconfig"
305 menu "Kernel Features"
307 menu "ARM errata workarounds via the alternatives framework"
309 config ARM64_ERRATUM_826319
310 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
313 This option adds an alternative code sequence to work around ARM
314 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
315 AXI master interface and an L2 cache.
317 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
318 and is unable to accept a certain write via this interface, it will
319 not progress on read data presented on the read data channel and the
322 The workaround promotes data cache clean instructions to
323 data cache clean-and-invalidate.
324 Please note that this does not necessarily enable the workaround,
325 as it depends on the alternative framework, which will only patch
326 the kernel if an affected CPU is detected.
330 config ARM64_ERRATUM_827319
331 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
334 This option adds an alternative code sequence to work around ARM
335 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
336 master interface and an L2 cache.
338 Under certain conditions this erratum can cause a clean line eviction
339 to occur at the same time as another transaction to the same address
340 on the AMBA 5 CHI interface, which can cause data corruption if the
341 interconnect reorders the two transactions.
343 The workaround promotes data cache clean instructions to
344 data cache clean-and-invalidate.
345 Please note that this does not necessarily enable the workaround,
346 as it depends on the alternative framework, which will only patch
347 the kernel if an affected CPU is detected.
351 config ARM64_ERRATUM_824069
352 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
355 This option adds an alternative code sequence to work around ARM
356 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
357 to a coherent interconnect.
359 If a Cortex-A53 processor is executing a store or prefetch for
360 write instruction at the same time as a processor in another
361 cluster is executing a cache maintenance operation to the same
362 address, then this erratum might cause a clean cache line to be
363 incorrectly marked as dirty.
365 The workaround promotes data cache clean instructions to
366 data cache clean-and-invalidate.
367 Please note that this option does not necessarily enable the
368 workaround, as it depends on the alternative framework, which will
369 only patch the kernel if an affected CPU is detected.
373 config ARM64_ERRATUM_819472
374 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
377 This option adds an alternative code sequence to work around ARM
378 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
379 present when it is connected to a coherent interconnect.
381 If the processor is executing a load and store exclusive sequence at
382 the same time as a processor in another cluster is executing a cache
383 maintenance operation to the same address, then this erratum might
384 cause data corruption.
386 The workaround promotes data cache clean instructions to
387 data cache clean-and-invalidate.
388 Please note that this does not necessarily enable the workaround,
389 as it depends on the alternative framework, which will only patch
390 the kernel if an affected CPU is detected.
394 config ARM64_ERRATUM_832075
395 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
398 This option adds an alternative code sequence to work around ARM
399 erratum 832075 on Cortex-A57 parts up to r1p2.
401 Affected Cortex-A57 parts might deadlock when exclusive load/store
402 instructions to Write-Back memory are mixed with Device loads.
404 The workaround is to promote device loads to use Load-Acquire
406 Please note that this does not necessarily enable the workaround,
407 as it depends on the alternative framework, which will only patch
408 the kernel if an affected CPU is detected.
412 config ARM64_ERRATUM_834220
413 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
417 This option adds an alternative code sequence to work around ARM
418 erratum 834220 on Cortex-A57 parts up to r1p2.
420 Affected Cortex-A57 parts might report a Stage 2 translation
421 fault as the result of a Stage 1 fault for load crossing a
422 page boundary when there is a permission or device memory
423 alignment fault at Stage 1 and a translation fault at Stage 2.
425 The workaround is to verify that the Stage 1 translation
426 doesn't generate a fault before handling the Stage 2 fault.
427 Please note that this does not necessarily enable the workaround,
428 as it depends on the alternative framework, which will only patch
429 the kernel if an affected CPU is detected.
433 config ARM64_ERRATUM_845719
434 bool "Cortex-A53: 845719: a load might read incorrect data"
438 This option adds an alternative code sequence to work around ARM
439 erratum 845719 on Cortex-A53 parts up to r0p4.
441 When running a compat (AArch32) userspace on an affected Cortex-A53
442 part, a load at EL0 from a virtual address that matches the bottom 32
443 bits of the virtual address used by a recent load at (AArch64) EL1
444 might return incorrect data.
446 The workaround is to write the contextidr_el1 register on exception
447 return to a 32-bit task.
448 Please note that this does not necessarily enable the workaround,
449 as it depends on the alternative framework, which will only patch
450 the kernel if an affected CPU is detected.
454 config ARM64_ERRATUM_843419
455 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
457 select ARM64_MODULE_CMODEL_LARGE if MODULES
459 This option links the kernel with '--fix-cortex-a53-843419' and
460 builds modules using the large memory model in order to avoid the use
461 of the ADRP instruction, which can cause a subsequent memory access
462 to use an incorrect address on Cortex-A53 parts up to r0p4.
466 config CAVIUM_ERRATUM_22375
467 bool "Cavium erratum 22375, 24313"
470 Enable workaround for erratum 22375, 24313.
472 This implements two gicv3-its errata workarounds for ThunderX. Both
473 with small impact affecting only ITS table allocation.
475 erratum 22375: only alloc 8MB table size
476 erratum 24313: ignore memory access type
478 The fixes are in ITS initialization and basically ignore memory access
479 type and table size provided by the TYPER and BASER registers.
483 config CAVIUM_ERRATUM_23144
484 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
488 ITS SYNC command hang for cross node io and collections/cpu mapping.
492 config CAVIUM_ERRATUM_23154
493 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
496 The gicv3 of ThunderX requires a modified version for
497 reading the IAR status to ensure data synchronization
498 (access to icc_iar1_el1 is not sync'ed before and after).
502 config CAVIUM_ERRATUM_27456
503 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
506 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
507 instructions may cause the icache to become corrupted if it
508 contains data for a non-current ASID. The fix is to
509 invalidate the icache when changing the mm context.
513 config CAVIUM_ERRATUM_30115
514 bool "Cavium erratum 30115: Guest may disable interrupts in host"
517 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
518 1.2, and T83 Pass 1.0, KVM guest execution may disable
519 interrupts in host. Trapping both GICv3 group-0 and group-1
520 accesses sidesteps the issue.
524 config QCOM_FALKOR_ERRATUM_1003
525 bool "Falkor E1003: Incorrect translation due to ASID change"
528 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
529 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
530 in TTBR1_EL1, this situation only occurs in the entry trampoline and
531 then only for entries in the walk cache, since the leaf translation
532 is unchanged. Work around the erratum by invalidating the walk cache
533 entries for the trampoline before entering the kernel proper.
535 config QCOM_FALKOR_ERRATUM_1009
536 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
539 On Falkor v1, the CPU may prematurely complete a DSB following a
540 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
541 one more time to fix the issue.
545 config QCOM_QDF2400_ERRATUM_0065
546 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
549 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
550 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
551 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
555 config SOCIONEXT_SYNQUACER_PREITS
556 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
559 Socionext Synquacer SoCs implement a separate h/w block to generate
560 MSI doorbell writes with non-zero values for the device ID.
564 config HISILICON_ERRATUM_161600802
565 bool "Hip07 161600802: Erroneous redistributor VLPI base"
568 The HiSilicon Hip07 SoC usees the wrong redistributor base
569 when issued ITS commands such as VMOVP and VMAPP, and requires
570 a 128kB offset to be applied to the target address in this commands.
574 config QCOM_FALKOR_ERRATUM_E1041
575 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
578 Falkor CPU may speculatively fetch instructions from an improper
579 memory location when MMU translation is changed from SCTLR_ELn[M]=1
580 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
589 default ARM64_4K_PAGES
591 Page size (translation granule) configuration.
593 config ARM64_4K_PAGES
596 This feature enables 4KB pages support.
598 config ARM64_16K_PAGES
601 The system will use 16KB pages support. AArch32 emulation
602 requires applications compiled with 16K (or a multiple of 16K)
605 config ARM64_64K_PAGES
608 This feature enables 64KB pages support (4KB by default)
609 allowing only two levels of page tables and faster TLB
610 look-up. AArch32 emulation requires applications compiled
611 with 64K aligned segments.
616 prompt "Virtual address space size"
617 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
618 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
619 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
621 Allows choosing one of multiple possible virtual address
622 space sizes. The level of translation table is determined by
623 a combination of page size and virtual address space size.
625 config ARM64_VA_BITS_36
626 bool "36-bit" if EXPERT
627 depends on ARM64_16K_PAGES
629 config ARM64_VA_BITS_39
631 depends on ARM64_4K_PAGES
633 config ARM64_VA_BITS_42
635 depends on ARM64_64K_PAGES
637 config ARM64_VA_BITS_47
639 depends on ARM64_16K_PAGES
641 config ARM64_VA_BITS_48
648 default 36 if ARM64_VA_BITS_36
649 default 39 if ARM64_VA_BITS_39
650 default 42 if ARM64_VA_BITS_42
651 default 47 if ARM64_VA_BITS_47
652 default 48 if ARM64_VA_BITS_48
655 prompt "Physical address space size"
656 default ARM64_PA_BITS_48
658 Choose the maximum physical address range that the kernel will
661 config ARM64_PA_BITS_48
664 config ARM64_PA_BITS_52
665 bool "52-bit (ARMv8.2)"
666 depends on ARM64_64K_PAGES
667 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
669 Enable support for a 52-bit physical address space, introduced as
670 part of the ARMv8.2-LPA extension.
672 With this enabled, the kernel will also continue to work on CPUs that
673 do not support ARMv8.2-LPA, but with some added memory overhead (and
674 minor performance overhead).
680 default 48 if ARM64_PA_BITS_48
681 default 52 if ARM64_PA_BITS_52
683 config CPU_BIG_ENDIAN
684 bool "Build big-endian kernel"
686 Say Y if you plan on running a kernel in big-endian mode.
689 bool "Multi-core scheduler support"
691 Multi-core scheduler support improves the CPU scheduler's decision
692 making when dealing with multi-core CPU chips at a cost of slightly
693 increased overhead in some places. If unsure say N here.
696 bool "SMT scheduler support"
698 Improves the CPU scheduler's decision making when dealing with
699 MultiThreading at a cost of slightly increased overhead in some
700 places. If unsure say N here.
703 int "Maximum number of CPUs (2-4096)"
705 # These have to remain sorted largest to smallest
709 bool "Support for hot-pluggable CPUs"
710 select GENERIC_IRQ_MIGRATION
712 Say Y here to experiment with turning CPUs off and on. CPUs
713 can be controlled through /sys/devices/system/cpu.
715 # Common NUMA Features
717 bool "Numa Memory Allocation and Scheduler Support"
718 select ACPI_NUMA if ACPI
721 Enable NUMA (Non Uniform Memory Access) support.
723 The kernel will try to allocate memory used by a CPU on the
724 local memory of the CPU and add some more
725 NUMA awareness to the kernel.
728 int "Maximum NUMA Nodes (as a power of 2)"
731 depends on NEED_MULTIPLE_NODES
733 Specify the maximum number of NUMA Nodes available on the target
734 system. Increases memory reserved to accommodate various tables.
736 config USE_PERCPU_NUMA_NODE_ID
740 config HAVE_SETUP_PER_CPU_AREA
744 config NEED_PER_CPU_EMBED_FIRST_CHUNK
752 source kernel/Kconfig.preempt
753 source kernel/Kconfig.hz
755 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
758 config ARCH_HAS_HOLES_MEMORYMODEL
759 def_bool y if SPARSEMEM
761 config ARCH_SPARSEMEM_ENABLE
763 select SPARSEMEM_VMEMMAP_ENABLE
765 config ARCH_SPARSEMEM_DEFAULT
766 def_bool ARCH_SPARSEMEM_ENABLE
768 config ARCH_SELECT_MEMORY_MODEL
769 def_bool ARCH_SPARSEMEM_ENABLE
771 config HAVE_ARCH_PFN_VALID
772 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
774 config HW_PERF_EVENTS
778 config SYS_SUPPORTS_HUGETLBFS
781 config ARCH_WANT_HUGE_PMD_SHARE
782 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
784 config ARCH_HAS_CACHE_LINE_SIZE
790 bool "Enable seccomp to safely compute untrusted bytecode"
792 This kernel feature is useful for number crunching applications
793 that may need to compute untrusted bytecode during their
794 execution. By using pipes or other transports made available to
795 the process as file descriptors supporting the read/write
796 syscalls, it's possible to isolate those applications in
797 their own address space using seccomp. Once seccomp is
798 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
799 and the task is only allowed to execute a few safe syscalls
800 defined by each seccomp mode.
803 bool "Enable paravirtualization code"
805 This changes the kernel so it can modify itself when it is run
806 under a hypervisor, potentially improving performance significantly
807 over full virtualization.
809 config PARAVIRT_TIME_ACCOUNTING
810 bool "Paravirtual steal time accounting"
814 Select this option to enable fine granularity task steal time
815 accounting. Time spent executing other tasks in parallel with
816 the current vCPU is discounted from the vCPU power. To account for
817 that, there can be a small performance impact.
819 If in doubt, say N here.
822 depends on PM_SLEEP_SMP
824 bool "kexec system call"
826 kexec is a system call that implements the ability to shutdown your
827 current kernel, and to start another kernel. It is like a reboot
828 but it is independent of the system firmware. And like a reboot
829 you can start any kernel with it, not just Linux.
832 bool "Build kdump crash kernel"
834 Generate crash dump after being started by kexec. This should
835 be normally only set in special crash dump kernels which are
836 loaded in the main kernel with kexec-tools into a specially
837 reserved region and then later executed after a crash by
840 For more details see Documentation/kdump/kdump.txt
847 bool "Xen guest support on ARM64"
848 depends on ARM64 && OF
852 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
854 config FORCE_MAX_ZONEORDER
856 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
857 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
860 The kernel memory allocator divides physically contiguous memory
861 blocks into "zones", where each zone is a power of two number of
862 pages. This option selects the largest power of two that the kernel
863 keeps in the memory allocator. If you need to allocate very large
864 blocks of physically contiguous memory, then you may need to
867 This config option is actually maximum order plus one. For example,
868 a value of 11 means that the largest free memory block is 2^10 pages.
870 We make sure that we can allocate upto a HugePage size for each configuration.
872 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
874 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
875 4M allocations matching the default size used by generic code.
877 config UNMAP_KERNEL_AT_EL0
878 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
881 Speculation attacks against some high-performance processors can
882 be used to bypass MMU permission checks and leak kernel data to
883 userspace. This can be defended against by unmapping the kernel
884 when running in userspace, mapping it back in on exception entry
885 via a trampoline page in the vector table.
889 config HARDEN_BRANCH_PREDICTOR
890 bool "Harden the branch predictor against aliasing attacks" if EXPERT
893 Speculation attacks against some high-performance processors rely on
894 being able to manipulate the branch predictor for a victim context by
895 executing aliasing branches in the attacker context. Such attacks
896 can be partially mitigated against by clearing internal branch
897 predictor state and limiting the prediction logic in some situations.
899 This config option will take CPU-specific actions to harden the
900 branch predictor against aliasing attacks and may rely on specific
901 instruction sequences or control bits being set by the system
906 menuconfig ARMV8_DEPRECATED
907 bool "Emulate deprecated/obsolete ARMv8 instructions"
911 Legacy software support may require certain instructions
912 that have been deprecated or obsoleted in the architecture.
914 Enable this config to enable selective emulation of these
922 bool "Emulate SWP/SWPB instructions"
924 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
925 they are always undefined. Say Y here to enable software
926 emulation of these instructions for userspace using LDXR/STXR.
928 In some older versions of glibc [<=2.8] SWP is used during futex
929 trylock() operations with the assumption that the code will not
930 be preempted. This invalid assumption may be more likely to fail
931 with SWP emulation enabled, leading to deadlock of the user
934 NOTE: when accessing uncached shared regions, LDXR/STXR rely
935 on an external transaction monitoring block called a global
936 monitor to maintain update atomicity. If your system does not
937 implement a global monitor, this option can cause programs that
938 perform SWP operations to uncached memory to deadlock.
942 config CP15_BARRIER_EMULATION
943 bool "Emulate CP15 Barrier instructions"
945 The CP15 barrier instructions - CP15ISB, CP15DSB, and
946 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
947 strongly recommended to use the ISB, DSB, and DMB
948 instructions instead.
950 Say Y here to enable software emulation of these
951 instructions for AArch32 userspace code. When this option is
952 enabled, CP15 barrier usage is traced which can help
953 identify software that needs updating.
957 config SETEND_EMULATION
958 bool "Emulate SETEND instruction"
960 The SETEND instruction alters the data-endianness of the
961 AArch32 EL0, and is deprecated in ARMv8.
963 Say Y here to enable software emulation of the instruction
964 for AArch32 userspace code.
966 Note: All the cpus on the system must have mixed endian support at EL0
967 for this feature to be enabled. If a new CPU - which doesn't support mixed
968 endian - is hotplugged in after this feature has been enabled, there could
969 be unexpected results in the applications.
974 config ARM64_SW_TTBR0_PAN
975 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
977 Enabling this option prevents the kernel from accessing
978 user-space memory directly by pointing TTBR0_EL1 to a reserved
979 zeroed area and reserved ASID. The user access routines
980 restore the valid TTBR0_EL1 temporarily.
982 menu "ARMv8.1 architectural features"
984 config ARM64_HW_AFDBM
985 bool "Support for hardware updates of the Access and Dirty page flags"
988 The ARMv8.1 architecture extensions introduce support for
989 hardware updates of the access and dirty information in page
990 table entries. When enabled in TCR_EL1 (HA and HD bits) on
991 capable processors, accesses to pages with PTE_AF cleared will
992 set this bit instead of raising an access flag fault.
993 Similarly, writes to read-only pages with the DBM bit set will
994 clear the read-only bit (AP[2]) instead of raising a
997 Kernels built with this configuration option enabled continue
998 to work on pre-ARMv8.1 hardware and the performance impact is
999 minimal. If unsure, say Y.
1002 bool "Enable support for Privileged Access Never (PAN)"
1005 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1006 prevents the kernel or hypervisor from accessing user-space (EL0)
1009 Choosing this option will cause any unprotected (not using
1010 copy_to_user et al) memory access to fail with a permission fault.
1012 The feature is detected at runtime, and will remain as a 'nop'
1013 instruction if the cpu does not implement the feature.
1015 config ARM64_LSE_ATOMICS
1016 bool "Atomic instructions"
1018 As part of the Large System Extensions, ARMv8.1 introduces new
1019 atomic instructions that are designed specifically to scale in
1022 Say Y here to make use of these instructions for the in-kernel
1023 atomic routines. This incurs a small overhead on CPUs that do
1024 not support these instructions and requires the kernel to be
1025 built with binutils >= 2.25.
1028 bool "Enable support for Virtualization Host Extensions (VHE)"
1031 Virtualization Host Extensions (VHE) allow the kernel to run
1032 directly at EL2 (instead of EL1) on processors that support
1033 it. This leads to better performance for KVM, as they reduce
1034 the cost of the world switch.
1036 Selecting this option allows the VHE feature to be detected
1037 at runtime, and does not affect processors that do not
1038 implement this feature.
1042 menu "ARMv8.2 architectural features"
1045 bool "Enable support for User Access Override (UAO)"
1048 User Access Override (UAO; part of the ARMv8.2 Extensions)
1049 causes the 'unprivileged' variant of the load/store instructions to
1050 be overridden to be privileged.
1052 This option changes get_user() and friends to use the 'unprivileged'
1053 variant of the load/store instructions. This ensures that user-space
1054 really did have access to the supplied memory. When addr_limit is
1055 set to kernel memory the UAO bit will be set, allowing privileged
1056 access to kernel memory.
1058 Choosing this option will cause copy_to_user() et al to use user-space
1061 The feature is detected at runtime, the kernel will use the
1062 regular load/store instructions if the cpu does not implement the
1066 bool "Enable support for persistent memory"
1067 select ARCH_HAS_PMEM_API
1068 select ARCH_HAS_UACCESS_FLUSHCACHE
1070 Say Y to enable support for the persistent memory API based on the
1071 ARMv8.2 DCPoP feature.
1073 The feature is detected at runtime, and the kernel will use DC CVAC
1074 operations if DC CVAP is not supported (following the behaviour of
1075 DC CVAP itself if the system does not define a point of persistence).
1077 config ARM64_RAS_EXTN
1078 bool "Enable support for RAS CPU Extensions"
1081 CPUs that support the Reliability, Availability and Serviceability
1082 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1083 errors, classify them and report them to software.
1085 On CPUs with these extensions system software can use additional
1086 barriers to determine if faults are pending and read the
1087 classification from a new set of registers.
1089 Selecting this feature will allow the kernel to use these barriers
1090 and access the new registers if the system supports the extension.
1091 Platform RAS features may additionally depend on firmware support.
1096 bool "ARM Scalable Vector Extension support"
1099 The Scalable Vector Extension (SVE) is an extension to the AArch64
1100 execution state which complements and extends the SIMD functionality
1101 of the base architecture to support much larger vectors and to enable
1102 additional vectorisation opportunities.
1104 To enable use of this extension on CPUs that implement it, say Y.
1106 config ARM64_MODULE_CMODEL_LARGE
1109 config ARM64_MODULE_PLTS
1111 select ARM64_MODULE_CMODEL_LARGE
1112 select HAVE_MOD_ARCH_SPECIFIC
1117 This builds the kernel as a Position Independent Executable (PIE),
1118 which retains all relocation metadata required to relocate the
1119 kernel binary at runtime to a different virtual address than the
1120 address it was linked at.
1121 Since AArch64 uses the RELA relocation format, this requires a
1122 relocation pass at runtime even if the kernel is loaded at the
1123 same address it was linked at.
1125 config RANDOMIZE_BASE
1126 bool "Randomize the address of the kernel image"
1127 select ARM64_MODULE_PLTS if MODULES
1130 Randomizes the virtual address at which the kernel image is
1131 loaded, as a security feature that deters exploit attempts
1132 relying on knowledge of the location of kernel internals.
1134 It is the bootloader's job to provide entropy, by passing a
1135 random u64 value in /chosen/kaslr-seed at kernel entry.
1137 When booting via the UEFI stub, it will invoke the firmware's
1138 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1139 to the kernel proper. In addition, it will randomise the physical
1140 location of the kernel Image as well.
1144 config RANDOMIZE_MODULE_REGION_FULL
1145 bool "Randomize the module region independently from the core kernel"
1146 depends on RANDOMIZE_BASE
1149 Randomizes the location of the module region without considering the
1150 location of the core kernel. This way, it is impossible for modules
1151 to leak information about the location of core kernel data structures
1152 but it does imply that function calls between modules and the core
1153 kernel will need to be resolved via veneers in the module PLT.
1155 When this option is not set, the module region will be randomized over
1156 a limited range that contains the [_stext, _etext] interval of the
1157 core kernel, so branch relocations are always in range.
1163 config ARM64_ACPI_PARKING_PROTOCOL
1164 bool "Enable support for the ARM64 ACPI parking protocol"
1167 Enable support for the ARM64 ACPI parking protocol. If disabled
1168 the kernel will not allow booting through the ARM64 ACPI parking
1169 protocol even if the corresponding data is present in the ACPI
1173 string "Default kernel command string"
1176 Provide a set of default command-line options at build time by
1177 entering them here. As a minimum, you should specify the the
1178 root device (e.g. root=/dev/nfs).
1180 config CMDLINE_FORCE
1181 bool "Always use the default kernel command string"
1183 Always use the default kernel command string, even if the boot
1184 loader passes other arguments to the kernel.
1185 This is useful if you cannot or don't want to change the
1186 command-line options your boot loader passes to the kernel.
1192 bool "UEFI runtime support"
1193 depends on OF && !CPU_BIG_ENDIAN
1194 depends on KERNEL_MODE_NEON
1197 select EFI_PARAMS_FROM_FDT
1198 select EFI_RUNTIME_WRAPPERS
1203 This option provides support for runtime services provided
1204 by UEFI firmware (such as non-volatile variables, realtime
1205 clock, and platform reset). A UEFI stub is also provided to
1206 allow the kernel to be booted as an EFI application. This
1207 is only useful on systems that have UEFI firmware.
1210 bool "Enable support for SMBIOS (DMI) tables"
1214 This enables SMBIOS/DMI feature for systems.
1216 This option is only useful on systems that have UEFI firmware.
1217 However, even with this option, the resultant kernel should
1218 continue to boot on existing non-UEFI platforms.
1222 menu "Userspace binary formats"
1224 source "fs/Kconfig.binfmt"
1227 bool "Kernel support for 32-bit EL0"
1228 depends on ARM64_4K_PAGES || EXPERT
1229 select COMPAT_BINFMT_ELF if BINFMT_ELF
1231 select OLD_SIGSUSPEND3
1232 select COMPAT_OLD_SIGACTION
1234 This option enables support for a 32-bit EL0 running under a 64-bit
1235 kernel at EL1. AArch32-specific components such as system calls,
1236 the user helper functions, VFP support and the ptrace interface are
1237 handled appropriately by the kernel.
1239 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1240 that you will only be able to execute AArch32 binaries that were compiled
1241 with page size aligned segments.
1243 If you want to execute 32-bit userspace applications, say Y.
1245 config SYSVIPC_COMPAT
1247 depends on COMPAT && SYSVIPC
1251 menu "Power management options"
1253 source "kernel/power/Kconfig"
1255 config ARCH_HIBERNATION_POSSIBLE
1259 config ARCH_HIBERNATION_HEADER
1261 depends on HIBERNATION
1263 config ARCH_SUSPEND_POSSIBLE
1268 menu "CPU Power Management"
1270 source "drivers/cpuidle/Kconfig"
1272 source "drivers/cpufreq/Kconfig"
1276 source "net/Kconfig"
1278 source "drivers/Kconfig"
1280 source "drivers/firmware/Kconfig"
1282 source "drivers/acpi/Kconfig"
1286 source "arch/arm64/kvm/Kconfig"
1288 source "arch/arm64/Kconfig.debug"
1290 source "security/Kconfig"
1292 source "crypto/Kconfig"
1294 source "arch/arm64/crypto/Kconfig"
1297 source "lib/Kconfig"