3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if (ACPI && PCI)
9 select ACPI_SPCR_TABLE if ACPI
10 select ACPI_PPTT if ACPI
11 select ARCH_CLOCKSOURCE_DATA
12 select ARCH_HAS_DEBUG_VIRTUAL
13 select ARCH_HAS_DEVMEM_IS_ALLOWED
14 select ARCH_HAS_DMA_COHERENT_TO_PFN
15 select ARCH_HAS_DMA_MMAP_PGPROT
16 select ARCH_HAS_DMA_PREP_COHERENT
17 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
18 select ARCH_HAS_ELF_RANDOMIZE
19 select ARCH_HAS_FAST_MULTIPLIER
20 select ARCH_HAS_FORTIFY_SOURCE
21 select ARCH_HAS_GCOV_PROFILE_ALL
22 select ARCH_HAS_GIGANTIC_PAGE
24 select ARCH_HAS_KEEPINITRD
25 select ARCH_HAS_MEMBARRIER_SYNC_CORE
26 select ARCH_HAS_PTE_SPECIAL
27 select ARCH_HAS_SETUP_DMA_OPS
28 select ARCH_HAS_SET_MEMORY
29 select ARCH_HAS_STRICT_KERNEL_RWX
30 select ARCH_HAS_STRICT_MODULE_RWX
31 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
32 select ARCH_HAS_SYNC_DMA_FOR_CPU
33 select ARCH_HAS_SYSCALL_WRAPPER
34 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
35 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
36 select ARCH_HAVE_NMI_SAFE_CMPXCHG
37 select ARCH_INLINE_READ_LOCK if !PREEMPT
38 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
39 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
40 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
41 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
42 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
43 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
44 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
45 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
46 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
47 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
48 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
49 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
50 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
51 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
52 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
53 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
54 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
55 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
56 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
57 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
58 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
59 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
60 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
61 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
62 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
63 select ARCH_KEEP_MEMBLOCK
64 select ARCH_USE_CMPXCHG_LOCKREF
65 select ARCH_USE_QUEUED_RWLOCKS
66 select ARCH_USE_QUEUED_SPINLOCKS
67 select ARCH_SUPPORTS_MEMORY_FAILURE
68 select ARCH_SUPPORTS_ATOMIC_RMW
69 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
70 select ARCH_SUPPORTS_NUMA_BALANCING
71 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
72 select ARCH_WANT_FRAME_POINTERS
73 select ARCH_HAS_UBSAN_SANITIZE_ALL
77 select AUDIT_ARCH_COMPAT_GENERIC
78 select ARM_GIC_V2M if PCI
80 select ARM_GIC_V3_ITS if PCI
82 select BUILDTIME_EXTABLE_SORT
83 select CLONE_BACKWARDS
85 select CPU_PM if (SUSPEND || CPU_IDLE)
87 select DCACHE_WORD_ACCESS
88 select DMA_DIRECT_REMAP
91 select GENERIC_ALLOCATOR
92 select GENERIC_ARCH_TOPOLOGY
93 select GENERIC_CLOCKEVENTS
94 select GENERIC_CLOCKEVENTS_BROADCAST
95 select GENERIC_CPU_AUTOPROBE
96 select GENERIC_CPU_VULNERABILITIES
97 select GENERIC_EARLY_IOREMAP
98 select GENERIC_IDLE_POLL_SETUP
99 select GENERIC_IRQ_MULTI_HANDLER
100 select GENERIC_IRQ_PROBE
101 select GENERIC_IRQ_SHOW
102 select GENERIC_IRQ_SHOW_LEVEL
103 select GENERIC_PCI_IOMAP
104 select GENERIC_SCHED_CLOCK
105 select GENERIC_SMP_IDLE_THREAD
106 select GENERIC_STRNCPY_FROM_USER
107 select GENERIC_STRNLEN_USER
108 select GENERIC_TIME_VSYSCALL
109 select HANDLE_DOMAIN_IRQ
110 select HARDIRQS_SW_RESEND
112 select HAVE_ACPI_APEI if (ACPI && EFI)
113 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
114 select HAVE_ARCH_AUDITSYSCALL
115 select HAVE_ARCH_BITREVERSE
116 select HAVE_ARCH_HUGE_VMAP
117 select HAVE_ARCH_JUMP_LABEL
118 select HAVE_ARCH_JUMP_LABEL_RELATIVE
119 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
120 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
121 select HAVE_ARCH_KGDB
122 select HAVE_ARCH_MMAP_RND_BITS
123 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
124 select HAVE_ARCH_PREL32_RELOCATIONS
125 select HAVE_ARCH_SECCOMP_FILTER
126 select HAVE_ARCH_STACKLEAK
127 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
128 select HAVE_ARCH_TRACEHOOK
129 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
130 select HAVE_ARCH_VMAP_STACK
131 select HAVE_ARM_SMCCC
133 select HAVE_C_RECORDMCOUNT
134 select HAVE_CMPXCHG_DOUBLE
135 select HAVE_CMPXCHG_LOCAL
136 select HAVE_CONTEXT_TRACKING
137 select HAVE_DEBUG_BUGVERBOSE
138 select HAVE_DEBUG_KMEMLEAK
139 select HAVE_DMA_CONTIGUOUS
140 select HAVE_DYNAMIC_FTRACE
141 select HAVE_EFFICIENT_UNALIGNED_ACCESS
142 select HAVE_FTRACE_MCOUNT_RECORD
143 select HAVE_FUNCTION_TRACER
144 select HAVE_FUNCTION_GRAPH_TRACER
145 select HAVE_GCC_PLUGINS
146 select HAVE_HW_BREAKPOINT if PERF_EVENTS
147 select HAVE_IRQ_TIME_ACCOUNTING
148 select HAVE_MEMBLOCK_NODE_MAP if NUMA
150 select HAVE_PATA_PLATFORM
151 select HAVE_PERF_EVENTS
152 select HAVE_PERF_REGS
153 select HAVE_PERF_USER_STACK_DUMP
154 select HAVE_REGS_AND_STACK_ACCESS_API
155 select HAVE_FUNCTION_ARG_ACCESS_API
156 select HAVE_RCU_TABLE_FREE
158 select HAVE_STACKPROTECTOR
159 select HAVE_SYSCALL_TRACEPOINTS
161 select HAVE_KRETPROBES
162 select IOMMU_DMA if IOMMU_SUPPORT
164 select IRQ_FORCED_THREADING
165 select MODULES_USE_ELF_RELA
166 select NEED_DMA_MAP_STATE
167 select NEED_SG_DMA_LENGTH
169 select OF_EARLY_FLATTREE
170 select PCI_DOMAINS_GENERIC if PCI
171 select PCI_ECAM if (ACPI && PCI)
172 select PCI_SYSCALL if PCI
178 select SYSCTL_EXCEPTION_TRACE
179 select THREAD_INFO_IN_TASK
181 ARM 64-bit (AArch64) Linux support.
189 config ARM64_PAGE_SHIFT
191 default 16 if ARM64_64K_PAGES
192 default 14 if ARM64_16K_PAGES
195 config ARM64_CONT_SHIFT
197 default 5 if ARM64_64K_PAGES
198 default 7 if ARM64_16K_PAGES
201 config ARCH_MMAP_RND_BITS_MIN
202 default 14 if ARM64_64K_PAGES
203 default 16 if ARM64_16K_PAGES
206 # max bits determined by the following formula:
207 # VA_BITS - PAGE_SHIFT - 3
208 config ARCH_MMAP_RND_BITS_MAX
209 default 19 if ARM64_VA_BITS=36
210 default 24 if ARM64_VA_BITS=39
211 default 27 if ARM64_VA_BITS=42
212 default 30 if ARM64_VA_BITS=47
213 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
214 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
215 default 33 if ARM64_VA_BITS=48
216 default 14 if ARM64_64K_PAGES
217 default 16 if ARM64_16K_PAGES
220 config ARCH_MMAP_RND_COMPAT_BITS_MIN
221 default 7 if ARM64_64K_PAGES
222 default 9 if ARM64_16K_PAGES
225 config ARCH_MMAP_RND_COMPAT_BITS_MAX
231 config STACKTRACE_SUPPORT
234 config ILLEGAL_POINTER_VALUE
236 default 0xdead000000000000
238 config LOCKDEP_SUPPORT
241 config TRACE_IRQFLAGS_SUPPORT
248 config GENERIC_BUG_RELATIVE_POINTERS
250 depends on GENERIC_BUG
252 config GENERIC_HWEIGHT
258 config GENERIC_CALIBRATE_DELAY
264 config HAVE_GENERIC_GUP
267 config ARCH_ENABLE_MEMORY_HOTPLUG
273 config KERNEL_MODE_NEON
276 config FIX_EARLYCON_MEM
279 config PGTABLE_LEVELS
281 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
282 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
283 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_USER_VA_BITS_52)
284 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
285 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
286 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
288 config ARCH_SUPPORTS_UPROBES
291 config ARCH_PROC_KCORE_TEXT
294 source "arch/arm64/Kconfig.platforms"
296 menu "Kernel Features"
298 menu "ARM errata workarounds via the alternatives framework"
300 config ARM64_WORKAROUND_CLEAN_CACHE
303 config ARM64_ERRATUM_826319
304 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
306 select ARM64_WORKAROUND_CLEAN_CACHE
308 This option adds an alternative code sequence to work around ARM
309 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
310 AXI master interface and an L2 cache.
312 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
313 and is unable to accept a certain write via this interface, it will
314 not progress on read data presented on the read data channel and the
317 The workaround promotes data cache clean instructions to
318 data cache clean-and-invalidate.
319 Please note that this does not necessarily enable the workaround,
320 as it depends on the alternative framework, which will only patch
321 the kernel if an affected CPU is detected.
325 config ARM64_ERRATUM_827319
326 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
328 select ARM64_WORKAROUND_CLEAN_CACHE
330 This option adds an alternative code sequence to work around ARM
331 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
332 master interface and an L2 cache.
334 Under certain conditions this erratum can cause a clean line eviction
335 to occur at the same time as another transaction to the same address
336 on the AMBA 5 CHI interface, which can cause data corruption if the
337 interconnect reorders the two transactions.
339 The workaround promotes data cache clean instructions to
340 data cache clean-and-invalidate.
341 Please note that this does not necessarily enable the workaround,
342 as it depends on the alternative framework, which will only patch
343 the kernel if an affected CPU is detected.
347 config ARM64_ERRATUM_824069
348 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
350 select ARM64_WORKAROUND_CLEAN_CACHE
352 This option adds an alternative code sequence to work around ARM
353 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
354 to a coherent interconnect.
356 If a Cortex-A53 processor is executing a store or prefetch for
357 write instruction at the same time as a processor in another
358 cluster is executing a cache maintenance operation to the same
359 address, then this erratum might cause a clean cache line to be
360 incorrectly marked as dirty.
362 The workaround promotes data cache clean instructions to
363 data cache clean-and-invalidate.
364 Please note that this option does not necessarily enable the
365 workaround, as it depends on the alternative framework, which will
366 only patch the kernel if an affected CPU is detected.
370 config ARM64_ERRATUM_819472
371 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
373 select ARM64_WORKAROUND_CLEAN_CACHE
375 This option adds an alternative code sequence to work around ARM
376 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
377 present when it is connected to a coherent interconnect.
379 If the processor is executing a load and store exclusive sequence at
380 the same time as a processor in another cluster is executing a cache
381 maintenance operation to the same address, then this erratum might
382 cause data corruption.
384 The workaround promotes data cache clean instructions to
385 data cache clean-and-invalidate.
386 Please note that this does not necessarily enable the workaround,
387 as it depends on the alternative framework, which will only patch
388 the kernel if an affected CPU is detected.
392 config ARM64_ERRATUM_832075
393 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
396 This option adds an alternative code sequence to work around ARM
397 erratum 832075 on Cortex-A57 parts up to r1p2.
399 Affected Cortex-A57 parts might deadlock when exclusive load/store
400 instructions to Write-Back memory are mixed with Device loads.
402 The workaround is to promote device loads to use Load-Acquire
404 Please note that this does not necessarily enable the workaround,
405 as it depends on the alternative framework, which will only patch
406 the kernel if an affected CPU is detected.
410 config ARM64_ERRATUM_834220
411 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
415 This option adds an alternative code sequence to work around ARM
416 erratum 834220 on Cortex-A57 parts up to r1p2.
418 Affected Cortex-A57 parts might report a Stage 2 translation
419 fault as the result of a Stage 1 fault for load crossing a
420 page boundary when there is a permission or device memory
421 alignment fault at Stage 1 and a translation fault at Stage 2.
423 The workaround is to verify that the Stage 1 translation
424 doesn't generate a fault before handling the Stage 2 fault.
425 Please note that this does not necessarily enable the workaround,
426 as it depends on the alternative framework, which will only patch
427 the kernel if an affected CPU is detected.
431 config ARM64_ERRATUM_845719
432 bool "Cortex-A53: 845719: a load might read incorrect data"
436 This option adds an alternative code sequence to work around ARM
437 erratum 845719 on Cortex-A53 parts up to r0p4.
439 When running a compat (AArch32) userspace on an affected Cortex-A53
440 part, a load at EL0 from a virtual address that matches the bottom 32
441 bits of the virtual address used by a recent load at (AArch64) EL1
442 might return incorrect data.
444 The workaround is to write the contextidr_el1 register on exception
445 return to a 32-bit task.
446 Please note that this does not necessarily enable the workaround,
447 as it depends on the alternative framework, which will only patch
448 the kernel if an affected CPU is detected.
452 config ARM64_ERRATUM_843419
453 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
455 select ARM64_MODULE_PLTS if MODULES
457 This option links the kernel with '--fix-cortex-a53-843419' and
458 enables PLT support to replace certain ADRP instructions, which can
459 cause subsequent memory accesses to use an incorrect address on
460 Cortex-A53 parts up to r0p4.
464 config ARM64_ERRATUM_1024718
465 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
468 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
470 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
471 update of the hardware dirty bit when the DBM/AP bits are updated
472 without a break-before-make. The workaround is to disable the usage
473 of hardware DBM locally on the affected cores. CPUs not affected by
474 this erratum will continue to use the feature.
478 config ARM64_ERRATUM_1188873
479 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
482 select ARM_ARCH_TIMER_OOL_WORKAROUND
484 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
487 Affected Cortex-A76/Neoverse-N1 cores (r0p0, r1p0, r2p0) could
488 cause register corruption when accessing the timer registers
489 from AArch32 userspace.
493 config ARM64_ERRATUM_1165522
494 bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
497 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
499 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
500 corrupted TLBs by speculating an AT instruction during a guest
505 config ARM64_ERRATUM_1286807
506 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
508 select ARM64_WORKAROUND_REPEAT_TLBI
510 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
512 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
513 address for a cacheable mapping of a location is being
514 accessed by a core while another core is remapping the virtual
515 address to a new physical page using the recommended
516 break-before-make sequence, then under very rare circumstances
517 TLBI+DSB completes before a read using the translation being
518 invalidated has been observed by other observers. The
519 workaround repeats the TLBI+DSB operation.
523 config CAVIUM_ERRATUM_22375
524 bool "Cavium erratum 22375, 24313"
527 Enable workaround for errata 22375 and 24313.
529 This implements two gicv3-its errata workarounds for ThunderX. Both
530 with a small impact affecting only ITS table allocation.
532 erratum 22375: only alloc 8MB table size
533 erratum 24313: ignore memory access type
535 The fixes are in ITS initialization and basically ignore memory access
536 type and table size provided by the TYPER and BASER registers.
540 config CAVIUM_ERRATUM_23144
541 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
545 ITS SYNC command hang for cross node io and collections/cpu mapping.
549 config CAVIUM_ERRATUM_23154
550 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
553 The gicv3 of ThunderX requires a modified version for
554 reading the IAR status to ensure data synchronization
555 (access to icc_iar1_el1 is not sync'ed before and after).
559 config CAVIUM_ERRATUM_27456
560 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
563 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
564 instructions may cause the icache to become corrupted if it
565 contains data for a non-current ASID. The fix is to
566 invalidate the icache when changing the mm context.
570 config CAVIUM_ERRATUM_30115
571 bool "Cavium erratum 30115: Guest may disable interrupts in host"
574 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
575 1.2, and T83 Pass 1.0, KVM guest execution may disable
576 interrupts in host. Trapping both GICv3 group-0 and group-1
577 accesses sidesteps the issue.
581 config QCOM_FALKOR_ERRATUM_1003
582 bool "Falkor E1003: Incorrect translation due to ASID change"
585 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
586 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
587 in TTBR1_EL1, this situation only occurs in the entry trampoline and
588 then only for entries in the walk cache, since the leaf translation
589 is unchanged. Work around the erratum by invalidating the walk cache
590 entries for the trampoline before entering the kernel proper.
592 config ARM64_WORKAROUND_REPEAT_TLBI
595 config QCOM_FALKOR_ERRATUM_1009
596 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
598 select ARM64_WORKAROUND_REPEAT_TLBI
600 On Falkor v1, the CPU may prematurely complete a DSB following a
601 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
602 one more time to fix the issue.
606 config QCOM_QDF2400_ERRATUM_0065
607 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
610 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
611 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
612 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
616 config SOCIONEXT_SYNQUACER_PREITS
617 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
620 Socionext Synquacer SoCs implement a separate h/w block to generate
621 MSI doorbell writes with non-zero values for the device ID.
625 config HISILICON_ERRATUM_161600802
626 bool "Hip07 161600802: Erroneous redistributor VLPI base"
629 The HiSilicon Hip07 SoC uses the wrong redistributor base
630 when issued ITS commands such as VMOVP and VMAPP, and requires
631 a 128kB offset to be applied to the target address in this commands.
635 config QCOM_FALKOR_ERRATUM_E1041
636 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
639 Falkor CPU may speculatively fetch instructions from an improper
640 memory location when MMU translation is changed from SCTLR_ELn[M]=1
641 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
645 config FUJITSU_ERRATUM_010001
646 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
649 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
650 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
651 accesses may cause undefined fault (Data abort, DFSC=0b111111).
652 This fault occurs under a specific hardware condition when a
653 load/store instruction performs an address translation using:
654 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
655 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
656 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
657 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
659 The workaround is to ensure these bits are clear in TCR_ELx.
660 The workaround only affects the Fujitsu-A64FX.
669 default ARM64_4K_PAGES
671 Page size (translation granule) configuration.
673 config ARM64_4K_PAGES
676 This feature enables 4KB pages support.
678 config ARM64_16K_PAGES
681 The system will use 16KB pages support. AArch32 emulation
682 requires applications compiled with 16K (or a multiple of 16K)
685 config ARM64_64K_PAGES
688 This feature enables 64KB pages support (4KB by default)
689 allowing only two levels of page tables and faster TLB
690 look-up. AArch32 emulation requires applications compiled
691 with 64K aligned segments.
696 prompt "Virtual address space size"
697 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
698 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
699 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
701 Allows choosing one of multiple possible virtual address
702 space sizes. The level of translation table is determined by
703 a combination of page size and virtual address space size.
705 config ARM64_VA_BITS_36
706 bool "36-bit" if EXPERT
707 depends on ARM64_16K_PAGES
709 config ARM64_VA_BITS_39
711 depends on ARM64_4K_PAGES
713 config ARM64_VA_BITS_42
715 depends on ARM64_64K_PAGES
717 config ARM64_VA_BITS_47
719 depends on ARM64_16K_PAGES
721 config ARM64_VA_BITS_48
724 config ARM64_USER_VA_BITS_52
726 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
728 Enable 52-bit virtual addressing for userspace when explicitly
729 requested via a hint to mmap(). The kernel will continue to
730 use 48-bit virtual addresses for its own mappings.
732 NOTE: Enabling 52-bit virtual addressing in conjunction with
733 ARMv8.3 Pointer Authentication will result in the PAC being
734 reduced from 7 bits to 3 bits, which may have a significant
735 impact on its susceptibility to brute-force attacks.
737 If unsure, select 48-bit virtual addressing instead.
741 config ARM64_FORCE_52BIT
742 bool "Force 52-bit virtual addresses for userspace"
743 depends on ARM64_USER_VA_BITS_52 && EXPERT
745 For systems with 52-bit userspace VAs enabled, the kernel will attempt
746 to maintain compatibility with older software by providing 48-bit VAs
747 unless a hint is supplied to mmap.
749 This configuration option disables the 48-bit compatibility logic, and
750 forces all userspace addresses to be 52-bit on HW that supports it. One
751 should only enable this configuration option for stress testing userspace
752 memory management code. If unsure say N here.
756 default 36 if ARM64_VA_BITS_36
757 default 39 if ARM64_VA_BITS_39
758 default 42 if ARM64_VA_BITS_42
759 default 47 if ARM64_VA_BITS_47
760 default 48 if ARM64_VA_BITS_48 || ARM64_USER_VA_BITS_52
763 prompt "Physical address space size"
764 default ARM64_PA_BITS_48
766 Choose the maximum physical address range that the kernel will
769 config ARM64_PA_BITS_48
772 config ARM64_PA_BITS_52
773 bool "52-bit (ARMv8.2)"
774 depends on ARM64_64K_PAGES
775 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
777 Enable support for a 52-bit physical address space, introduced as
778 part of the ARMv8.2-LPA extension.
780 With this enabled, the kernel will also continue to work on CPUs that
781 do not support ARMv8.2-LPA, but with some added memory overhead (and
782 minor performance overhead).
788 default 48 if ARM64_PA_BITS_48
789 default 52 if ARM64_PA_BITS_52
791 config CPU_BIG_ENDIAN
792 bool "Build big-endian kernel"
794 Say Y if you plan on running a kernel in big-endian mode.
797 bool "Multi-core scheduler support"
799 Multi-core scheduler support improves the CPU scheduler's decision
800 making when dealing with multi-core CPU chips at a cost of slightly
801 increased overhead in some places. If unsure say N here.
804 bool "SMT scheduler support"
806 Improves the CPU scheduler's decision making when dealing with
807 MultiThreading at a cost of slightly increased overhead in some
808 places. If unsure say N here.
811 int "Maximum number of CPUs (2-4096)"
816 bool "Support for hot-pluggable CPUs"
817 select GENERIC_IRQ_MIGRATION
819 Say Y here to experiment with turning CPUs off and on. CPUs
820 can be controlled through /sys/devices/system/cpu.
822 # Common NUMA Features
824 bool "Numa Memory Allocation and Scheduler Support"
825 select ACPI_NUMA if ACPI
828 Enable NUMA (Non Uniform Memory Access) support.
830 The kernel will try to allocate memory used by a CPU on the
831 local memory of the CPU and add some more
832 NUMA awareness to the kernel.
835 int "Maximum NUMA Nodes (as a power of 2)"
838 depends on NEED_MULTIPLE_NODES
840 Specify the maximum number of NUMA Nodes available on the target
841 system. Increases memory reserved to accommodate various tables.
843 config USE_PERCPU_NUMA_NODE_ID
847 config HAVE_SETUP_PER_CPU_AREA
851 config NEED_PER_CPU_EMBED_FIRST_CHUNK
858 source "kernel/Kconfig.hz"
860 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
863 config ARCH_SPARSEMEM_ENABLE
865 select SPARSEMEM_VMEMMAP_ENABLE
867 config ARCH_SPARSEMEM_DEFAULT
868 def_bool ARCH_SPARSEMEM_ENABLE
870 config ARCH_SELECT_MEMORY_MODEL
871 def_bool ARCH_SPARSEMEM_ENABLE
873 config ARCH_FLATMEM_ENABLE
876 config HAVE_ARCH_PFN_VALID
879 config HW_PERF_EVENTS
883 config SYS_SUPPORTS_HUGETLBFS
886 config ARCH_WANT_HUGE_PMD_SHARE
887 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
889 config ARCH_HAS_CACHE_LINE_SIZE
892 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
893 def_bool y if PGTABLE_LEVELS > 2
896 bool "Enable seccomp to safely compute untrusted bytecode"
898 This kernel feature is useful for number crunching applications
899 that may need to compute untrusted bytecode during their
900 execution. By using pipes or other transports made available to
901 the process as file descriptors supporting the read/write
902 syscalls, it's possible to isolate those applications in
903 their own address space using seccomp. Once seccomp is
904 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
905 and the task is only allowed to execute a few safe syscalls
906 defined by each seccomp mode.
909 bool "Enable paravirtualization code"
911 This changes the kernel so it can modify itself when it is run
912 under a hypervisor, potentially improving performance significantly
913 over full virtualization.
915 config PARAVIRT_TIME_ACCOUNTING
916 bool "Paravirtual steal time accounting"
920 Select this option to enable fine granularity task steal time
921 accounting. Time spent executing other tasks in parallel with
922 the current vCPU is discounted from the vCPU power. To account for
923 that, there can be a small performance impact.
925 If in doubt, say N here.
928 depends on PM_SLEEP_SMP
930 bool "kexec system call"
932 kexec is a system call that implements the ability to shutdown your
933 current kernel, and to start another kernel. It is like a reboot
934 but it is independent of the system firmware. And like a reboot
935 you can start any kernel with it, not just Linux.
938 bool "kexec file based system call"
941 This is new version of kexec system call. This system call is
942 file based and takes file descriptors as system call argument
943 for kernel and initramfs as opposed to list of segments as
944 accepted by previous system call.
946 config KEXEC_VERIFY_SIG
947 bool "Verify kernel signature during kexec_file_load() syscall"
948 depends on KEXEC_FILE
950 Select this option to verify a signature with loaded kernel
951 image. If configured, any attempt of loading a image without
952 valid signature will fail.
954 In addition to that option, you need to enable signature
955 verification for the corresponding kernel image type being
956 loaded in order for this to work.
958 config KEXEC_IMAGE_VERIFY_SIG
959 bool "Enable Image signature verification support"
961 depends on KEXEC_VERIFY_SIG
962 depends on EFI && SIGNED_PE_FILE_VERIFICATION
964 Enable Image signature verification support.
966 comment "Support for PE file signature verification disabled"
967 depends on KEXEC_VERIFY_SIG
968 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
971 bool "Build kdump crash kernel"
973 Generate crash dump after being started by kexec. This should
974 be normally only set in special crash dump kernels which are
975 loaded in the main kernel with kexec-tools into a specially
976 reserved region and then later executed after a crash by
979 For more details see Documentation/kdump/kdump.txt
986 bool "Xen guest support on ARM64"
987 depends on ARM64 && OF
991 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
993 config FORCE_MAX_ZONEORDER
995 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
996 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
999 The kernel memory allocator divides physically contiguous memory
1000 blocks into "zones", where each zone is a power of two number of
1001 pages. This option selects the largest power of two that the kernel
1002 keeps in the memory allocator. If you need to allocate very large
1003 blocks of physically contiguous memory, then you may need to
1004 increase this value.
1006 This config option is actually maximum order plus one. For example,
1007 a value of 11 means that the largest free memory block is 2^10 pages.
1009 We make sure that we can allocate upto a HugePage size for each configuration.
1011 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1013 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1014 4M allocations matching the default size used by generic code.
1016 config UNMAP_KERNEL_AT_EL0
1017 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1020 Speculation attacks against some high-performance processors can
1021 be used to bypass MMU permission checks and leak kernel data to
1022 userspace. This can be defended against by unmapping the kernel
1023 when running in userspace, mapping it back in on exception entry
1024 via a trampoline page in the vector table.
1028 config HARDEN_BRANCH_PREDICTOR
1029 bool "Harden the branch predictor against aliasing attacks" if EXPERT
1032 Speculation attacks against some high-performance processors rely on
1033 being able to manipulate the branch predictor for a victim context by
1034 executing aliasing branches in the attacker context. Such attacks
1035 can be partially mitigated against by clearing internal branch
1036 predictor state and limiting the prediction logic in some situations.
1038 This config option will take CPU-specific actions to harden the
1039 branch predictor against aliasing attacks and may rely on specific
1040 instruction sequences or control bits being set by the system
1045 config HARDEN_EL2_VECTORS
1046 bool "Harden EL2 vector mapping against system register leak" if EXPERT
1049 Speculation attacks against some high-performance processors can
1050 be used to leak privileged information such as the vector base
1051 register, resulting in a potential defeat of the EL2 layout
1054 This config option will map the vectors to a fixed location,
1055 independent of the EL2 code mapping, so that revealing VBAR_EL2
1056 to an attacker does not give away any extra information. This
1057 only gets enabled on affected CPUs.
1062 bool "Speculative Store Bypass Disable" if EXPERT
1065 This enables mitigation of the bypassing of previous stores
1066 by speculative loads.
1070 config RODATA_FULL_DEFAULT_ENABLED
1071 bool "Apply r/o permissions of VM areas also to their linear aliases"
1074 Apply read-only attributes of VM areas to the linear alias of
1075 the backing pages as well. This prevents code or read-only data
1076 from being modified (inadvertently or intentionally) via another
1077 mapping of the same memory page. This additional enhancement can
1078 be turned off at runtime by passing rodata=[off|on] (and turned on
1079 with rodata=full if this option is set to 'n')
1081 This requires the linear region to be mapped down to pages,
1082 which may adversely affect performance in some cases.
1084 config ARM64_SW_TTBR0_PAN
1085 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1087 Enabling this option prevents the kernel from accessing
1088 user-space memory directly by pointing TTBR0_EL1 to a reserved
1089 zeroed area and reserved ASID. The user access routines
1090 restore the valid TTBR0_EL1 temporarily.
1093 bool "Kernel support for 32-bit EL0"
1094 depends on ARM64_4K_PAGES || EXPERT
1095 select COMPAT_BINFMT_ELF if BINFMT_ELF
1097 select OLD_SIGSUSPEND3
1098 select COMPAT_OLD_SIGACTION
1100 This option enables support for a 32-bit EL0 running under a 64-bit
1101 kernel at EL1. AArch32-specific components such as system calls,
1102 the user helper functions, VFP support and the ptrace interface are
1103 handled appropriately by the kernel.
1105 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1106 that you will only be able to execute AArch32 binaries that were compiled
1107 with page size aligned segments.
1109 If you want to execute 32-bit userspace applications, say Y.
1113 config KUSER_HELPERS
1114 bool "Enable kuser helpers page for 32 bit applications"
1117 Warning: disabling this option may break 32-bit user programs.
1119 Provide kuser helpers to compat tasks. The kernel provides
1120 helper code to userspace in read only form at a fixed location
1121 to allow userspace to be independent of the CPU type fitted to
1122 the system. This permits binaries to be run on ARMv4 through
1123 to ARMv8 without modification.
1125 See Documentation/arm/kernel_user_helpers.txt for details.
1127 However, the fixed address nature of these helpers can be used
1128 by ROP (return orientated programming) authors when creating
1131 If all of the binaries and libraries which run on your platform
1132 are built specifically for your platform, and make no use of
1133 these helpers, then you can turn this option off to hinder
1134 such exploits. However, in that case, if a binary or library
1135 relying on those helpers is run, it will not function correctly.
1137 Say N here only if you are absolutely certain that you do not
1138 need these helpers; otherwise, the safe option is to say Y.
1141 menuconfig ARMV8_DEPRECATED
1142 bool "Emulate deprecated/obsolete ARMv8 instructions"
1145 Legacy software support may require certain instructions
1146 that have been deprecated or obsoleted in the architecture.
1148 Enable this config to enable selective emulation of these
1155 config SWP_EMULATION
1156 bool "Emulate SWP/SWPB instructions"
1158 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1159 they are always undefined. Say Y here to enable software
1160 emulation of these instructions for userspace using LDXR/STXR.
1162 In some older versions of glibc [<=2.8] SWP is used during futex
1163 trylock() operations with the assumption that the code will not
1164 be preempted. This invalid assumption may be more likely to fail
1165 with SWP emulation enabled, leading to deadlock of the user
1168 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1169 on an external transaction monitoring block called a global
1170 monitor to maintain update atomicity. If your system does not
1171 implement a global monitor, this option can cause programs that
1172 perform SWP operations to uncached memory to deadlock.
1176 config CP15_BARRIER_EMULATION
1177 bool "Emulate CP15 Barrier instructions"
1179 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1180 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1181 strongly recommended to use the ISB, DSB, and DMB
1182 instructions instead.
1184 Say Y here to enable software emulation of these
1185 instructions for AArch32 userspace code. When this option is
1186 enabled, CP15 barrier usage is traced which can help
1187 identify software that needs updating.
1191 config SETEND_EMULATION
1192 bool "Emulate SETEND instruction"
1194 The SETEND instruction alters the data-endianness of the
1195 AArch32 EL0, and is deprecated in ARMv8.
1197 Say Y here to enable software emulation of the instruction
1198 for AArch32 userspace code.
1200 Note: All the cpus on the system must have mixed endian support at EL0
1201 for this feature to be enabled. If a new CPU - which doesn't support mixed
1202 endian - is hotplugged in after this feature has been enabled, there could
1203 be unexpected results in the applications.
1210 menu "ARMv8.1 architectural features"
1212 config ARM64_HW_AFDBM
1213 bool "Support for hardware updates of the Access and Dirty page flags"
1216 The ARMv8.1 architecture extensions introduce support for
1217 hardware updates of the access and dirty information in page
1218 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1219 capable processors, accesses to pages with PTE_AF cleared will
1220 set this bit instead of raising an access flag fault.
1221 Similarly, writes to read-only pages with the DBM bit set will
1222 clear the read-only bit (AP[2]) instead of raising a
1225 Kernels built with this configuration option enabled continue
1226 to work on pre-ARMv8.1 hardware and the performance impact is
1227 minimal. If unsure, say Y.
1230 bool "Enable support for Privileged Access Never (PAN)"
1233 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1234 prevents the kernel or hypervisor from accessing user-space (EL0)
1237 Choosing this option will cause any unprotected (not using
1238 copy_to_user et al) memory access to fail with a permission fault.
1240 The feature is detected at runtime, and will remain as a 'nop'
1241 instruction if the cpu does not implement the feature.
1243 config ARM64_LSE_ATOMICS
1244 bool "Atomic instructions"
1247 As part of the Large System Extensions, ARMv8.1 introduces new
1248 atomic instructions that are designed specifically to scale in
1251 Say Y here to make use of these instructions for the in-kernel
1252 atomic routines. This incurs a small overhead on CPUs that do
1253 not support these instructions and requires the kernel to be
1254 built with binutils >= 2.25 in order for the new instructions
1258 bool "Enable support for Virtualization Host Extensions (VHE)"
1261 Virtualization Host Extensions (VHE) allow the kernel to run
1262 directly at EL2 (instead of EL1) on processors that support
1263 it. This leads to better performance for KVM, as they reduce
1264 the cost of the world switch.
1266 Selecting this option allows the VHE feature to be detected
1267 at runtime, and does not affect processors that do not
1268 implement this feature.
1272 menu "ARMv8.2 architectural features"
1275 bool "Enable support for User Access Override (UAO)"
1278 User Access Override (UAO; part of the ARMv8.2 Extensions)
1279 causes the 'unprivileged' variant of the load/store instructions to
1280 be overridden to be privileged.
1282 This option changes get_user() and friends to use the 'unprivileged'
1283 variant of the load/store instructions. This ensures that user-space
1284 really did have access to the supplied memory. When addr_limit is
1285 set to kernel memory the UAO bit will be set, allowing privileged
1286 access to kernel memory.
1288 Choosing this option will cause copy_to_user() et al to use user-space
1291 The feature is detected at runtime, the kernel will use the
1292 regular load/store instructions if the cpu does not implement the
1296 bool "Enable support for persistent memory"
1297 select ARCH_HAS_PMEM_API
1298 select ARCH_HAS_UACCESS_FLUSHCACHE
1300 Say Y to enable support for the persistent memory API based on the
1301 ARMv8.2 DCPoP feature.
1303 The feature is detected at runtime, and the kernel will use DC CVAC
1304 operations if DC CVAP is not supported (following the behaviour of
1305 DC CVAP itself if the system does not define a point of persistence).
1307 config ARM64_RAS_EXTN
1308 bool "Enable support for RAS CPU Extensions"
1311 CPUs that support the Reliability, Availability and Serviceability
1312 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1313 errors, classify them and report them to software.
1315 On CPUs with these extensions system software can use additional
1316 barriers to determine if faults are pending and read the
1317 classification from a new set of registers.
1319 Selecting this feature will allow the kernel to use these barriers
1320 and access the new registers if the system supports the extension.
1321 Platform RAS features may additionally depend on firmware support.
1324 bool "Enable support for Common Not Private (CNP) translations"
1326 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1328 Common Not Private (CNP) allows translation table entries to
1329 be shared between different PEs in the same inner shareable
1330 domain, so the hardware can use this fact to optimise the
1331 caching of such entries in the TLB.
1333 Selecting this option allows the CNP feature to be detected
1334 at runtime, and does not affect PEs that do not implement
1339 menu "ARMv8.3 architectural features"
1341 config ARM64_PTR_AUTH
1342 bool "Enable support for pointer authentication"
1344 depends on !KVM || ARM64_VHE
1346 Pointer authentication (part of the ARMv8.3 Extensions) provides
1347 instructions for signing and authenticating pointers against secret
1348 keys, which can be used to mitigate Return Oriented Programming (ROP)
1351 This option enables these instructions at EL0 (i.e. for userspace).
1353 Choosing this option will cause the kernel to initialise secret keys
1354 for each process at exec() time, with these keys being
1355 context-switched along with the process.
1357 The feature is detected at runtime. If the feature is not present in
1358 hardware it will not be advertised to userspace/KVM guest nor will it
1359 be enabled. However, KVM guest also require VHE mode and hence
1360 CONFIG_ARM64_VHE=y option to use this feature.
1365 bool "ARM Scalable Vector Extension support"
1367 depends on !KVM || ARM64_VHE
1369 The Scalable Vector Extension (SVE) is an extension to the AArch64
1370 execution state which complements and extends the SIMD functionality
1371 of the base architecture to support much larger vectors and to enable
1372 additional vectorisation opportunities.
1374 To enable use of this extension on CPUs that implement it, say Y.
1376 On CPUs that support the SVE2 extensions, this option will enable
1379 Note that for architectural reasons, firmware _must_ implement SVE
1380 support when running on SVE capable hardware. The required support
1383 * version 1.5 and later of the ARM Trusted Firmware
1384 * the AArch64 boot wrapper since commit 5e1261e08abf
1385 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1387 For other firmware implementations, consult the firmware documentation
1390 If you need the kernel to boot on SVE-capable hardware with broken
1391 firmware, you may need to say N here until you get your firmware
1392 fixed. Otherwise, you may experience firmware panics or lockups when
1393 booting the kernel. If unsure and you are not observing these
1394 symptoms, you should assume that it is safe to say Y.
1396 CPUs that support SVE are architecturally required to support the
1397 Virtualization Host Extensions (VHE), so the kernel makes no
1398 provision for supporting SVE alongside KVM without VHE enabled.
1399 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1400 KVM in the same kernel image.
1402 config ARM64_MODULE_PLTS
1404 select HAVE_MOD_ARCH_SPECIFIC
1406 config ARM64_PSEUDO_NMI
1407 bool "Support for NMI-like interrupts"
1408 select CONFIG_ARM_GIC_V3
1410 Adds support for mimicking Non-Maskable Interrupts through the use of
1411 GIC interrupt priority. This support requires version 3 or later of
1414 This high priority configuration for interrupts needs to be
1415 explicitly enabled by setting the kernel parameter
1416 "irqchip.gicv3_pseudo_nmi" to 1.
1423 This builds the kernel as a Position Independent Executable (PIE),
1424 which retains all relocation metadata required to relocate the
1425 kernel binary at runtime to a different virtual address than the
1426 address it was linked at.
1427 Since AArch64 uses the RELA relocation format, this requires a
1428 relocation pass at runtime even if the kernel is loaded at the
1429 same address it was linked at.
1431 config RANDOMIZE_BASE
1432 bool "Randomize the address of the kernel image"
1433 select ARM64_MODULE_PLTS if MODULES
1436 Randomizes the virtual address at which the kernel image is
1437 loaded, as a security feature that deters exploit attempts
1438 relying on knowledge of the location of kernel internals.
1440 It is the bootloader's job to provide entropy, by passing a
1441 random u64 value in /chosen/kaslr-seed at kernel entry.
1443 When booting via the UEFI stub, it will invoke the firmware's
1444 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1445 to the kernel proper. In addition, it will randomise the physical
1446 location of the kernel Image as well.
1450 config RANDOMIZE_MODULE_REGION_FULL
1451 bool "Randomize the module region over a 4 GB range"
1452 depends on RANDOMIZE_BASE
1455 Randomizes the location of the module region inside a 4 GB window
1456 covering the core kernel. This way, it is less likely for modules
1457 to leak information about the location of core kernel data structures
1458 but it does imply that function calls between modules and the core
1459 kernel will need to be resolved via veneers in the module PLT.
1461 When this option is not set, the module region will be randomized over
1462 a limited range that contains the [_stext, _etext] interval of the
1463 core kernel, so branch relocations are always in range.
1465 config CC_HAVE_STACKPROTECTOR_SYSREG
1466 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1468 config STACKPROTECTOR_PER_TASK
1470 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1476 config ARM64_ACPI_PARKING_PROTOCOL
1477 bool "Enable support for the ARM64 ACPI parking protocol"
1480 Enable support for the ARM64 ACPI parking protocol. If disabled
1481 the kernel will not allow booting through the ARM64 ACPI parking
1482 protocol even if the corresponding data is present in the ACPI
1486 string "Default kernel command string"
1489 Provide a set of default command-line options at build time by
1490 entering them here. As a minimum, you should specify the the
1491 root device (e.g. root=/dev/nfs).
1493 config CMDLINE_FORCE
1494 bool "Always use the default kernel command string"
1496 Always use the default kernel command string, even if the boot
1497 loader passes other arguments to the kernel.
1498 This is useful if you cannot or don't want to change the
1499 command-line options your boot loader passes to the kernel.
1505 bool "UEFI runtime support"
1506 depends on OF && !CPU_BIG_ENDIAN
1507 depends on KERNEL_MODE_NEON
1508 select ARCH_SUPPORTS_ACPI
1511 select EFI_PARAMS_FROM_FDT
1512 select EFI_RUNTIME_WRAPPERS
1517 This option provides support for runtime services provided
1518 by UEFI firmware (such as non-volatile variables, realtime
1519 clock, and platform reset). A UEFI stub is also provided to
1520 allow the kernel to be booted as an EFI application. This
1521 is only useful on systems that have UEFI firmware.
1524 bool "Enable support for SMBIOS (DMI) tables"
1528 This enables SMBIOS/DMI feature for systems.
1530 This option is only useful on systems that have UEFI firmware.
1531 However, even with this option, the resultant kernel should
1532 continue to boot on existing non-UEFI platforms.
1536 config SYSVIPC_COMPAT
1538 depends on COMPAT && SYSVIPC
1540 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1542 depends on HUGETLB_PAGE && MIGRATION
1544 menu "Power management options"
1546 source "kernel/power/Kconfig"
1548 config ARCH_HIBERNATION_POSSIBLE
1552 config ARCH_HIBERNATION_HEADER
1554 depends on HIBERNATION
1556 config ARCH_SUSPEND_POSSIBLE
1561 menu "CPU Power Management"
1563 source "drivers/cpuidle/Kconfig"
1565 source "drivers/cpufreq/Kconfig"
1569 source "drivers/firmware/Kconfig"
1571 source "drivers/acpi/Kconfig"
1573 source "arch/arm64/kvm/Kconfig"
1576 source "arch/arm64/crypto/Kconfig"