3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if ACPI
9 select ACPI_SPCR_TABLE if ACPI
10 select ARCH_CLOCKSOURCE_DATA
11 select ARCH_HAS_DEBUG_VIRTUAL
12 select ARCH_HAS_DEVMEM_IS_ALLOWED
13 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
14 select ARCH_HAS_ELF_RANDOMIZE
15 select ARCH_HAS_FORTIFY_SOURCE
16 select ARCH_HAS_GCOV_PROFILE_ALL
17 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
19 select ARCH_HAS_MEMBARRIER_SYNC_CORE
20 select ARCH_HAS_PTE_SPECIAL
21 select ARCH_HAS_SET_MEMORY
22 select ARCH_HAS_SG_CHAIN
23 select ARCH_HAS_STRICT_KERNEL_RWX
24 select ARCH_HAS_STRICT_MODULE_RWX
25 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
26 select ARCH_HAVE_NMI_SAFE_CMPXCHG
27 select ARCH_INLINE_READ_LOCK if !PREEMPT
28 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
29 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
30 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
31 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
32 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
33 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
34 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
35 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
36 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
37 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
38 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
39 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
40 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
41 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
42 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
43 select ARCH_USE_CMPXCHG_LOCKREF
44 select ARCH_USE_QUEUED_RWLOCKS
45 select ARCH_SUPPORTS_MEMORY_FAILURE
46 select ARCH_SUPPORTS_ATOMIC_RMW
47 select ARCH_SUPPORTS_NUMA_BALANCING
48 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
49 select ARCH_WANT_FRAME_POINTERS
50 select ARCH_HAS_UBSAN_SANITIZE_ALL
54 select AUDIT_ARCH_COMPAT_GENERIC
55 select ARM_GIC_V2M if PCI
57 select ARM_GIC_V3_ITS if PCI
59 select BUILDTIME_EXTABLE_SORT
60 select CLONE_BACKWARDS
62 select CPU_PM if (SUSPEND || CPU_IDLE)
63 select DCACHE_WORD_ACCESS
67 select GENERIC_ALLOCATOR
68 select GENERIC_ARCH_TOPOLOGY
69 select GENERIC_CLOCKEVENTS
70 select GENERIC_CLOCKEVENTS_BROADCAST
71 select GENERIC_CPU_AUTOPROBE
72 select GENERIC_EARLY_IOREMAP
73 select GENERIC_IDLE_POLL_SETUP
74 select GENERIC_IRQ_PROBE
75 select GENERIC_IRQ_SHOW
76 select GENERIC_IRQ_SHOW_LEVEL
77 select GENERIC_PCI_IOMAP
78 select GENERIC_SCHED_CLOCK
79 select GENERIC_SMP_IDLE_THREAD
80 select GENERIC_STRNCPY_FROM_USER
81 select GENERIC_STRNLEN_USER
82 select GENERIC_TIME_VSYSCALL
83 select HANDLE_DOMAIN_IRQ
84 select HARDIRQS_SW_RESEND
85 select HAVE_ACPI_APEI if (ACPI && EFI)
86 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
87 select HAVE_ARCH_AUDITSYSCALL
88 select HAVE_ARCH_BITREVERSE
89 select HAVE_ARCH_HUGE_VMAP
90 select HAVE_ARCH_JUMP_LABEL
91 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
93 select HAVE_ARCH_MMAP_RND_BITS
94 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
95 select HAVE_ARCH_SECCOMP_FILTER
96 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
97 select HAVE_ARCH_TRACEHOOK
98 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
99 select HAVE_ARCH_VMAP_STACK
100 select HAVE_ARM_SMCCC
102 select HAVE_C_RECORDMCOUNT
103 select HAVE_CC_STACKPROTECTOR
104 select HAVE_CMPXCHG_DOUBLE
105 select HAVE_CMPXCHG_LOCAL
106 select HAVE_CONTEXT_TRACKING
107 select HAVE_DEBUG_BUGVERBOSE
108 select HAVE_DEBUG_KMEMLEAK
109 select HAVE_DMA_CONTIGUOUS
110 select HAVE_DYNAMIC_FTRACE
111 select HAVE_EFFICIENT_UNALIGNED_ACCESS
112 select HAVE_FTRACE_MCOUNT_RECORD
113 select HAVE_FUNCTION_TRACER
114 select HAVE_FUNCTION_GRAPH_TRACER
115 select HAVE_GCC_PLUGINS
116 select HAVE_GENERIC_DMA_COHERENT
117 select HAVE_HW_BREAKPOINT if PERF_EVENTS
118 select HAVE_IRQ_TIME_ACCOUNTING
120 select HAVE_MEMBLOCK_NODE_MAP if NUMA
122 select HAVE_PATA_PLATFORM
123 select HAVE_PERF_EVENTS
124 select HAVE_PERF_REGS
125 select HAVE_PERF_USER_STACK_DUMP
126 select HAVE_REGS_AND_STACK_ACCESS_API
127 select HAVE_RCU_TABLE_FREE
128 select HAVE_SYSCALL_TRACEPOINTS
130 select HAVE_KRETPROBES
131 select IOMMU_DMA if IOMMU_SUPPORT
133 select IRQ_FORCED_THREADING
134 select MODULES_USE_ELF_RELA
135 select MULTI_IRQ_HANDLER
136 select NEED_DMA_MAP_STATE
137 select NEED_SG_DMA_LENGTH
140 select OF_EARLY_FLATTREE
141 select OF_RESERVED_MEM
142 select PCI_ECAM if ACPI
148 select SYSCTL_EXCEPTION_TRACE
149 select THREAD_INFO_IN_TASK
151 ARM 64-bit (AArch64) Linux support.
159 config ARM64_PAGE_SHIFT
161 default 16 if ARM64_64K_PAGES
162 default 14 if ARM64_16K_PAGES
165 config ARM64_CONT_SHIFT
167 default 5 if ARM64_64K_PAGES
168 default 7 if ARM64_16K_PAGES
171 config ARCH_MMAP_RND_BITS_MIN
172 default 14 if ARM64_64K_PAGES
173 default 16 if ARM64_16K_PAGES
176 # max bits determined by the following formula:
177 # VA_BITS - PAGE_SHIFT - 3
178 config ARCH_MMAP_RND_BITS_MAX
179 default 19 if ARM64_VA_BITS=36
180 default 24 if ARM64_VA_BITS=39
181 default 27 if ARM64_VA_BITS=42
182 default 30 if ARM64_VA_BITS=47
183 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
184 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
185 default 33 if ARM64_VA_BITS=48
186 default 14 if ARM64_64K_PAGES
187 default 16 if ARM64_16K_PAGES
190 config ARCH_MMAP_RND_COMPAT_BITS_MIN
191 default 7 if ARM64_64K_PAGES
192 default 9 if ARM64_16K_PAGES
195 config ARCH_MMAP_RND_COMPAT_BITS_MAX
201 config STACKTRACE_SUPPORT
204 config ILLEGAL_POINTER_VALUE
206 default 0xdead000000000000
208 config LOCKDEP_SUPPORT
211 config TRACE_IRQFLAGS_SUPPORT
214 config RWSEM_XCHGADD_ALGORITHM
221 config GENERIC_BUG_RELATIVE_POINTERS
223 depends on GENERIC_BUG
225 config GENERIC_HWEIGHT
231 config GENERIC_CALIBRATE_DELAY
237 config HAVE_GENERIC_GUP
243 config KERNEL_MODE_NEON
246 config FIX_EARLYCON_MEM
249 config PGTABLE_LEVELS
251 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
252 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
253 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
254 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
255 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
256 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
258 config ARCH_SUPPORTS_UPROBES
261 config ARCH_PROC_KCORE_TEXT
264 config MULTI_IRQ_HANDLER
267 source "init/Kconfig"
269 source "kernel/Kconfig.freezer"
271 source "arch/arm64/Kconfig.platforms"
278 This feature enables support for PCI bus system. If you say Y
279 here, the kernel will include drivers and infrastructure code
280 to support PCI bus devices.
285 config PCI_DOMAINS_GENERIC
291 source "drivers/pci/Kconfig"
295 menu "Kernel Features"
297 menu "ARM errata workarounds via the alternatives framework"
299 config ARM64_ERRATUM_826319
300 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
303 This option adds an alternative code sequence to work around ARM
304 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
305 AXI master interface and an L2 cache.
307 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
308 and is unable to accept a certain write via this interface, it will
309 not progress on read data presented on the read data channel and the
312 The workaround promotes data cache clean instructions to
313 data cache clean-and-invalidate.
314 Please note that this does not necessarily enable the workaround,
315 as it depends on the alternative framework, which will only patch
316 the kernel if an affected CPU is detected.
320 config ARM64_ERRATUM_827319
321 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
324 This option adds an alternative code sequence to work around ARM
325 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
326 master interface and an L2 cache.
328 Under certain conditions this erratum can cause a clean line eviction
329 to occur at the same time as another transaction to the same address
330 on the AMBA 5 CHI interface, which can cause data corruption if the
331 interconnect reorders the two transactions.
333 The workaround promotes data cache clean instructions to
334 data cache clean-and-invalidate.
335 Please note that this does not necessarily enable the workaround,
336 as it depends on the alternative framework, which will only patch
337 the kernel if an affected CPU is detected.
341 config ARM64_ERRATUM_824069
342 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
345 This option adds an alternative code sequence to work around ARM
346 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
347 to a coherent interconnect.
349 If a Cortex-A53 processor is executing a store or prefetch for
350 write instruction at the same time as a processor in another
351 cluster is executing a cache maintenance operation to the same
352 address, then this erratum might cause a clean cache line to be
353 incorrectly marked as dirty.
355 The workaround promotes data cache clean instructions to
356 data cache clean-and-invalidate.
357 Please note that this option does not necessarily enable the
358 workaround, as it depends on the alternative framework, which will
359 only patch the kernel if an affected CPU is detected.
363 config ARM64_ERRATUM_819472
364 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
367 This option adds an alternative code sequence to work around ARM
368 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
369 present when it is connected to a coherent interconnect.
371 If the processor is executing a load and store exclusive sequence at
372 the same time as a processor in another cluster is executing a cache
373 maintenance operation to the same address, then this erratum might
374 cause data corruption.
376 The workaround promotes data cache clean instructions to
377 data cache clean-and-invalidate.
378 Please note that this does not necessarily enable the workaround,
379 as it depends on the alternative framework, which will only patch
380 the kernel if an affected CPU is detected.
384 config ARM64_ERRATUM_832075
385 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
388 This option adds an alternative code sequence to work around ARM
389 erratum 832075 on Cortex-A57 parts up to r1p2.
391 Affected Cortex-A57 parts might deadlock when exclusive load/store
392 instructions to Write-Back memory are mixed with Device loads.
394 The workaround is to promote device loads to use Load-Acquire
396 Please note that this does not necessarily enable the workaround,
397 as it depends on the alternative framework, which will only patch
398 the kernel if an affected CPU is detected.
402 config ARM64_ERRATUM_834220
403 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
407 This option adds an alternative code sequence to work around ARM
408 erratum 834220 on Cortex-A57 parts up to r1p2.
410 Affected Cortex-A57 parts might report a Stage 2 translation
411 fault as the result of a Stage 1 fault for load crossing a
412 page boundary when there is a permission or device memory
413 alignment fault at Stage 1 and a translation fault at Stage 2.
415 The workaround is to verify that the Stage 1 translation
416 doesn't generate a fault before handling the Stage 2 fault.
417 Please note that this does not necessarily enable the workaround,
418 as it depends on the alternative framework, which will only patch
419 the kernel if an affected CPU is detected.
423 config ARM64_ERRATUM_845719
424 bool "Cortex-A53: 845719: a load might read incorrect data"
428 This option adds an alternative code sequence to work around ARM
429 erratum 845719 on Cortex-A53 parts up to r0p4.
431 When running a compat (AArch32) userspace on an affected Cortex-A53
432 part, a load at EL0 from a virtual address that matches the bottom 32
433 bits of the virtual address used by a recent load at (AArch64) EL1
434 might return incorrect data.
436 The workaround is to write the contextidr_el1 register on exception
437 return to a 32-bit task.
438 Please note that this does not necessarily enable the workaround,
439 as it depends on the alternative framework, which will only patch
440 the kernel if an affected CPU is detected.
444 config ARM64_ERRATUM_843419
445 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
447 select ARM64_MODULE_PLTS if MODULES
449 This option links the kernel with '--fix-cortex-a53-843419' and
450 enables PLT support to replace certain ADRP instructions, which can
451 cause subsequent memory accesses to use an incorrect address on
452 Cortex-A53 parts up to r0p4.
456 config ARM64_ERRATUM_1024718
457 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
460 This option adds work around for Arm Cortex-A55 Erratum 1024718.
462 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
463 update of the hardware dirty bit when the DBM/AP bits are updated
464 without a break-before-make. The work around is to disable the usage
465 of hardware DBM locally on the affected cores. CPUs not affected by
466 erratum will continue to use the feature.
470 config CAVIUM_ERRATUM_22375
471 bool "Cavium erratum 22375, 24313"
474 Enable workaround for erratum 22375, 24313.
476 This implements two gicv3-its errata workarounds for ThunderX. Both
477 with small impact affecting only ITS table allocation.
479 erratum 22375: only alloc 8MB table size
480 erratum 24313: ignore memory access type
482 The fixes are in ITS initialization and basically ignore memory access
483 type and table size provided by the TYPER and BASER registers.
487 config CAVIUM_ERRATUM_23144
488 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
492 ITS SYNC command hang for cross node io and collections/cpu mapping.
496 config CAVIUM_ERRATUM_23154
497 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
500 The gicv3 of ThunderX requires a modified version for
501 reading the IAR status to ensure data synchronization
502 (access to icc_iar1_el1 is not sync'ed before and after).
506 config CAVIUM_ERRATUM_27456
507 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
510 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
511 instructions may cause the icache to become corrupted if it
512 contains data for a non-current ASID. The fix is to
513 invalidate the icache when changing the mm context.
517 config CAVIUM_ERRATUM_30115
518 bool "Cavium erratum 30115: Guest may disable interrupts in host"
521 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
522 1.2, and T83 Pass 1.0, KVM guest execution may disable
523 interrupts in host. Trapping both GICv3 group-0 and group-1
524 accesses sidesteps the issue.
528 config QCOM_FALKOR_ERRATUM_1003
529 bool "Falkor E1003: Incorrect translation due to ASID change"
532 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
533 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
534 in TTBR1_EL1, this situation only occurs in the entry trampoline and
535 then only for entries in the walk cache, since the leaf translation
536 is unchanged. Work around the erratum by invalidating the walk cache
537 entries for the trampoline before entering the kernel proper.
539 config QCOM_FALKOR_ERRATUM_1009
540 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
543 On Falkor v1, the CPU may prematurely complete a DSB following a
544 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
545 one more time to fix the issue.
549 config QCOM_QDF2400_ERRATUM_0065
550 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
553 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
554 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
555 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
559 config SOCIONEXT_SYNQUACER_PREITS
560 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
563 Socionext Synquacer SoCs implement a separate h/w block to generate
564 MSI doorbell writes with non-zero values for the device ID.
568 config HISILICON_ERRATUM_161600802
569 bool "Hip07 161600802: Erroneous redistributor VLPI base"
572 The HiSilicon Hip07 SoC usees the wrong redistributor base
573 when issued ITS commands such as VMOVP and VMAPP, and requires
574 a 128kB offset to be applied to the target address in this commands.
578 config QCOM_FALKOR_ERRATUM_E1041
579 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
582 Falkor CPU may speculatively fetch instructions from an improper
583 memory location when MMU translation is changed from SCTLR_ELn[M]=1
584 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
593 default ARM64_4K_PAGES
595 Page size (translation granule) configuration.
597 config ARM64_4K_PAGES
600 This feature enables 4KB pages support.
602 config ARM64_16K_PAGES
605 The system will use 16KB pages support. AArch32 emulation
606 requires applications compiled with 16K (or a multiple of 16K)
609 config ARM64_64K_PAGES
612 This feature enables 64KB pages support (4KB by default)
613 allowing only two levels of page tables and faster TLB
614 look-up. AArch32 emulation requires applications compiled
615 with 64K aligned segments.
620 prompt "Virtual address space size"
621 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
622 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
623 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
625 Allows choosing one of multiple possible virtual address
626 space sizes. The level of translation table is determined by
627 a combination of page size and virtual address space size.
629 config ARM64_VA_BITS_36
630 bool "36-bit" if EXPERT
631 depends on ARM64_16K_PAGES
633 config ARM64_VA_BITS_39
635 depends on ARM64_4K_PAGES
637 config ARM64_VA_BITS_42
639 depends on ARM64_64K_PAGES
641 config ARM64_VA_BITS_47
643 depends on ARM64_16K_PAGES
645 config ARM64_VA_BITS_48
652 default 36 if ARM64_VA_BITS_36
653 default 39 if ARM64_VA_BITS_39
654 default 42 if ARM64_VA_BITS_42
655 default 47 if ARM64_VA_BITS_47
656 default 48 if ARM64_VA_BITS_48
659 prompt "Physical address space size"
660 default ARM64_PA_BITS_48
662 Choose the maximum physical address range that the kernel will
665 config ARM64_PA_BITS_48
668 config ARM64_PA_BITS_52
669 bool "52-bit (ARMv8.2)"
670 depends on ARM64_64K_PAGES
671 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
673 Enable support for a 52-bit physical address space, introduced as
674 part of the ARMv8.2-LPA extension.
676 With this enabled, the kernel will also continue to work on CPUs that
677 do not support ARMv8.2-LPA, but with some added memory overhead (and
678 minor performance overhead).
684 default 48 if ARM64_PA_BITS_48
685 default 52 if ARM64_PA_BITS_52
687 config CPU_BIG_ENDIAN
688 bool "Build big-endian kernel"
690 Say Y if you plan on running a kernel in big-endian mode.
693 bool "Multi-core scheduler support"
695 Multi-core scheduler support improves the CPU scheduler's decision
696 making when dealing with multi-core CPU chips at a cost of slightly
697 increased overhead in some places. If unsure say N here.
700 bool "SMT scheduler support"
702 Improves the CPU scheduler's decision making when dealing with
703 MultiThreading at a cost of slightly increased overhead in some
704 places. If unsure say N here.
707 int "Maximum number of CPUs (2-4096)"
709 # These have to remain sorted largest to smallest
713 bool "Support for hot-pluggable CPUs"
714 select GENERIC_IRQ_MIGRATION
716 Say Y here to experiment with turning CPUs off and on. CPUs
717 can be controlled through /sys/devices/system/cpu.
719 # Common NUMA Features
721 bool "Numa Memory Allocation and Scheduler Support"
722 select ACPI_NUMA if ACPI
725 Enable NUMA (Non Uniform Memory Access) support.
727 The kernel will try to allocate memory used by a CPU on the
728 local memory of the CPU and add some more
729 NUMA awareness to the kernel.
732 int "Maximum NUMA Nodes (as a power of 2)"
735 depends on NEED_MULTIPLE_NODES
737 Specify the maximum number of NUMA Nodes available on the target
738 system. Increases memory reserved to accommodate various tables.
740 config USE_PERCPU_NUMA_NODE_ID
744 config HAVE_SETUP_PER_CPU_AREA
748 config NEED_PER_CPU_EMBED_FIRST_CHUNK
756 source kernel/Kconfig.preempt
757 source kernel/Kconfig.hz
759 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
762 config ARCH_HAS_HOLES_MEMORYMODEL
763 def_bool y if SPARSEMEM
765 config ARCH_SPARSEMEM_ENABLE
767 select SPARSEMEM_VMEMMAP_ENABLE
769 config ARCH_SPARSEMEM_DEFAULT
770 def_bool ARCH_SPARSEMEM_ENABLE
772 config ARCH_SELECT_MEMORY_MODEL
773 def_bool ARCH_SPARSEMEM_ENABLE
775 config HAVE_ARCH_PFN_VALID
776 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
778 config HW_PERF_EVENTS
782 config SYS_SUPPORTS_HUGETLBFS
785 config ARCH_WANT_HUGE_PMD_SHARE
786 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
788 config ARCH_HAS_CACHE_LINE_SIZE
794 bool "Enable seccomp to safely compute untrusted bytecode"
796 This kernel feature is useful for number crunching applications
797 that may need to compute untrusted bytecode during their
798 execution. By using pipes or other transports made available to
799 the process as file descriptors supporting the read/write
800 syscalls, it's possible to isolate those applications in
801 their own address space using seccomp. Once seccomp is
802 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
803 and the task is only allowed to execute a few safe syscalls
804 defined by each seccomp mode.
807 bool "Enable paravirtualization code"
809 This changes the kernel so it can modify itself when it is run
810 under a hypervisor, potentially improving performance significantly
811 over full virtualization.
813 config PARAVIRT_TIME_ACCOUNTING
814 bool "Paravirtual steal time accounting"
818 Select this option to enable fine granularity task steal time
819 accounting. Time spent executing other tasks in parallel with
820 the current vCPU is discounted from the vCPU power. To account for
821 that, there can be a small performance impact.
823 If in doubt, say N here.
826 depends on PM_SLEEP_SMP
828 bool "kexec system call"
830 kexec is a system call that implements the ability to shutdown your
831 current kernel, and to start another kernel. It is like a reboot
832 but it is independent of the system firmware. And like a reboot
833 you can start any kernel with it, not just Linux.
836 bool "Build kdump crash kernel"
838 Generate crash dump after being started by kexec. This should
839 be normally only set in special crash dump kernels which are
840 loaded in the main kernel with kexec-tools into a specially
841 reserved region and then later executed after a crash by
844 For more details see Documentation/kdump/kdump.txt
851 bool "Xen guest support on ARM64"
852 depends on ARM64 && OF
856 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
858 config FORCE_MAX_ZONEORDER
860 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
861 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
864 The kernel memory allocator divides physically contiguous memory
865 blocks into "zones", where each zone is a power of two number of
866 pages. This option selects the largest power of two that the kernel
867 keeps in the memory allocator. If you need to allocate very large
868 blocks of physically contiguous memory, then you may need to
871 This config option is actually maximum order plus one. For example,
872 a value of 11 means that the largest free memory block is 2^10 pages.
874 We make sure that we can allocate upto a HugePage size for each configuration.
876 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
878 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
879 4M allocations matching the default size used by generic code.
881 config UNMAP_KERNEL_AT_EL0
882 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
885 Speculation attacks against some high-performance processors can
886 be used to bypass MMU permission checks and leak kernel data to
887 userspace. This can be defended against by unmapping the kernel
888 when running in userspace, mapping it back in on exception entry
889 via a trampoline page in the vector table.
893 config HARDEN_BRANCH_PREDICTOR
894 bool "Harden the branch predictor against aliasing attacks" if EXPERT
897 Speculation attacks against some high-performance processors rely on
898 being able to manipulate the branch predictor for a victim context by
899 executing aliasing branches in the attacker context. Such attacks
900 can be partially mitigated against by clearing internal branch
901 predictor state and limiting the prediction logic in some situations.
903 This config option will take CPU-specific actions to harden the
904 branch predictor against aliasing attacks and may rely on specific
905 instruction sequences or control bits being set by the system
910 config HARDEN_EL2_VECTORS
911 bool "Harden EL2 vector mapping against system register leak" if EXPERT
914 Speculation attacks against some high-performance processors can
915 be used to leak privileged information such as the vector base
916 register, resulting in a potential defeat of the EL2 layout
919 This config option will map the vectors to a fixed location,
920 independent of the EL2 code mapping, so that revealing VBAR_EL2
921 to an attacker does not give away any extra information. This
922 only gets enabled on affected CPUs.
926 menuconfig ARMV8_DEPRECATED
927 bool "Emulate deprecated/obsolete ARMv8 instructions"
931 Legacy software support may require certain instructions
932 that have been deprecated or obsoleted in the architecture.
934 Enable this config to enable selective emulation of these
942 bool "Emulate SWP/SWPB instructions"
944 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
945 they are always undefined. Say Y here to enable software
946 emulation of these instructions for userspace using LDXR/STXR.
948 In some older versions of glibc [<=2.8] SWP is used during futex
949 trylock() operations with the assumption that the code will not
950 be preempted. This invalid assumption may be more likely to fail
951 with SWP emulation enabled, leading to deadlock of the user
954 NOTE: when accessing uncached shared regions, LDXR/STXR rely
955 on an external transaction monitoring block called a global
956 monitor to maintain update atomicity. If your system does not
957 implement a global monitor, this option can cause programs that
958 perform SWP operations to uncached memory to deadlock.
962 config CP15_BARRIER_EMULATION
963 bool "Emulate CP15 Barrier instructions"
965 The CP15 barrier instructions - CP15ISB, CP15DSB, and
966 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
967 strongly recommended to use the ISB, DSB, and DMB
968 instructions instead.
970 Say Y here to enable software emulation of these
971 instructions for AArch32 userspace code. When this option is
972 enabled, CP15 barrier usage is traced which can help
973 identify software that needs updating.
977 config SETEND_EMULATION
978 bool "Emulate SETEND instruction"
980 The SETEND instruction alters the data-endianness of the
981 AArch32 EL0, and is deprecated in ARMv8.
983 Say Y here to enable software emulation of the instruction
984 for AArch32 userspace code.
986 Note: All the cpus on the system must have mixed endian support at EL0
987 for this feature to be enabled. If a new CPU - which doesn't support mixed
988 endian - is hotplugged in after this feature has been enabled, there could
989 be unexpected results in the applications.
994 config ARM64_SW_TTBR0_PAN
995 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
997 Enabling this option prevents the kernel from accessing
998 user-space memory directly by pointing TTBR0_EL1 to a reserved
999 zeroed area and reserved ASID. The user access routines
1000 restore the valid TTBR0_EL1 temporarily.
1002 menu "ARMv8.1 architectural features"
1004 config ARM64_HW_AFDBM
1005 bool "Support for hardware updates of the Access and Dirty page flags"
1008 The ARMv8.1 architecture extensions introduce support for
1009 hardware updates of the access and dirty information in page
1010 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1011 capable processors, accesses to pages with PTE_AF cleared will
1012 set this bit instead of raising an access flag fault.
1013 Similarly, writes to read-only pages with the DBM bit set will
1014 clear the read-only bit (AP[2]) instead of raising a
1017 Kernels built with this configuration option enabled continue
1018 to work on pre-ARMv8.1 hardware and the performance impact is
1019 minimal. If unsure, say Y.
1022 bool "Enable support for Privileged Access Never (PAN)"
1025 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1026 prevents the kernel or hypervisor from accessing user-space (EL0)
1029 Choosing this option will cause any unprotected (not using
1030 copy_to_user et al) memory access to fail with a permission fault.
1032 The feature is detected at runtime, and will remain as a 'nop'
1033 instruction if the cpu does not implement the feature.
1035 config ARM64_LSE_ATOMICS
1036 bool "Atomic instructions"
1038 As part of the Large System Extensions, ARMv8.1 introduces new
1039 atomic instructions that are designed specifically to scale in
1042 Say Y here to make use of these instructions for the in-kernel
1043 atomic routines. This incurs a small overhead on CPUs that do
1044 not support these instructions and requires the kernel to be
1045 built with binutils >= 2.25.
1048 bool "Enable support for Virtualization Host Extensions (VHE)"
1051 Virtualization Host Extensions (VHE) allow the kernel to run
1052 directly at EL2 (instead of EL1) on processors that support
1053 it. This leads to better performance for KVM, as they reduce
1054 the cost of the world switch.
1056 Selecting this option allows the VHE feature to be detected
1057 at runtime, and does not affect processors that do not
1058 implement this feature.
1062 menu "ARMv8.2 architectural features"
1065 bool "Enable support for User Access Override (UAO)"
1068 User Access Override (UAO; part of the ARMv8.2 Extensions)
1069 causes the 'unprivileged' variant of the load/store instructions to
1070 be overridden to be privileged.
1072 This option changes get_user() and friends to use the 'unprivileged'
1073 variant of the load/store instructions. This ensures that user-space
1074 really did have access to the supplied memory. When addr_limit is
1075 set to kernel memory the UAO bit will be set, allowing privileged
1076 access to kernel memory.
1078 Choosing this option will cause copy_to_user() et al to use user-space
1081 The feature is detected at runtime, the kernel will use the
1082 regular load/store instructions if the cpu does not implement the
1086 bool "Enable support for persistent memory"
1087 select ARCH_HAS_PMEM_API
1088 select ARCH_HAS_UACCESS_FLUSHCACHE
1090 Say Y to enable support for the persistent memory API based on the
1091 ARMv8.2 DCPoP feature.
1093 The feature is detected at runtime, and the kernel will use DC CVAC
1094 operations if DC CVAP is not supported (following the behaviour of
1095 DC CVAP itself if the system does not define a point of persistence).
1097 config ARM64_RAS_EXTN
1098 bool "Enable support for RAS CPU Extensions"
1101 CPUs that support the Reliability, Availability and Serviceability
1102 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1103 errors, classify them and report them to software.
1105 On CPUs with these extensions system software can use additional
1106 barriers to determine if faults are pending and read the
1107 classification from a new set of registers.
1109 Selecting this feature will allow the kernel to use these barriers
1110 and access the new registers if the system supports the extension.
1111 Platform RAS features may additionally depend on firmware support.
1116 bool "ARM Scalable Vector Extension support"
1119 The Scalable Vector Extension (SVE) is an extension to the AArch64
1120 execution state which complements and extends the SIMD functionality
1121 of the base architecture to support much larger vectors and to enable
1122 additional vectorisation opportunities.
1124 To enable use of this extension on CPUs that implement it, say Y.
1126 Note that for architectural reasons, firmware _must_ implement SVE
1127 support when running on SVE capable hardware. The required support
1130 * version 1.5 and later of the ARM Trusted Firmware
1131 * the AArch64 boot wrapper since commit 5e1261e08abf
1132 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1134 For other firmware implementations, consult the firmware documentation
1137 If you need the kernel to boot on SVE-capable hardware with broken
1138 firmware, you may need to say N here until you get your firmware
1139 fixed. Otherwise, you may experience firmware panics or lockups when
1140 booting the kernel. If unsure and you are not observing these
1141 symptoms, you should assume that it is safe to say Y.
1143 config ARM64_MODULE_PLTS
1145 select HAVE_MOD_ARCH_SPECIFIC
1150 This builds the kernel as a Position Independent Executable (PIE),
1151 which retains all relocation metadata required to relocate the
1152 kernel binary at runtime to a different virtual address than the
1153 address it was linked at.
1154 Since AArch64 uses the RELA relocation format, this requires a
1155 relocation pass at runtime even if the kernel is loaded at the
1156 same address it was linked at.
1158 config RANDOMIZE_BASE
1159 bool "Randomize the address of the kernel image"
1160 select ARM64_MODULE_PLTS if MODULES
1163 Randomizes the virtual address at which the kernel image is
1164 loaded, as a security feature that deters exploit attempts
1165 relying on knowledge of the location of kernel internals.
1167 It is the bootloader's job to provide entropy, by passing a
1168 random u64 value in /chosen/kaslr-seed at kernel entry.
1170 When booting via the UEFI stub, it will invoke the firmware's
1171 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1172 to the kernel proper. In addition, it will randomise the physical
1173 location of the kernel Image as well.
1177 config RANDOMIZE_MODULE_REGION_FULL
1178 bool "Randomize the module region over a 4 GB range"
1179 depends on RANDOMIZE_BASE
1182 Randomizes the location of the module region inside a 4 GB window
1183 covering the core kernel. This way, it is less likely for modules
1184 to leak information about the location of core kernel data structures
1185 but it does imply that function calls between modules and the core
1186 kernel will need to be resolved via veneers in the module PLT.
1188 When this option is not set, the module region will be randomized over
1189 a limited range that contains the [_stext, _etext] interval of the
1190 core kernel, so branch relocations are always in range.
1196 config ARM64_ACPI_PARKING_PROTOCOL
1197 bool "Enable support for the ARM64 ACPI parking protocol"
1200 Enable support for the ARM64 ACPI parking protocol. If disabled
1201 the kernel will not allow booting through the ARM64 ACPI parking
1202 protocol even if the corresponding data is present in the ACPI
1206 string "Default kernel command string"
1209 Provide a set of default command-line options at build time by
1210 entering them here. As a minimum, you should specify the the
1211 root device (e.g. root=/dev/nfs).
1213 config CMDLINE_FORCE
1214 bool "Always use the default kernel command string"
1216 Always use the default kernel command string, even if the boot
1217 loader passes other arguments to the kernel.
1218 This is useful if you cannot or don't want to change the
1219 command-line options your boot loader passes to the kernel.
1225 bool "UEFI runtime support"
1226 depends on OF && !CPU_BIG_ENDIAN
1227 depends on KERNEL_MODE_NEON
1230 select EFI_PARAMS_FROM_FDT
1231 select EFI_RUNTIME_WRAPPERS
1236 This option provides support for runtime services provided
1237 by UEFI firmware (such as non-volatile variables, realtime
1238 clock, and platform reset). A UEFI stub is also provided to
1239 allow the kernel to be booted as an EFI application. This
1240 is only useful on systems that have UEFI firmware.
1243 bool "Enable support for SMBIOS (DMI) tables"
1247 This enables SMBIOS/DMI feature for systems.
1249 This option is only useful on systems that have UEFI firmware.
1250 However, even with this option, the resultant kernel should
1251 continue to boot on existing non-UEFI platforms.
1255 menu "Userspace binary formats"
1257 source "fs/Kconfig.binfmt"
1260 bool "Kernel support for 32-bit EL0"
1261 depends on ARM64_4K_PAGES || EXPERT
1262 select COMPAT_BINFMT_ELF if BINFMT_ELF
1264 select OLD_SIGSUSPEND3
1265 select COMPAT_OLD_SIGACTION
1267 This option enables support for a 32-bit EL0 running under a 64-bit
1268 kernel at EL1. AArch32-specific components such as system calls,
1269 the user helper functions, VFP support and the ptrace interface are
1270 handled appropriately by the kernel.
1272 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1273 that you will only be able to execute AArch32 binaries that were compiled
1274 with page size aligned segments.
1276 If you want to execute 32-bit userspace applications, say Y.
1278 config SYSVIPC_COMPAT
1280 depends on COMPAT && SYSVIPC
1284 menu "Power management options"
1286 source "kernel/power/Kconfig"
1288 config ARCH_HIBERNATION_POSSIBLE
1292 config ARCH_HIBERNATION_HEADER
1294 depends on HIBERNATION
1296 config ARCH_SUSPEND_POSSIBLE
1301 menu "CPU Power Management"
1303 source "drivers/cpuidle/Kconfig"
1305 source "drivers/cpufreq/Kconfig"
1309 source "net/Kconfig"
1311 source "drivers/Kconfig"
1313 source "drivers/firmware/Kconfig"
1315 source "drivers/acpi/Kconfig"
1319 source "arch/arm64/kvm/Kconfig"
1321 source "arch/arm64/Kconfig.debug"
1323 source "security/Kconfig"
1325 source "crypto/Kconfig"
1327 source "arch/arm64/crypto/Kconfig"
1330 source "lib/Kconfig"