3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if ACPI
9 select ACPI_SPCR_TABLE if ACPI
10 select ACPI_PPTT if ACPI
11 select ARCH_CLOCKSOURCE_DATA
12 select ARCH_HAS_DEBUG_VIRTUAL
13 select ARCH_HAS_DEVMEM_IS_ALLOWED
14 select ARCH_HAS_DMA_COHERENT_TO_PFN
15 select ARCH_HAS_DMA_MMAP_PGPROT
16 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
17 select ARCH_HAS_ELF_RANDOMIZE
18 select ARCH_HAS_FAST_MULTIPLIER
19 select ARCH_HAS_FORTIFY_SOURCE
20 select ARCH_HAS_GCOV_PROFILE_ALL
21 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
23 select ARCH_HAS_MEMBARRIER_SYNC_CORE
24 select ARCH_HAS_PTE_SPECIAL
25 select ARCH_HAS_SET_MEMORY
26 select ARCH_HAS_STRICT_KERNEL_RWX
27 select ARCH_HAS_STRICT_MODULE_RWX
28 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
29 select ARCH_HAS_SYNC_DMA_FOR_CPU
30 select ARCH_HAS_SYSCALL_WRAPPER
31 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
32 select ARCH_HAVE_NMI_SAFE_CMPXCHG
33 select ARCH_INLINE_READ_LOCK if !PREEMPT
34 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
35 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
36 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
37 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
38 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
39 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
40 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
41 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
42 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
43 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
44 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
45 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
46 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
47 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
48 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
49 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
50 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
51 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
52 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
53 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
54 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
55 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
56 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
57 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
58 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
59 select ARCH_USE_CMPXCHG_LOCKREF
60 select ARCH_USE_QUEUED_RWLOCKS
61 select ARCH_USE_QUEUED_SPINLOCKS
62 select ARCH_SUPPORTS_MEMORY_FAILURE
63 select ARCH_SUPPORTS_ATOMIC_RMW
64 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
65 select ARCH_SUPPORTS_NUMA_BALANCING
66 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
67 select ARCH_WANT_FRAME_POINTERS
68 select ARCH_HAS_UBSAN_SANITIZE_ALL
72 select AUDIT_ARCH_COMPAT_GENERIC
73 select ARM_GIC_V2M if PCI
75 select ARM_GIC_V3_ITS if PCI
77 select BUILDTIME_EXTABLE_SORT
78 select CLONE_BACKWARDS
80 select CPU_PM if (SUSPEND || CPU_IDLE)
82 select DCACHE_WORD_ACCESS
83 select DMA_DIRECT_REMAP
86 select GENERIC_ALLOCATOR
87 select GENERIC_ARCH_TOPOLOGY
88 select GENERIC_CLOCKEVENTS
89 select GENERIC_CLOCKEVENTS_BROADCAST
90 select GENERIC_CPU_AUTOPROBE
91 select GENERIC_EARLY_IOREMAP
92 select GENERIC_IDLE_POLL_SETUP
93 select GENERIC_IRQ_MULTI_HANDLER
94 select GENERIC_IRQ_PROBE
95 select GENERIC_IRQ_SHOW
96 select GENERIC_IRQ_SHOW_LEVEL
97 select GENERIC_PCI_IOMAP
98 select GENERIC_SCHED_CLOCK
99 select GENERIC_SMP_IDLE_THREAD
100 select GENERIC_STRNCPY_FROM_USER
101 select GENERIC_STRNLEN_USER
102 select GENERIC_TIME_VSYSCALL
103 select HANDLE_DOMAIN_IRQ
104 select HARDIRQS_SW_RESEND
105 select HAVE_ACPI_APEI if (ACPI && EFI)
106 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
107 select HAVE_ARCH_AUDITSYSCALL
108 select HAVE_ARCH_BITREVERSE
109 select HAVE_ARCH_HUGE_VMAP
110 select HAVE_ARCH_JUMP_LABEL
111 select HAVE_ARCH_JUMP_LABEL_RELATIVE
112 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
113 select HAVE_ARCH_KGDB
114 select HAVE_ARCH_MMAP_RND_BITS
115 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
116 select HAVE_ARCH_PREL32_RELOCATIONS
117 select HAVE_ARCH_SECCOMP_FILTER
118 select HAVE_ARCH_STACKLEAK
119 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
120 select HAVE_ARCH_TRACEHOOK
121 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
122 select HAVE_ARCH_VMAP_STACK
123 select HAVE_ARM_SMCCC
125 select HAVE_C_RECORDMCOUNT
126 select HAVE_CMPXCHG_DOUBLE
127 select HAVE_CMPXCHG_LOCAL
128 select HAVE_CONTEXT_TRACKING
129 select HAVE_DEBUG_BUGVERBOSE
130 select HAVE_DEBUG_KMEMLEAK
131 select HAVE_DMA_CONTIGUOUS
132 select HAVE_DYNAMIC_FTRACE
133 select HAVE_EFFICIENT_UNALIGNED_ACCESS
134 select HAVE_FTRACE_MCOUNT_RECORD
135 select HAVE_FUNCTION_TRACER
136 select HAVE_FUNCTION_GRAPH_TRACER
137 select HAVE_GCC_PLUGINS
138 select HAVE_GENERIC_DMA_COHERENT
139 select HAVE_HW_BREAKPOINT if PERF_EVENTS
140 select HAVE_IRQ_TIME_ACCOUNTING
141 select HAVE_MEMBLOCK_NODE_MAP if NUMA
143 select HAVE_PATA_PLATFORM
144 select HAVE_PERF_EVENTS
145 select HAVE_PERF_REGS
146 select HAVE_PERF_USER_STACK_DUMP
147 select HAVE_REGS_AND_STACK_ACCESS_API
148 select HAVE_RCU_TABLE_FREE
149 select HAVE_RCU_TABLE_INVALIDATE
151 select HAVE_STACKPROTECTOR
152 select HAVE_SYSCALL_TRACEPOINTS
154 select HAVE_KRETPROBES
155 select IOMMU_DMA if IOMMU_SUPPORT
157 select IRQ_FORCED_THREADING
158 select MODULES_USE_ELF_RELA
159 select MULTI_IRQ_HANDLER
160 select NEED_DMA_MAP_STATE
161 select NEED_SG_DMA_LENGTH
163 select OF_EARLY_FLATTREE
164 select OF_RESERVED_MEM
165 select PCI_ECAM if ACPI
171 select SYSCTL_EXCEPTION_TRACE
172 select THREAD_INFO_IN_TASK
174 ARM 64-bit (AArch64) Linux support.
182 config ARM64_PAGE_SHIFT
184 default 16 if ARM64_64K_PAGES
185 default 14 if ARM64_16K_PAGES
188 config ARM64_CONT_SHIFT
190 default 5 if ARM64_64K_PAGES
191 default 7 if ARM64_16K_PAGES
194 config ARCH_MMAP_RND_BITS_MIN
195 default 14 if ARM64_64K_PAGES
196 default 16 if ARM64_16K_PAGES
199 # max bits determined by the following formula:
200 # VA_BITS - PAGE_SHIFT - 3
201 config ARCH_MMAP_RND_BITS_MAX
202 default 19 if ARM64_VA_BITS=36
203 default 24 if ARM64_VA_BITS=39
204 default 27 if ARM64_VA_BITS=42
205 default 30 if ARM64_VA_BITS=47
206 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
207 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
208 default 33 if ARM64_VA_BITS=48
209 default 14 if ARM64_64K_PAGES
210 default 16 if ARM64_16K_PAGES
213 config ARCH_MMAP_RND_COMPAT_BITS_MIN
214 default 7 if ARM64_64K_PAGES
215 default 9 if ARM64_16K_PAGES
218 config ARCH_MMAP_RND_COMPAT_BITS_MAX
224 config STACKTRACE_SUPPORT
227 config ILLEGAL_POINTER_VALUE
229 default 0xdead000000000000
231 config LOCKDEP_SUPPORT
234 config TRACE_IRQFLAGS_SUPPORT
237 config RWSEM_XCHGADD_ALGORITHM
244 config GENERIC_BUG_RELATIVE_POINTERS
246 depends on GENERIC_BUG
248 config GENERIC_HWEIGHT
254 config GENERIC_CALIBRATE_DELAY
260 config HAVE_GENERIC_GUP
266 config KERNEL_MODE_NEON
269 config FIX_EARLYCON_MEM
272 config PGTABLE_LEVELS
274 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
275 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
276 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
277 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
278 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
279 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
281 config ARCH_SUPPORTS_UPROBES
284 config ARCH_PROC_KCORE_TEXT
287 source "arch/arm64/Kconfig.platforms"
294 This feature enables support for PCI bus system. If you say Y
295 here, the kernel will include drivers and infrastructure code
296 to support PCI bus devices.
301 config PCI_DOMAINS_GENERIC
307 source "drivers/pci/Kconfig"
311 menu "Kernel Features"
313 menu "ARM errata workarounds via the alternatives framework"
315 config ARM64_ERRATUM_826319
316 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
319 This option adds an alternative code sequence to work around ARM
320 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
321 AXI master interface and an L2 cache.
323 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
324 and is unable to accept a certain write via this interface, it will
325 not progress on read data presented on the read data channel and the
328 The workaround promotes data cache clean instructions to
329 data cache clean-and-invalidate.
330 Please note that this does not necessarily enable the workaround,
331 as it depends on the alternative framework, which will only patch
332 the kernel if an affected CPU is detected.
336 config ARM64_ERRATUM_827319
337 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
340 This option adds an alternative code sequence to work around ARM
341 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
342 master interface and an L2 cache.
344 Under certain conditions this erratum can cause a clean line eviction
345 to occur at the same time as another transaction to the same address
346 on the AMBA 5 CHI interface, which can cause data corruption if the
347 interconnect reorders the two transactions.
349 The workaround promotes data cache clean instructions to
350 data cache clean-and-invalidate.
351 Please note that this does not necessarily enable the workaround,
352 as it depends on the alternative framework, which will only patch
353 the kernel if an affected CPU is detected.
357 config ARM64_ERRATUM_824069
358 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
361 This option adds an alternative code sequence to work around ARM
362 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
363 to a coherent interconnect.
365 If a Cortex-A53 processor is executing a store or prefetch for
366 write instruction at the same time as a processor in another
367 cluster is executing a cache maintenance operation to the same
368 address, then this erratum might cause a clean cache line to be
369 incorrectly marked as dirty.
371 The workaround promotes data cache clean instructions to
372 data cache clean-and-invalidate.
373 Please note that this option does not necessarily enable the
374 workaround, as it depends on the alternative framework, which will
375 only patch the kernel if an affected CPU is detected.
379 config ARM64_ERRATUM_819472
380 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
383 This option adds an alternative code sequence to work around ARM
384 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
385 present when it is connected to a coherent interconnect.
387 If the processor is executing a load and store exclusive sequence at
388 the same time as a processor in another cluster is executing a cache
389 maintenance operation to the same address, then this erratum might
390 cause data corruption.
392 The workaround promotes data cache clean instructions to
393 data cache clean-and-invalidate.
394 Please note that this does not necessarily enable the workaround,
395 as it depends on the alternative framework, which will only patch
396 the kernel if an affected CPU is detected.
400 config ARM64_ERRATUM_832075
401 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
404 This option adds an alternative code sequence to work around ARM
405 erratum 832075 on Cortex-A57 parts up to r1p2.
407 Affected Cortex-A57 parts might deadlock when exclusive load/store
408 instructions to Write-Back memory are mixed with Device loads.
410 The workaround is to promote device loads to use Load-Acquire
412 Please note that this does not necessarily enable the workaround,
413 as it depends on the alternative framework, which will only patch
414 the kernel if an affected CPU is detected.
418 config ARM64_ERRATUM_834220
419 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
423 This option adds an alternative code sequence to work around ARM
424 erratum 834220 on Cortex-A57 parts up to r1p2.
426 Affected Cortex-A57 parts might report a Stage 2 translation
427 fault as the result of a Stage 1 fault for load crossing a
428 page boundary when there is a permission or device memory
429 alignment fault at Stage 1 and a translation fault at Stage 2.
431 The workaround is to verify that the Stage 1 translation
432 doesn't generate a fault before handling the Stage 2 fault.
433 Please note that this does not necessarily enable the workaround,
434 as it depends on the alternative framework, which will only patch
435 the kernel if an affected CPU is detected.
439 config ARM64_ERRATUM_845719
440 bool "Cortex-A53: 845719: a load might read incorrect data"
444 This option adds an alternative code sequence to work around ARM
445 erratum 845719 on Cortex-A53 parts up to r0p4.
447 When running a compat (AArch32) userspace on an affected Cortex-A53
448 part, a load at EL0 from a virtual address that matches the bottom 32
449 bits of the virtual address used by a recent load at (AArch64) EL1
450 might return incorrect data.
452 The workaround is to write the contextidr_el1 register on exception
453 return to a 32-bit task.
454 Please note that this does not necessarily enable the workaround,
455 as it depends on the alternative framework, which will only patch
456 the kernel if an affected CPU is detected.
460 config ARM64_ERRATUM_843419
461 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
463 select ARM64_MODULE_PLTS if MODULES
465 This option links the kernel with '--fix-cortex-a53-843419' and
466 enables PLT support to replace certain ADRP instructions, which can
467 cause subsequent memory accesses to use an incorrect address on
468 Cortex-A53 parts up to r0p4.
472 config ARM64_ERRATUM_1024718
473 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
476 This option adds work around for Arm Cortex-A55 Erratum 1024718.
478 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
479 update of the hardware dirty bit when the DBM/AP bits are updated
480 without a break-before-make. The work around is to disable the usage
481 of hardware DBM locally on the affected cores. CPUs not affected by
482 erratum will continue to use the feature.
486 config ARM64_ERRATUM_1188873
487 bool "Cortex-A76: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
489 select ARM_ARCH_TIMER_OOL_WORKAROUND
491 This option adds work arounds for ARM Cortex-A76 erratum 1188873
493 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could cause
494 register corruption when accessing the timer registers from
499 config CAVIUM_ERRATUM_22375
500 bool "Cavium erratum 22375, 24313"
503 Enable workaround for erratum 22375, 24313.
505 This implements two gicv3-its errata workarounds for ThunderX. Both
506 with small impact affecting only ITS table allocation.
508 erratum 22375: only alloc 8MB table size
509 erratum 24313: ignore memory access type
511 The fixes are in ITS initialization and basically ignore memory access
512 type and table size provided by the TYPER and BASER registers.
516 config CAVIUM_ERRATUM_23144
517 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
521 ITS SYNC command hang for cross node io and collections/cpu mapping.
525 config CAVIUM_ERRATUM_23154
526 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
529 The gicv3 of ThunderX requires a modified version for
530 reading the IAR status to ensure data synchronization
531 (access to icc_iar1_el1 is not sync'ed before and after).
535 config CAVIUM_ERRATUM_27456
536 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
539 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
540 instructions may cause the icache to become corrupted if it
541 contains data for a non-current ASID. The fix is to
542 invalidate the icache when changing the mm context.
546 config CAVIUM_ERRATUM_30115
547 bool "Cavium erratum 30115: Guest may disable interrupts in host"
550 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
551 1.2, and T83 Pass 1.0, KVM guest execution may disable
552 interrupts in host. Trapping both GICv3 group-0 and group-1
553 accesses sidesteps the issue.
557 config QCOM_FALKOR_ERRATUM_1003
558 bool "Falkor E1003: Incorrect translation due to ASID change"
561 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
562 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
563 in TTBR1_EL1, this situation only occurs in the entry trampoline and
564 then only for entries in the walk cache, since the leaf translation
565 is unchanged. Work around the erratum by invalidating the walk cache
566 entries for the trampoline before entering the kernel proper.
568 config QCOM_FALKOR_ERRATUM_1009
569 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
572 On Falkor v1, the CPU may prematurely complete a DSB following a
573 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
574 one more time to fix the issue.
578 config QCOM_QDF2400_ERRATUM_0065
579 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
582 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
583 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
584 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
588 config SOCIONEXT_SYNQUACER_PREITS
589 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
592 Socionext Synquacer SoCs implement a separate h/w block to generate
593 MSI doorbell writes with non-zero values for the device ID.
597 config HISILICON_ERRATUM_161600802
598 bool "Hip07 161600802: Erroneous redistributor VLPI base"
601 The HiSilicon Hip07 SoC usees the wrong redistributor base
602 when issued ITS commands such as VMOVP and VMAPP, and requires
603 a 128kB offset to be applied to the target address in this commands.
607 config QCOM_FALKOR_ERRATUM_E1041
608 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
611 Falkor CPU may speculatively fetch instructions from an improper
612 memory location when MMU translation is changed from SCTLR_ELn[M]=1
613 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
622 default ARM64_4K_PAGES
624 Page size (translation granule) configuration.
626 config ARM64_4K_PAGES
629 This feature enables 4KB pages support.
631 config ARM64_16K_PAGES
634 The system will use 16KB pages support. AArch32 emulation
635 requires applications compiled with 16K (or a multiple of 16K)
638 config ARM64_64K_PAGES
641 This feature enables 64KB pages support (4KB by default)
642 allowing only two levels of page tables and faster TLB
643 look-up. AArch32 emulation requires applications compiled
644 with 64K aligned segments.
649 prompt "Virtual address space size"
650 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
651 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
652 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
654 Allows choosing one of multiple possible virtual address
655 space sizes. The level of translation table is determined by
656 a combination of page size and virtual address space size.
658 config ARM64_VA_BITS_36
659 bool "36-bit" if EXPERT
660 depends on ARM64_16K_PAGES
662 config ARM64_VA_BITS_39
664 depends on ARM64_4K_PAGES
666 config ARM64_VA_BITS_42
668 depends on ARM64_64K_PAGES
670 config ARM64_VA_BITS_47
672 depends on ARM64_16K_PAGES
674 config ARM64_VA_BITS_48
681 default 36 if ARM64_VA_BITS_36
682 default 39 if ARM64_VA_BITS_39
683 default 42 if ARM64_VA_BITS_42
684 default 47 if ARM64_VA_BITS_47
685 default 48 if ARM64_VA_BITS_48
688 prompt "Physical address space size"
689 default ARM64_PA_BITS_48
691 Choose the maximum physical address range that the kernel will
694 config ARM64_PA_BITS_48
697 config ARM64_PA_BITS_52
698 bool "52-bit (ARMv8.2)"
699 depends on ARM64_64K_PAGES
700 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
702 Enable support for a 52-bit physical address space, introduced as
703 part of the ARMv8.2-LPA extension.
705 With this enabled, the kernel will also continue to work on CPUs that
706 do not support ARMv8.2-LPA, but with some added memory overhead (and
707 minor performance overhead).
713 default 48 if ARM64_PA_BITS_48
714 default 52 if ARM64_PA_BITS_52
716 config CPU_BIG_ENDIAN
717 bool "Build big-endian kernel"
719 Say Y if you plan on running a kernel in big-endian mode.
722 bool "Multi-core scheduler support"
724 Multi-core scheduler support improves the CPU scheduler's decision
725 making when dealing with multi-core CPU chips at a cost of slightly
726 increased overhead in some places. If unsure say N here.
729 bool "SMT scheduler support"
731 Improves the CPU scheduler's decision making when dealing with
732 MultiThreading at a cost of slightly increased overhead in some
733 places. If unsure say N here.
736 int "Maximum number of CPUs (2-4096)"
738 # These have to remain sorted largest to smallest
742 bool "Support for hot-pluggable CPUs"
743 select GENERIC_IRQ_MIGRATION
745 Say Y here to experiment with turning CPUs off and on. CPUs
746 can be controlled through /sys/devices/system/cpu.
748 # Common NUMA Features
750 bool "Numa Memory Allocation and Scheduler Support"
751 select ACPI_NUMA if ACPI
754 Enable NUMA (Non Uniform Memory Access) support.
756 The kernel will try to allocate memory used by a CPU on the
757 local memory of the CPU and add some more
758 NUMA awareness to the kernel.
761 int "Maximum NUMA Nodes (as a power of 2)"
764 depends on NEED_MULTIPLE_NODES
766 Specify the maximum number of NUMA Nodes available on the target
767 system. Increases memory reserved to accommodate various tables.
769 config USE_PERCPU_NUMA_NODE_ID
773 config HAVE_SETUP_PER_CPU_AREA
777 config NEED_PER_CPU_EMBED_FIRST_CHUNK
784 source kernel/Kconfig.hz
786 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
789 config ARCH_SPARSEMEM_ENABLE
791 select SPARSEMEM_VMEMMAP_ENABLE
793 config ARCH_SPARSEMEM_DEFAULT
794 def_bool ARCH_SPARSEMEM_ENABLE
796 config ARCH_SELECT_MEMORY_MODEL
797 def_bool ARCH_SPARSEMEM_ENABLE
799 config ARCH_FLATMEM_ENABLE
802 config HAVE_ARCH_PFN_VALID
805 config HW_PERF_EVENTS
809 config SYS_SUPPORTS_HUGETLBFS
812 config ARCH_WANT_HUGE_PMD_SHARE
813 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
815 config ARCH_HAS_CACHE_LINE_SIZE
819 bool "Enable seccomp to safely compute untrusted bytecode"
821 This kernel feature is useful for number crunching applications
822 that may need to compute untrusted bytecode during their
823 execution. By using pipes or other transports made available to
824 the process as file descriptors supporting the read/write
825 syscalls, it's possible to isolate those applications in
826 their own address space using seccomp. Once seccomp is
827 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
828 and the task is only allowed to execute a few safe syscalls
829 defined by each seccomp mode.
832 bool "Enable paravirtualization code"
834 This changes the kernel so it can modify itself when it is run
835 under a hypervisor, potentially improving performance significantly
836 over full virtualization.
838 config PARAVIRT_TIME_ACCOUNTING
839 bool "Paravirtual steal time accounting"
843 Select this option to enable fine granularity task steal time
844 accounting. Time spent executing other tasks in parallel with
845 the current vCPU is discounted from the vCPU power. To account for
846 that, there can be a small performance impact.
848 If in doubt, say N here.
851 depends on PM_SLEEP_SMP
853 bool "kexec system call"
855 kexec is a system call that implements the ability to shutdown your
856 current kernel, and to start another kernel. It is like a reboot
857 but it is independent of the system firmware. And like a reboot
858 you can start any kernel with it, not just Linux.
861 bool "Build kdump crash kernel"
863 Generate crash dump after being started by kexec. This should
864 be normally only set in special crash dump kernels which are
865 loaded in the main kernel with kexec-tools into a specially
866 reserved region and then later executed after a crash by
869 For more details see Documentation/kdump/kdump.txt
876 bool "Xen guest support on ARM64"
877 depends on ARM64 && OF
881 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
883 config FORCE_MAX_ZONEORDER
885 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
886 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
889 The kernel memory allocator divides physically contiguous memory
890 blocks into "zones", where each zone is a power of two number of
891 pages. This option selects the largest power of two that the kernel
892 keeps in the memory allocator. If you need to allocate very large
893 blocks of physically contiguous memory, then you may need to
896 This config option is actually maximum order plus one. For example,
897 a value of 11 means that the largest free memory block is 2^10 pages.
899 We make sure that we can allocate upto a HugePage size for each configuration.
901 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
903 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
904 4M allocations matching the default size used by generic code.
906 config UNMAP_KERNEL_AT_EL0
907 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
910 Speculation attacks against some high-performance processors can
911 be used to bypass MMU permission checks and leak kernel data to
912 userspace. This can be defended against by unmapping the kernel
913 when running in userspace, mapping it back in on exception entry
914 via a trampoline page in the vector table.
918 config HARDEN_BRANCH_PREDICTOR
919 bool "Harden the branch predictor against aliasing attacks" if EXPERT
922 Speculation attacks against some high-performance processors rely on
923 being able to manipulate the branch predictor for a victim context by
924 executing aliasing branches in the attacker context. Such attacks
925 can be partially mitigated against by clearing internal branch
926 predictor state and limiting the prediction logic in some situations.
928 This config option will take CPU-specific actions to harden the
929 branch predictor against aliasing attacks and may rely on specific
930 instruction sequences or control bits being set by the system
935 config HARDEN_EL2_VECTORS
936 bool "Harden EL2 vector mapping against system register leak" if EXPERT
939 Speculation attacks against some high-performance processors can
940 be used to leak privileged information such as the vector base
941 register, resulting in a potential defeat of the EL2 layout
944 This config option will map the vectors to a fixed location,
945 independent of the EL2 code mapping, so that revealing VBAR_EL2
946 to an attacker does not give away any extra information. This
947 only gets enabled on affected CPUs.
952 bool "Speculative Store Bypass Disable" if EXPERT
955 This enables mitigation of the bypassing of previous stores
956 by speculative loads.
960 menuconfig ARMV8_DEPRECATED
961 bool "Emulate deprecated/obsolete ARMv8 instructions"
965 Legacy software support may require certain instructions
966 that have been deprecated or obsoleted in the architecture.
968 Enable this config to enable selective emulation of these
976 bool "Emulate SWP/SWPB instructions"
978 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
979 they are always undefined. Say Y here to enable software
980 emulation of these instructions for userspace using LDXR/STXR.
982 In some older versions of glibc [<=2.8] SWP is used during futex
983 trylock() operations with the assumption that the code will not
984 be preempted. This invalid assumption may be more likely to fail
985 with SWP emulation enabled, leading to deadlock of the user
988 NOTE: when accessing uncached shared regions, LDXR/STXR rely
989 on an external transaction monitoring block called a global
990 monitor to maintain update atomicity. If your system does not
991 implement a global monitor, this option can cause programs that
992 perform SWP operations to uncached memory to deadlock.
996 config CP15_BARRIER_EMULATION
997 bool "Emulate CP15 Barrier instructions"
999 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1000 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1001 strongly recommended to use the ISB, DSB, and DMB
1002 instructions instead.
1004 Say Y here to enable software emulation of these
1005 instructions for AArch32 userspace code. When this option is
1006 enabled, CP15 barrier usage is traced which can help
1007 identify software that needs updating.
1011 config SETEND_EMULATION
1012 bool "Emulate SETEND instruction"
1014 The SETEND instruction alters the data-endianness of the
1015 AArch32 EL0, and is deprecated in ARMv8.
1017 Say Y here to enable software emulation of the instruction
1018 for AArch32 userspace code.
1020 Note: All the cpus on the system must have mixed endian support at EL0
1021 for this feature to be enabled. If a new CPU - which doesn't support mixed
1022 endian - is hotplugged in after this feature has been enabled, there could
1023 be unexpected results in the applications.
1028 config ARM64_SW_TTBR0_PAN
1029 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1031 Enabling this option prevents the kernel from accessing
1032 user-space memory directly by pointing TTBR0_EL1 to a reserved
1033 zeroed area and reserved ASID. The user access routines
1034 restore the valid TTBR0_EL1 temporarily.
1036 menu "ARMv8.1 architectural features"
1038 config ARM64_HW_AFDBM
1039 bool "Support for hardware updates of the Access and Dirty page flags"
1042 The ARMv8.1 architecture extensions introduce support for
1043 hardware updates of the access and dirty information in page
1044 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1045 capable processors, accesses to pages with PTE_AF cleared will
1046 set this bit instead of raising an access flag fault.
1047 Similarly, writes to read-only pages with the DBM bit set will
1048 clear the read-only bit (AP[2]) instead of raising a
1051 Kernels built with this configuration option enabled continue
1052 to work on pre-ARMv8.1 hardware and the performance impact is
1053 minimal. If unsure, say Y.
1056 bool "Enable support for Privileged Access Never (PAN)"
1059 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1060 prevents the kernel or hypervisor from accessing user-space (EL0)
1063 Choosing this option will cause any unprotected (not using
1064 copy_to_user et al) memory access to fail with a permission fault.
1066 The feature is detected at runtime, and will remain as a 'nop'
1067 instruction if the cpu does not implement the feature.
1069 config ARM64_LSE_ATOMICS
1070 bool "Atomic instructions"
1073 As part of the Large System Extensions, ARMv8.1 introduces new
1074 atomic instructions that are designed specifically to scale in
1077 Say Y here to make use of these instructions for the in-kernel
1078 atomic routines. This incurs a small overhead on CPUs that do
1079 not support these instructions and requires the kernel to be
1080 built with binutils >= 2.25 in order for the new instructions
1084 bool "Enable support for Virtualization Host Extensions (VHE)"
1087 Virtualization Host Extensions (VHE) allow the kernel to run
1088 directly at EL2 (instead of EL1) on processors that support
1089 it. This leads to better performance for KVM, as they reduce
1090 the cost of the world switch.
1092 Selecting this option allows the VHE feature to be detected
1093 at runtime, and does not affect processors that do not
1094 implement this feature.
1098 menu "ARMv8.2 architectural features"
1101 bool "Enable support for User Access Override (UAO)"
1104 User Access Override (UAO; part of the ARMv8.2 Extensions)
1105 causes the 'unprivileged' variant of the load/store instructions to
1106 be overridden to be privileged.
1108 This option changes get_user() and friends to use the 'unprivileged'
1109 variant of the load/store instructions. This ensures that user-space
1110 really did have access to the supplied memory. When addr_limit is
1111 set to kernel memory the UAO bit will be set, allowing privileged
1112 access to kernel memory.
1114 Choosing this option will cause copy_to_user() et al to use user-space
1117 The feature is detected at runtime, the kernel will use the
1118 regular load/store instructions if the cpu does not implement the
1122 bool "Enable support for persistent memory"
1123 select ARCH_HAS_PMEM_API
1124 select ARCH_HAS_UACCESS_FLUSHCACHE
1126 Say Y to enable support for the persistent memory API based on the
1127 ARMv8.2 DCPoP feature.
1129 The feature is detected at runtime, and the kernel will use DC CVAC
1130 operations if DC CVAP is not supported (following the behaviour of
1131 DC CVAP itself if the system does not define a point of persistence).
1133 config ARM64_RAS_EXTN
1134 bool "Enable support for RAS CPU Extensions"
1137 CPUs that support the Reliability, Availability and Serviceability
1138 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1139 errors, classify them and report them to software.
1141 On CPUs with these extensions system software can use additional
1142 barriers to determine if faults are pending and read the
1143 classification from a new set of registers.
1145 Selecting this feature will allow the kernel to use these barriers
1146 and access the new registers if the system supports the extension.
1147 Platform RAS features may additionally depend on firmware support.
1150 bool "Enable support for Common Not Private (CNP) translations"
1152 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1154 Common Not Private (CNP) allows translation table entries to
1155 be shared between different PEs in the same inner shareable
1156 domain, so the hardware can use this fact to optimise the
1157 caching of such entries in the TLB.
1159 Selecting this option allows the CNP feature to be detected
1160 at runtime, and does not affect PEs that do not implement
1166 bool "ARM Scalable Vector Extension support"
1168 depends on !KVM || ARM64_VHE
1170 The Scalable Vector Extension (SVE) is an extension to the AArch64
1171 execution state which complements and extends the SIMD functionality
1172 of the base architecture to support much larger vectors and to enable
1173 additional vectorisation opportunities.
1175 To enable use of this extension on CPUs that implement it, say Y.
1177 Note that for architectural reasons, firmware _must_ implement SVE
1178 support when running on SVE capable hardware. The required support
1181 * version 1.5 and later of the ARM Trusted Firmware
1182 * the AArch64 boot wrapper since commit 5e1261e08abf
1183 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1185 For other firmware implementations, consult the firmware documentation
1188 If you need the kernel to boot on SVE-capable hardware with broken
1189 firmware, you may need to say N here until you get your firmware
1190 fixed. Otherwise, you may experience firmware panics or lockups when
1191 booting the kernel. If unsure and you are not observing these
1192 symptoms, you should assume that it is safe to say Y.
1194 CPUs that support SVE are architecturally required to support the
1195 Virtualization Host Extensions (VHE), so the kernel makes no
1196 provision for supporting SVE alongside KVM without VHE enabled.
1197 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1198 KVM in the same kernel image.
1200 config ARM64_MODULE_PLTS
1202 select HAVE_MOD_ARCH_SPECIFIC
1207 This builds the kernel as a Position Independent Executable (PIE),
1208 which retains all relocation metadata required to relocate the
1209 kernel binary at runtime to a different virtual address than the
1210 address it was linked at.
1211 Since AArch64 uses the RELA relocation format, this requires a
1212 relocation pass at runtime even if the kernel is loaded at the
1213 same address it was linked at.
1215 config RANDOMIZE_BASE
1216 bool "Randomize the address of the kernel image"
1217 select ARM64_MODULE_PLTS if MODULES
1220 Randomizes the virtual address at which the kernel image is
1221 loaded, as a security feature that deters exploit attempts
1222 relying on knowledge of the location of kernel internals.
1224 It is the bootloader's job to provide entropy, by passing a
1225 random u64 value in /chosen/kaslr-seed at kernel entry.
1227 When booting via the UEFI stub, it will invoke the firmware's
1228 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1229 to the kernel proper. In addition, it will randomise the physical
1230 location of the kernel Image as well.
1234 config RANDOMIZE_MODULE_REGION_FULL
1235 bool "Randomize the module region over a 4 GB range"
1236 depends on RANDOMIZE_BASE
1239 Randomizes the location of the module region inside a 4 GB window
1240 covering the core kernel. This way, it is less likely for modules
1241 to leak information about the location of core kernel data structures
1242 but it does imply that function calls between modules and the core
1243 kernel will need to be resolved via veneers in the module PLT.
1245 When this option is not set, the module region will be randomized over
1246 a limited range that contains the [_stext, _etext] interval of the
1247 core kernel, so branch relocations are always in range.
1253 config ARM64_ACPI_PARKING_PROTOCOL
1254 bool "Enable support for the ARM64 ACPI parking protocol"
1257 Enable support for the ARM64 ACPI parking protocol. If disabled
1258 the kernel will not allow booting through the ARM64 ACPI parking
1259 protocol even if the corresponding data is present in the ACPI
1263 string "Default kernel command string"
1266 Provide a set of default command-line options at build time by
1267 entering them here. As a minimum, you should specify the the
1268 root device (e.g. root=/dev/nfs).
1270 config CMDLINE_FORCE
1271 bool "Always use the default kernel command string"
1273 Always use the default kernel command string, even if the boot
1274 loader passes other arguments to the kernel.
1275 This is useful if you cannot or don't want to change the
1276 command-line options your boot loader passes to the kernel.
1282 bool "UEFI runtime support"
1283 depends on OF && !CPU_BIG_ENDIAN
1284 depends on KERNEL_MODE_NEON
1285 select ARCH_SUPPORTS_ACPI
1288 select EFI_PARAMS_FROM_FDT
1289 select EFI_RUNTIME_WRAPPERS
1294 This option provides support for runtime services provided
1295 by UEFI firmware (such as non-volatile variables, realtime
1296 clock, and platform reset). A UEFI stub is also provided to
1297 allow the kernel to be booted as an EFI application. This
1298 is only useful on systems that have UEFI firmware.
1301 bool "Enable support for SMBIOS (DMI) tables"
1305 This enables SMBIOS/DMI feature for systems.
1307 This option is only useful on systems that have UEFI firmware.
1308 However, even with this option, the resultant kernel should
1309 continue to boot on existing non-UEFI platforms.
1314 bool "Kernel support for 32-bit EL0"
1315 depends on ARM64_4K_PAGES || EXPERT
1316 select COMPAT_BINFMT_ELF if BINFMT_ELF
1318 select OLD_SIGSUSPEND3
1319 select COMPAT_OLD_SIGACTION
1321 This option enables support for a 32-bit EL0 running under a 64-bit
1322 kernel at EL1. AArch32-specific components such as system calls,
1323 the user helper functions, VFP support and the ptrace interface are
1324 handled appropriately by the kernel.
1326 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1327 that you will only be able to execute AArch32 binaries that were compiled
1328 with page size aligned segments.
1330 If you want to execute 32-bit userspace applications, say Y.
1332 config SYSVIPC_COMPAT
1334 depends on COMPAT && SYSVIPC
1336 menu "Power management options"
1338 source "kernel/power/Kconfig"
1340 config ARCH_HIBERNATION_POSSIBLE
1344 config ARCH_HIBERNATION_HEADER
1346 depends on HIBERNATION
1348 config ARCH_SUSPEND_POSSIBLE
1353 menu "CPU Power Management"
1355 source "drivers/cpuidle/Kconfig"
1357 source "drivers/cpufreq/Kconfig"
1361 source "drivers/firmware/Kconfig"
1363 source "drivers/acpi/Kconfig"
1365 source "arch/arm64/kvm/Kconfig"
1368 source "arch/arm64/crypto/Kconfig"