1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_WX
13 select ARCH_BINFMT_ELF_STATE
14 select ARCH_HAS_DEBUG_VIRTUAL
15 select ARCH_HAS_DEBUG_VM_PGTABLE
16 select ARCH_HAS_DEVMEM_IS_ALLOWED
17 select ARCH_HAS_DMA_PREP_COHERENT
18 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
19 select ARCH_HAS_FAST_MULTIPLIER
20 select ARCH_HAS_FORTIFY_SOURCE
21 select ARCH_HAS_GCOV_PROFILE_ALL
22 select ARCH_HAS_GIGANTIC_PAGE
24 select ARCH_HAS_KEEPINITRD
25 select ARCH_HAS_MEMBARRIER_SYNC_CORE
26 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
27 select ARCH_HAS_PTE_DEVMAP
28 select ARCH_HAS_PTE_SPECIAL
29 select ARCH_HAS_SETUP_DMA_OPS
30 select ARCH_HAS_SET_DIRECT_MAP
31 select ARCH_HAS_SET_MEMORY
33 select ARCH_HAS_STRICT_KERNEL_RWX
34 select ARCH_HAS_STRICT_MODULE_RWX
35 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
36 select ARCH_HAS_SYNC_DMA_FOR_CPU
37 select ARCH_HAS_SYSCALL_WRAPPER
38 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
39 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
40 select ARCH_HAVE_ELF_PROT
41 select ARCH_HAVE_NMI_SAFE_CMPXCHG
42 select ARCH_INLINE_READ_LOCK if !PREEMPTION
43 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
44 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
45 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
46 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
47 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
48 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
49 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
50 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
51 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
52 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
53 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
54 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
55 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
56 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
57 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
58 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
59 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
60 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
61 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
62 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
63 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
64 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
65 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
66 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
67 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
68 select ARCH_KEEP_MEMBLOCK
69 select ARCH_USE_CMPXCHG_LOCKREF
70 select ARCH_USE_GNU_PROPERTY
71 select ARCH_USE_QUEUED_RWLOCKS
72 select ARCH_USE_QUEUED_SPINLOCKS
73 select ARCH_USE_SYM_ANNOTATIONS
74 select ARCH_SUPPORTS_MEMORY_FAILURE
75 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
76 select ARCH_SUPPORTS_ATOMIC_RMW
77 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG)
78 select ARCH_SUPPORTS_NUMA_BALANCING
79 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
80 select ARCH_WANT_DEFAULT_BPF_JIT
81 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
82 select ARCH_WANT_FRAME_POINTERS
83 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
84 select ARCH_WANT_LD_ORPHAN_WARN
85 select ARCH_HAS_UBSAN_SANITIZE_ALL
89 select AUDIT_ARCH_COMPAT_GENERIC
90 select ARM_GIC_V2M if PCI
92 select ARM_GIC_V3_ITS if PCI
94 select BUILDTIME_TABLE_SORT
95 select CLONE_BACKWARDS
97 select CPU_PM if (SUSPEND || CPU_IDLE)
99 select DCACHE_WORD_ACCESS
100 select DMA_DIRECT_REMAP
103 select GENERIC_ALLOCATOR
104 select GENERIC_ARCH_TOPOLOGY
105 select GENERIC_CLOCKEVENTS
106 select GENERIC_CLOCKEVENTS_BROADCAST
107 select GENERIC_CPU_AUTOPROBE
108 select GENERIC_CPU_VULNERABILITIES
109 select GENERIC_EARLY_IOREMAP
110 select GENERIC_IDLE_POLL_SETUP
111 select GENERIC_IRQ_IPI
112 select GENERIC_IRQ_MULTI_HANDLER
113 select GENERIC_IRQ_PROBE
114 select GENERIC_IRQ_SHOW
115 select GENERIC_IRQ_SHOW_LEVEL
116 select GENERIC_PCI_IOMAP
117 select GENERIC_PTDUMP
118 select GENERIC_SCHED_CLOCK
119 select GENERIC_SMP_IDLE_THREAD
120 select GENERIC_STRNCPY_FROM_USER
121 select GENERIC_STRNLEN_USER
122 select GENERIC_TIME_VSYSCALL
123 select GENERIC_GETTIMEOFDAY
124 select GENERIC_VDSO_TIME_NS
125 select HANDLE_DOMAIN_IRQ
126 select HARDIRQS_SW_RESEND
130 select HAVE_ACPI_APEI if (ACPI && EFI)
131 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
132 select HAVE_ARCH_AUDITSYSCALL
133 select HAVE_ARCH_BITREVERSE
134 select HAVE_ARCH_COMPILER_H
135 select HAVE_ARCH_HUGE_VMAP
136 select HAVE_ARCH_JUMP_LABEL
137 select HAVE_ARCH_JUMP_LABEL_RELATIVE
138 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
139 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
140 select HAVE_ARCH_KGDB
141 select HAVE_ARCH_MMAP_RND_BITS
142 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
143 select HAVE_ARCH_PREL32_RELOCATIONS
144 select HAVE_ARCH_SECCOMP_FILTER
145 select HAVE_ARCH_STACKLEAK
146 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
147 select HAVE_ARCH_TRACEHOOK
148 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
149 select HAVE_ARCH_VMAP_STACK
150 select HAVE_ARM_SMCCC
151 select HAVE_ASM_MODVERSIONS
153 select HAVE_C_RECORDMCOUNT
154 select HAVE_CMPXCHG_DOUBLE
155 select HAVE_CMPXCHG_LOCAL
156 select HAVE_CONTEXT_TRACKING
157 select HAVE_DEBUG_BUGVERBOSE
158 select HAVE_DEBUG_KMEMLEAK
159 select HAVE_DMA_CONTIGUOUS
160 select HAVE_DYNAMIC_FTRACE
161 select HAVE_DYNAMIC_FTRACE_WITH_REGS \
162 if $(cc-option,-fpatchable-function-entry=2)
163 select HAVE_EFFICIENT_UNALIGNED_ACCESS
165 select HAVE_FTRACE_MCOUNT_RECORD
166 select HAVE_FUNCTION_TRACER
167 select HAVE_FUNCTION_ERROR_INJECTION
168 select HAVE_FUNCTION_GRAPH_TRACER
169 select HAVE_GCC_PLUGINS
170 select HAVE_HW_BREAKPOINT if PERF_EVENTS
171 select HAVE_IRQ_TIME_ACCOUNTING
173 select HAVE_PATA_PLATFORM
174 select HAVE_PERF_EVENTS
175 select HAVE_PERF_REGS
176 select HAVE_PERF_USER_STACK_DUMP
177 select HAVE_REGS_AND_STACK_ACCESS_API
178 select HAVE_FUNCTION_ARG_ACCESS_API
179 select HAVE_FUTEX_CMPXCHG if FUTEX
180 select MMU_GATHER_RCU_TABLE_FREE
182 select HAVE_STACKPROTECTOR
183 select HAVE_SYSCALL_TRACEPOINTS
185 select HAVE_KRETPROBES
186 select HAVE_GENERIC_VDSO
187 select IOMMU_DMA if IOMMU_SUPPORT
189 select IRQ_FORCED_THREADING
190 select MODULES_USE_ELF_RELA
191 select NEED_DMA_MAP_STATE
192 select NEED_SG_DMA_LENGTH
194 select OF_EARLY_FLATTREE
195 select PCI_DOMAINS_GENERIC if PCI
196 select PCI_ECAM if (ACPI && PCI)
197 select PCI_SYSCALL if PCI
203 select SYSCTL_EXCEPTION_TRACE
204 select THREAD_INFO_IN_TASK
206 ARM 64-bit (AArch64) Linux support.
214 config ARM64_PAGE_SHIFT
216 default 16 if ARM64_64K_PAGES
217 default 14 if ARM64_16K_PAGES
220 config ARM64_CONT_PTE_SHIFT
222 default 5 if ARM64_64K_PAGES
223 default 7 if ARM64_16K_PAGES
226 config ARM64_CONT_PMD_SHIFT
228 default 5 if ARM64_64K_PAGES
229 default 5 if ARM64_16K_PAGES
232 config ARCH_MMAP_RND_BITS_MIN
233 default 14 if ARM64_64K_PAGES
234 default 16 if ARM64_16K_PAGES
237 # max bits determined by the following formula:
238 # VA_BITS - PAGE_SHIFT - 3
239 config ARCH_MMAP_RND_BITS_MAX
240 default 19 if ARM64_VA_BITS=36
241 default 24 if ARM64_VA_BITS=39
242 default 27 if ARM64_VA_BITS=42
243 default 30 if ARM64_VA_BITS=47
244 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
245 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
246 default 33 if ARM64_VA_BITS=48
247 default 14 if ARM64_64K_PAGES
248 default 16 if ARM64_16K_PAGES
251 config ARCH_MMAP_RND_COMPAT_BITS_MIN
252 default 7 if ARM64_64K_PAGES
253 default 9 if ARM64_16K_PAGES
256 config ARCH_MMAP_RND_COMPAT_BITS_MAX
262 config STACKTRACE_SUPPORT
265 config ILLEGAL_POINTER_VALUE
267 default 0xdead000000000000
269 config LOCKDEP_SUPPORT
272 config TRACE_IRQFLAGS_SUPPORT
279 config GENERIC_BUG_RELATIVE_POINTERS
281 depends on GENERIC_BUG
283 config GENERIC_HWEIGHT
289 config GENERIC_CALIBRATE_DELAY
293 bool "Support DMA zone" if EXPERT
297 bool "Support DMA32 zone" if EXPERT
300 config ARCH_ENABLE_MEMORY_HOTPLUG
303 config ARCH_ENABLE_MEMORY_HOTREMOVE
309 config KERNEL_MODE_NEON
312 config FIX_EARLYCON_MEM
315 config PGTABLE_LEVELS
317 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
318 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
319 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
320 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
321 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
322 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
324 config ARCH_SUPPORTS_UPROBES
327 config ARCH_PROC_KCORE_TEXT
330 config BROKEN_GAS_INST
331 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
333 config KASAN_SHADOW_OFFSET
336 default 0xdfffa00000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
337 default 0xdfffd00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
338 default 0xdffffe8000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
339 default 0xdfffffd000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
340 default 0xdffffffa00000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
341 default 0xefff900000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
342 default 0xefffc80000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
343 default 0xeffffe4000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
344 default 0xefffffc800000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
345 default 0xeffffff900000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
346 default 0xffffffffffffffff
348 source "arch/arm64/Kconfig.platforms"
350 menu "Kernel Features"
352 menu "ARM errata workarounds via the alternatives framework"
354 config ARM64_WORKAROUND_CLEAN_CACHE
357 config ARM64_ERRATUM_826319
358 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
360 select ARM64_WORKAROUND_CLEAN_CACHE
362 This option adds an alternative code sequence to work around ARM
363 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
364 AXI master interface and an L2 cache.
366 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
367 and is unable to accept a certain write via this interface, it will
368 not progress on read data presented on the read data channel and the
371 The workaround promotes data cache clean instructions to
372 data cache clean-and-invalidate.
373 Please note that this does not necessarily enable the workaround,
374 as it depends on the alternative framework, which will only patch
375 the kernel if an affected CPU is detected.
379 config ARM64_ERRATUM_827319
380 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
382 select ARM64_WORKAROUND_CLEAN_CACHE
384 This option adds an alternative code sequence to work around ARM
385 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
386 master interface and an L2 cache.
388 Under certain conditions this erratum can cause a clean line eviction
389 to occur at the same time as another transaction to the same address
390 on the AMBA 5 CHI interface, which can cause data corruption if the
391 interconnect reorders the two transactions.
393 The workaround promotes data cache clean instructions to
394 data cache clean-and-invalidate.
395 Please note that this does not necessarily enable the workaround,
396 as it depends on the alternative framework, which will only patch
397 the kernel if an affected CPU is detected.
401 config ARM64_ERRATUM_824069
402 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
404 select ARM64_WORKAROUND_CLEAN_CACHE
406 This option adds an alternative code sequence to work around ARM
407 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
408 to a coherent interconnect.
410 If a Cortex-A53 processor is executing a store or prefetch for
411 write instruction at the same time as a processor in another
412 cluster is executing a cache maintenance operation to the same
413 address, then this erratum might cause a clean cache line to be
414 incorrectly marked as dirty.
416 The workaround promotes data cache clean instructions to
417 data cache clean-and-invalidate.
418 Please note that this option does not necessarily enable the
419 workaround, as it depends on the alternative framework, which will
420 only patch the kernel if an affected CPU is detected.
424 config ARM64_ERRATUM_819472
425 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
427 select ARM64_WORKAROUND_CLEAN_CACHE
429 This option adds an alternative code sequence to work around ARM
430 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
431 present when it is connected to a coherent interconnect.
433 If the processor is executing a load and store exclusive sequence at
434 the same time as a processor in another cluster is executing a cache
435 maintenance operation to the same address, then this erratum might
436 cause data corruption.
438 The workaround promotes data cache clean instructions to
439 data cache clean-and-invalidate.
440 Please note that this does not necessarily enable the workaround,
441 as it depends on the alternative framework, which will only patch
442 the kernel if an affected CPU is detected.
446 config ARM64_ERRATUM_832075
447 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
450 This option adds an alternative code sequence to work around ARM
451 erratum 832075 on Cortex-A57 parts up to r1p2.
453 Affected Cortex-A57 parts might deadlock when exclusive load/store
454 instructions to Write-Back memory are mixed with Device loads.
456 The workaround is to promote device loads to use Load-Acquire
458 Please note that this does not necessarily enable the workaround,
459 as it depends on the alternative framework, which will only patch
460 the kernel if an affected CPU is detected.
464 config ARM64_ERRATUM_834220
465 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
469 This option adds an alternative code sequence to work around ARM
470 erratum 834220 on Cortex-A57 parts up to r1p2.
472 Affected Cortex-A57 parts might report a Stage 2 translation
473 fault as the result of a Stage 1 fault for load crossing a
474 page boundary when there is a permission or device memory
475 alignment fault at Stage 1 and a translation fault at Stage 2.
477 The workaround is to verify that the Stage 1 translation
478 doesn't generate a fault before handling the Stage 2 fault.
479 Please note that this does not necessarily enable the workaround,
480 as it depends on the alternative framework, which will only patch
481 the kernel if an affected CPU is detected.
485 config ARM64_ERRATUM_845719
486 bool "Cortex-A53: 845719: a load might read incorrect data"
490 This option adds an alternative code sequence to work around ARM
491 erratum 845719 on Cortex-A53 parts up to r0p4.
493 When running a compat (AArch32) userspace on an affected Cortex-A53
494 part, a load at EL0 from a virtual address that matches the bottom 32
495 bits of the virtual address used by a recent load at (AArch64) EL1
496 might return incorrect data.
498 The workaround is to write the contextidr_el1 register on exception
499 return to a 32-bit task.
500 Please note that this does not necessarily enable the workaround,
501 as it depends on the alternative framework, which will only patch
502 the kernel if an affected CPU is detected.
506 config ARM64_ERRATUM_843419
507 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
509 select ARM64_MODULE_PLTS if MODULES
511 This option links the kernel with '--fix-cortex-a53-843419' and
512 enables PLT support to replace certain ADRP instructions, which can
513 cause subsequent memory accesses to use an incorrect address on
514 Cortex-A53 parts up to r0p4.
518 config ARM64_ERRATUM_1024718
519 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
522 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
524 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
525 update of the hardware dirty bit when the DBM/AP bits are updated
526 without a break-before-make. The workaround is to disable the usage
527 of hardware DBM locally on the affected cores. CPUs not affected by
528 this erratum will continue to use the feature.
532 config ARM64_ERRATUM_1418040
533 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
537 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
538 errata 1188873 and 1418040.
540 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
541 cause register corruption when accessing the timer registers
542 from AArch32 userspace.
546 config ARM64_WORKAROUND_SPECULATIVE_AT
549 config ARM64_ERRATUM_1165522
550 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
552 select ARM64_WORKAROUND_SPECULATIVE_AT
554 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
556 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
557 corrupted TLBs by speculating an AT instruction during a guest
562 config ARM64_ERRATUM_1319367
563 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
565 select ARM64_WORKAROUND_SPECULATIVE_AT
567 This option adds work arounds for ARM Cortex-A57 erratum 1319537
568 and A72 erratum 1319367
570 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
571 speculating an AT instruction during a guest context switch.
575 config ARM64_ERRATUM_1530923
576 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
578 select ARM64_WORKAROUND_SPECULATIVE_AT
580 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
582 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
583 corrupted TLBs by speculating an AT instruction during a guest
588 config ARM64_WORKAROUND_REPEAT_TLBI
591 config ARM64_ERRATUM_1286807
592 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
594 select ARM64_WORKAROUND_REPEAT_TLBI
596 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
598 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
599 address for a cacheable mapping of a location is being
600 accessed by a core while another core is remapping the virtual
601 address to a new physical page using the recommended
602 break-before-make sequence, then under very rare circumstances
603 TLBI+DSB completes before a read using the translation being
604 invalidated has been observed by other observers. The
605 workaround repeats the TLBI+DSB operation.
607 config ARM64_ERRATUM_1463225
608 bool "Cortex-A76: Software Step might prevent interrupt recognition"
611 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
613 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
614 of a system call instruction (SVC) can prevent recognition of
615 subsequent interrupts when software stepping is disabled in the
616 exception handler of the system call and either kernel debugging
617 is enabled or VHE is in use.
619 Work around the erratum by triggering a dummy step exception
620 when handling a system call from a task that is being stepped
621 in a VHE configuration of the kernel.
625 config ARM64_ERRATUM_1542419
626 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
629 This option adds a workaround for ARM Neoverse-N1 erratum
632 Affected Neoverse-N1 cores could execute a stale instruction when
633 modified by another CPU. The workaround depends on a firmware
636 Workaround the issue by hiding the DIC feature from EL0. This
637 forces user-space to perform cache maintenance.
641 config ARM64_ERRATUM_1508412
642 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
645 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
647 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
648 of a store-exclusive or read of PAR_EL1 and a load with device or
649 non-cacheable memory attributes. The workaround depends on a firmware
652 KVM guests must also have the workaround implemented or they can
655 Work around the issue by inserting DMB SY barriers around PAR_EL1
656 register reads and warning KVM users. The DMB barrier is sufficient
657 to prevent a speculative PAR_EL1 read.
661 config CAVIUM_ERRATUM_22375
662 bool "Cavium erratum 22375, 24313"
665 Enable workaround for errata 22375 and 24313.
667 This implements two gicv3-its errata workarounds for ThunderX. Both
668 with a small impact affecting only ITS table allocation.
670 erratum 22375: only alloc 8MB table size
671 erratum 24313: ignore memory access type
673 The fixes are in ITS initialization and basically ignore memory access
674 type and table size provided by the TYPER and BASER registers.
678 config CAVIUM_ERRATUM_23144
679 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
683 ITS SYNC command hang for cross node io and collections/cpu mapping.
687 config CAVIUM_ERRATUM_23154
688 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
691 The gicv3 of ThunderX requires a modified version for
692 reading the IAR status to ensure data synchronization
693 (access to icc_iar1_el1 is not sync'ed before and after).
697 config CAVIUM_ERRATUM_27456
698 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
701 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
702 instructions may cause the icache to become corrupted if it
703 contains data for a non-current ASID. The fix is to
704 invalidate the icache when changing the mm context.
708 config CAVIUM_ERRATUM_30115
709 bool "Cavium erratum 30115: Guest may disable interrupts in host"
712 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
713 1.2, and T83 Pass 1.0, KVM guest execution may disable
714 interrupts in host. Trapping both GICv3 group-0 and group-1
715 accesses sidesteps the issue.
719 config CAVIUM_TX2_ERRATUM_219
720 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
723 On Cavium ThunderX2, a load, store or prefetch instruction between a
724 TTBR update and the corresponding context synchronizing operation can
725 cause a spurious Data Abort to be delivered to any hardware thread in
728 Work around the issue by avoiding the problematic code sequence and
729 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
730 trap handler performs the corresponding register access, skips the
731 instruction and ensures context synchronization by virtue of the
736 config FUJITSU_ERRATUM_010001
737 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
740 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
741 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
742 accesses may cause undefined fault (Data abort, DFSC=0b111111).
743 This fault occurs under a specific hardware condition when a
744 load/store instruction performs an address translation using:
745 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
746 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
747 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
748 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
750 The workaround is to ensure these bits are clear in TCR_ELx.
751 The workaround only affects the Fujitsu-A64FX.
755 config HISILICON_ERRATUM_161600802
756 bool "Hip07 161600802: Erroneous redistributor VLPI base"
759 The HiSilicon Hip07 SoC uses the wrong redistributor base
760 when issued ITS commands such as VMOVP and VMAPP, and requires
761 a 128kB offset to be applied to the target address in this commands.
765 config QCOM_FALKOR_ERRATUM_1003
766 bool "Falkor E1003: Incorrect translation due to ASID change"
769 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
770 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
771 in TTBR1_EL1, this situation only occurs in the entry trampoline and
772 then only for entries in the walk cache, since the leaf translation
773 is unchanged. Work around the erratum by invalidating the walk cache
774 entries for the trampoline before entering the kernel proper.
776 config QCOM_FALKOR_ERRATUM_1009
777 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
779 select ARM64_WORKAROUND_REPEAT_TLBI
781 On Falkor v1, the CPU may prematurely complete a DSB following a
782 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
783 one more time to fix the issue.
787 config QCOM_QDF2400_ERRATUM_0065
788 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
791 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
792 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
793 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
797 config QCOM_FALKOR_ERRATUM_E1041
798 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
801 Falkor CPU may speculatively fetch instructions from an improper
802 memory location when MMU translation is changed from SCTLR_ELn[M]=1
803 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
807 config SOCIONEXT_SYNQUACER_PREITS
808 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
811 Socionext Synquacer SoCs implement a separate h/w block to generate
812 MSI doorbell writes with non-zero values for the device ID.
821 default ARM64_4K_PAGES
823 Page size (translation granule) configuration.
825 config ARM64_4K_PAGES
828 This feature enables 4KB pages support.
830 config ARM64_16K_PAGES
833 The system will use 16KB pages support. AArch32 emulation
834 requires applications compiled with 16K (or a multiple of 16K)
837 config ARM64_64K_PAGES
840 This feature enables 64KB pages support (4KB by default)
841 allowing only two levels of page tables and faster TLB
842 look-up. AArch32 emulation requires applications compiled
843 with 64K aligned segments.
848 prompt "Virtual address space size"
849 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
850 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
851 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
853 Allows choosing one of multiple possible virtual address
854 space sizes. The level of translation table is determined by
855 a combination of page size and virtual address space size.
857 config ARM64_VA_BITS_36
858 bool "36-bit" if EXPERT
859 depends on ARM64_16K_PAGES
861 config ARM64_VA_BITS_39
863 depends on ARM64_4K_PAGES
865 config ARM64_VA_BITS_42
867 depends on ARM64_64K_PAGES
869 config ARM64_VA_BITS_47
871 depends on ARM64_16K_PAGES
873 config ARM64_VA_BITS_48
876 config ARM64_VA_BITS_52
878 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
880 Enable 52-bit virtual addressing for userspace when explicitly
881 requested via a hint to mmap(). The kernel will also use 52-bit
882 virtual addresses for its own mappings (provided HW support for
883 this feature is available, otherwise it reverts to 48-bit).
885 NOTE: Enabling 52-bit virtual addressing in conjunction with
886 ARMv8.3 Pointer Authentication will result in the PAC being
887 reduced from 7 bits to 3 bits, which may have a significant
888 impact on its susceptibility to brute-force attacks.
890 If unsure, select 48-bit virtual addressing instead.
894 config ARM64_FORCE_52BIT
895 bool "Force 52-bit virtual addresses for userspace"
896 depends on ARM64_VA_BITS_52 && EXPERT
898 For systems with 52-bit userspace VAs enabled, the kernel will attempt
899 to maintain compatibility with older software by providing 48-bit VAs
900 unless a hint is supplied to mmap.
902 This configuration option disables the 48-bit compatibility logic, and
903 forces all userspace addresses to be 52-bit on HW that supports it. One
904 should only enable this configuration option for stress testing userspace
905 memory management code. If unsure say N here.
909 default 36 if ARM64_VA_BITS_36
910 default 39 if ARM64_VA_BITS_39
911 default 42 if ARM64_VA_BITS_42
912 default 47 if ARM64_VA_BITS_47
913 default 48 if ARM64_VA_BITS_48
914 default 52 if ARM64_VA_BITS_52
917 prompt "Physical address space size"
918 default ARM64_PA_BITS_48
920 Choose the maximum physical address range that the kernel will
923 config ARM64_PA_BITS_48
926 config ARM64_PA_BITS_52
927 bool "52-bit (ARMv8.2)"
928 depends on ARM64_64K_PAGES
929 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
931 Enable support for a 52-bit physical address space, introduced as
932 part of the ARMv8.2-LPA extension.
934 With this enabled, the kernel will also continue to work on CPUs that
935 do not support ARMv8.2-LPA, but with some added memory overhead (and
936 minor performance overhead).
942 default 48 if ARM64_PA_BITS_48
943 default 52 if ARM64_PA_BITS_52
947 default CPU_LITTLE_ENDIAN
949 Select the endianness of data accesses performed by the CPU. Userspace
950 applications will need to be compiled and linked for the endianness
951 that is selected here.
953 config CPU_BIG_ENDIAN
954 bool "Build big-endian kernel"
956 Say Y if you plan on running a kernel with a big-endian userspace.
958 config CPU_LITTLE_ENDIAN
959 bool "Build little-endian kernel"
961 Say Y if you plan on running a kernel with a little-endian userspace.
962 This is usually the case for distributions targeting arm64.
967 bool "Multi-core scheduler support"
969 Multi-core scheduler support improves the CPU scheduler's decision
970 making when dealing with multi-core CPU chips at a cost of slightly
971 increased overhead in some places. If unsure say N here.
974 bool "SMT scheduler support"
976 Improves the CPU scheduler's decision making when dealing with
977 MultiThreading at a cost of slightly increased overhead in some
978 places. If unsure say N here.
981 int "Maximum number of CPUs (2-4096)"
986 bool "Support for hot-pluggable CPUs"
987 select GENERIC_IRQ_MIGRATION
989 Say Y here to experiment with turning CPUs off and on. CPUs
990 can be controlled through /sys/devices/system/cpu.
992 # Common NUMA Features
994 bool "NUMA Memory Allocation and Scheduler Support"
995 select ACPI_NUMA if ACPI
998 Enable NUMA (Non-Uniform Memory Access) support.
1000 The kernel will try to allocate memory used by a CPU on the
1001 local memory of the CPU and add some more
1002 NUMA awareness to the kernel.
1005 int "Maximum NUMA Nodes (as a power of 2)"
1008 depends on NEED_MULTIPLE_NODES
1010 Specify the maximum number of NUMA Nodes available on the target
1011 system. Increases memory reserved to accommodate various tables.
1013 config USE_PERCPU_NUMA_NODE_ID
1017 config HAVE_SETUP_PER_CPU_AREA
1021 config NEED_PER_CPU_EMBED_FIRST_CHUNK
1025 config HOLES_IN_ZONE
1028 source "kernel/Kconfig.hz"
1030 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
1033 config ARCH_SPARSEMEM_ENABLE
1035 select SPARSEMEM_VMEMMAP_ENABLE
1037 config ARCH_SPARSEMEM_DEFAULT
1038 def_bool ARCH_SPARSEMEM_ENABLE
1040 config ARCH_SELECT_MEMORY_MODEL
1041 def_bool ARCH_SPARSEMEM_ENABLE
1043 config ARCH_FLATMEM_ENABLE
1046 config HAVE_ARCH_PFN_VALID
1049 config HW_PERF_EVENTS
1053 config SYS_SUPPORTS_HUGETLBFS
1056 config ARCH_WANT_HUGE_PMD_SHARE
1058 config ARCH_HAS_CACHE_LINE_SIZE
1061 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
1062 def_bool y if PGTABLE_LEVELS > 2
1064 # Supported by clang >= 7.0
1065 config CC_HAVE_SHADOW_CALL_STACK
1066 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1069 bool "Enable paravirtualization code"
1071 This changes the kernel so it can modify itself when it is run
1072 under a hypervisor, potentially improving performance significantly
1073 over full virtualization.
1075 config PARAVIRT_TIME_ACCOUNTING
1076 bool "Paravirtual steal time accounting"
1079 Select this option to enable fine granularity task steal time
1080 accounting. Time spent executing other tasks in parallel with
1081 the current vCPU is discounted from the vCPU power. To account for
1082 that, there can be a small performance impact.
1084 If in doubt, say N here.
1087 depends on PM_SLEEP_SMP
1089 bool "kexec system call"
1091 kexec is a system call that implements the ability to shutdown your
1092 current kernel, and to start another kernel. It is like a reboot
1093 but it is independent of the system firmware. And like a reboot
1094 you can start any kernel with it, not just Linux.
1097 bool "kexec file based system call"
1100 This is new version of kexec system call. This system call is
1101 file based and takes file descriptors as system call argument
1102 for kernel and initramfs as opposed to list of segments as
1103 accepted by previous system call.
1106 bool "Verify kernel signature during kexec_file_load() syscall"
1107 depends on KEXEC_FILE
1109 Select this option to verify a signature with loaded kernel
1110 image. If configured, any attempt of loading a image without
1111 valid signature will fail.
1113 In addition to that option, you need to enable signature
1114 verification for the corresponding kernel image type being
1115 loaded in order for this to work.
1117 config KEXEC_IMAGE_VERIFY_SIG
1118 bool "Enable Image signature verification support"
1120 depends on KEXEC_SIG
1121 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1123 Enable Image signature verification support.
1125 comment "Support for PE file signature verification disabled"
1126 depends on KEXEC_SIG
1127 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1130 bool "Build kdump crash kernel"
1132 Generate crash dump after being started by kexec. This should
1133 be normally only set in special crash dump kernels which are
1134 loaded in the main kernel with kexec-tools into a specially
1135 reserved region and then later executed after a crash by
1138 For more details see Documentation/admin-guide/kdump/kdump.rst
1145 bool "Xen guest support on ARM64"
1146 depends on ARM64 && OF
1150 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1152 config FORCE_MAX_ZONEORDER
1154 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1155 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1158 The kernel memory allocator divides physically contiguous memory
1159 blocks into "zones", where each zone is a power of two number of
1160 pages. This option selects the largest power of two that the kernel
1161 keeps in the memory allocator. If you need to allocate very large
1162 blocks of physically contiguous memory, then you may need to
1163 increase this value.
1165 This config option is actually maximum order plus one. For example,
1166 a value of 11 means that the largest free memory block is 2^10 pages.
1168 We make sure that we can allocate upto a HugePage size for each configuration.
1170 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1172 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1173 4M allocations matching the default size used by generic code.
1175 config UNMAP_KERNEL_AT_EL0
1176 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1179 Speculation attacks against some high-performance processors can
1180 be used to bypass MMU permission checks and leak kernel data to
1181 userspace. This can be defended against by unmapping the kernel
1182 when running in userspace, mapping it back in on exception entry
1183 via a trampoline page in the vector table.
1187 config RODATA_FULL_DEFAULT_ENABLED
1188 bool "Apply r/o permissions of VM areas also to their linear aliases"
1191 Apply read-only attributes of VM areas to the linear alias of
1192 the backing pages as well. This prevents code or read-only data
1193 from being modified (inadvertently or intentionally) via another
1194 mapping of the same memory page. This additional enhancement can
1195 be turned off at runtime by passing rodata=[off|on] (and turned on
1196 with rodata=full if this option is set to 'n')
1198 This requires the linear region to be mapped down to pages,
1199 which may adversely affect performance in some cases.
1201 config ARM64_SW_TTBR0_PAN
1202 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1204 Enabling this option prevents the kernel from accessing
1205 user-space memory directly by pointing TTBR0_EL1 to a reserved
1206 zeroed area and reserved ASID. The user access routines
1207 restore the valid TTBR0_EL1 temporarily.
1209 config ARM64_TAGGED_ADDR_ABI
1210 bool "Enable the tagged user addresses syscall ABI"
1213 When this option is enabled, user applications can opt in to a
1214 relaxed ABI via prctl() allowing tagged addresses to be passed
1215 to system calls as pointer arguments. For details, see
1216 Documentation/arm64/tagged-address-abi.rst.
1219 bool "Kernel support for 32-bit EL0"
1220 depends on ARM64_4K_PAGES || EXPERT
1221 select COMPAT_BINFMT_ELF if BINFMT_ELF
1223 select OLD_SIGSUSPEND3
1224 select COMPAT_OLD_SIGACTION
1226 This option enables support for a 32-bit EL0 running under a 64-bit
1227 kernel at EL1. AArch32-specific components such as system calls,
1228 the user helper functions, VFP support and the ptrace interface are
1229 handled appropriately by the kernel.
1231 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1232 that you will only be able to execute AArch32 binaries that were compiled
1233 with page size aligned segments.
1235 If you want to execute 32-bit userspace applications, say Y.
1239 config KUSER_HELPERS
1240 bool "Enable kuser helpers page for 32-bit applications"
1243 Warning: disabling this option may break 32-bit user programs.
1245 Provide kuser helpers to compat tasks. The kernel provides
1246 helper code to userspace in read only form at a fixed location
1247 to allow userspace to be independent of the CPU type fitted to
1248 the system. This permits binaries to be run on ARMv4 through
1249 to ARMv8 without modification.
1251 See Documentation/arm/kernel_user_helpers.rst for details.
1253 However, the fixed address nature of these helpers can be used
1254 by ROP (return orientated programming) authors when creating
1257 If all of the binaries and libraries which run on your platform
1258 are built specifically for your platform, and make no use of
1259 these helpers, then you can turn this option off to hinder
1260 such exploits. However, in that case, if a binary or library
1261 relying on those helpers is run, it will not function correctly.
1263 Say N here only if you are absolutely certain that you do not
1264 need these helpers; otherwise, the safe option is to say Y.
1267 bool "Enable vDSO for 32-bit applications"
1268 depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1269 select GENERIC_COMPAT_VDSO
1272 Place in the process address space of 32-bit applications an
1273 ELF shared object providing fast implementations of gettimeofday
1276 You must have a 32-bit build of glibc 2.22 or later for programs
1277 to seamlessly take advantage of this.
1279 config THUMB2_COMPAT_VDSO
1280 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1281 depends on COMPAT_VDSO
1284 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1285 otherwise with '-marm'.
1287 menuconfig ARMV8_DEPRECATED
1288 bool "Emulate deprecated/obsolete ARMv8 instructions"
1291 Legacy software support may require certain instructions
1292 that have been deprecated or obsoleted in the architecture.
1294 Enable this config to enable selective emulation of these
1301 config SWP_EMULATION
1302 bool "Emulate SWP/SWPB instructions"
1304 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1305 they are always undefined. Say Y here to enable software
1306 emulation of these instructions for userspace using LDXR/STXR.
1307 This feature can be controlled at runtime with the abi.swp
1308 sysctl which is disabled by default.
1310 In some older versions of glibc [<=2.8] SWP is used during futex
1311 trylock() operations with the assumption that the code will not
1312 be preempted. This invalid assumption may be more likely to fail
1313 with SWP emulation enabled, leading to deadlock of the user
1316 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1317 on an external transaction monitoring block called a global
1318 monitor to maintain update atomicity. If your system does not
1319 implement a global monitor, this option can cause programs that
1320 perform SWP operations to uncached memory to deadlock.
1324 config CP15_BARRIER_EMULATION
1325 bool "Emulate CP15 Barrier instructions"
1327 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1328 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1329 strongly recommended to use the ISB, DSB, and DMB
1330 instructions instead.
1332 Say Y here to enable software emulation of these
1333 instructions for AArch32 userspace code. When this option is
1334 enabled, CP15 barrier usage is traced which can help
1335 identify software that needs updating. This feature can be
1336 controlled at runtime with the abi.cp15_barrier sysctl.
1340 config SETEND_EMULATION
1341 bool "Emulate SETEND instruction"
1343 The SETEND instruction alters the data-endianness of the
1344 AArch32 EL0, and is deprecated in ARMv8.
1346 Say Y here to enable software emulation of the instruction
1347 for AArch32 userspace code. This feature can be controlled
1348 at runtime with the abi.setend sysctl.
1350 Note: All the cpus on the system must have mixed endian support at EL0
1351 for this feature to be enabled. If a new CPU - which doesn't support mixed
1352 endian - is hotplugged in after this feature has been enabled, there could
1353 be unexpected results in the applications.
1360 menu "ARMv8.1 architectural features"
1362 config ARM64_HW_AFDBM
1363 bool "Support for hardware updates of the Access and Dirty page flags"
1366 The ARMv8.1 architecture extensions introduce support for
1367 hardware updates of the access and dirty information in page
1368 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1369 capable processors, accesses to pages with PTE_AF cleared will
1370 set this bit instead of raising an access flag fault.
1371 Similarly, writes to read-only pages with the DBM bit set will
1372 clear the read-only bit (AP[2]) instead of raising a
1375 Kernels built with this configuration option enabled continue
1376 to work on pre-ARMv8.1 hardware and the performance impact is
1377 minimal. If unsure, say Y.
1380 bool "Enable support for Privileged Access Never (PAN)"
1383 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1384 prevents the kernel or hypervisor from accessing user-space (EL0)
1387 Choosing this option will cause any unprotected (not using
1388 copy_to_user et al) memory access to fail with a permission fault.
1390 The feature is detected at runtime, and will remain as a 'nop'
1391 instruction if the cpu does not implement the feature.
1393 config ARM64_LSE_ATOMICS
1395 default ARM64_USE_LSE_ATOMICS
1396 depends on $(as-instr,.arch_extension lse)
1398 config ARM64_USE_LSE_ATOMICS
1399 bool "Atomic instructions"
1400 depends on JUMP_LABEL
1403 As part of the Large System Extensions, ARMv8.1 introduces new
1404 atomic instructions that are designed specifically to scale in
1407 Say Y here to make use of these instructions for the in-kernel
1408 atomic routines. This incurs a small overhead on CPUs that do
1409 not support these instructions and requires the kernel to be
1410 built with binutils >= 2.25 in order for the new instructions
1414 bool "Enable support for Virtualization Host Extensions (VHE)"
1417 Virtualization Host Extensions (VHE) allow the kernel to run
1418 directly at EL2 (instead of EL1) on processors that support
1419 it. This leads to better performance for KVM, as they reduce
1420 the cost of the world switch.
1422 Selecting this option allows the VHE feature to be detected
1423 at runtime, and does not affect processors that do not
1424 implement this feature.
1428 menu "ARMv8.2 architectural features"
1431 bool "Enable support for User Access Override (UAO)"
1434 User Access Override (UAO; part of the ARMv8.2 Extensions)
1435 causes the 'unprivileged' variant of the load/store instructions to
1436 be overridden to be privileged.
1438 This option changes get_user() and friends to use the 'unprivileged'
1439 variant of the load/store instructions. This ensures that user-space
1440 really did have access to the supplied memory. When addr_limit is
1441 set to kernel memory the UAO bit will be set, allowing privileged
1442 access to kernel memory.
1444 Choosing this option will cause copy_to_user() et al to use user-space
1447 The feature is detected at runtime, the kernel will use the
1448 regular load/store instructions if the cpu does not implement the
1452 bool "Enable support for persistent memory"
1453 select ARCH_HAS_PMEM_API
1454 select ARCH_HAS_UACCESS_FLUSHCACHE
1456 Say Y to enable support for the persistent memory API based on the
1457 ARMv8.2 DCPoP feature.
1459 The feature is detected at runtime, and the kernel will use DC CVAC
1460 operations if DC CVAP is not supported (following the behaviour of
1461 DC CVAP itself if the system does not define a point of persistence).
1463 config ARM64_RAS_EXTN
1464 bool "Enable support for RAS CPU Extensions"
1467 CPUs that support the Reliability, Availability and Serviceability
1468 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1469 errors, classify them and report them to software.
1471 On CPUs with these extensions system software can use additional
1472 barriers to determine if faults are pending and read the
1473 classification from a new set of registers.
1475 Selecting this feature will allow the kernel to use these barriers
1476 and access the new registers if the system supports the extension.
1477 Platform RAS features may additionally depend on firmware support.
1480 bool "Enable support for Common Not Private (CNP) translations"
1482 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1484 Common Not Private (CNP) allows translation table entries to
1485 be shared between different PEs in the same inner shareable
1486 domain, so the hardware can use this fact to optimise the
1487 caching of such entries in the TLB.
1489 Selecting this option allows the CNP feature to be detected
1490 at runtime, and does not affect PEs that do not implement
1495 menu "ARMv8.3 architectural features"
1497 config ARM64_PTR_AUTH
1498 bool "Enable support for pointer authentication"
1500 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1501 # Modern compilers insert a .note.gnu.property section note for PAC
1502 # which is only understood by binutils starting with version 2.33.1.
1503 depends on LD_IS_LLD || LD_VERSION >= 233010000 || (CC_IS_GCC && GCC_VERSION < 90100)
1504 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1505 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1507 Pointer authentication (part of the ARMv8.3 Extensions) provides
1508 instructions for signing and authenticating pointers against secret
1509 keys, which can be used to mitigate Return Oriented Programming (ROP)
1512 This option enables these instructions at EL0 (i.e. for userspace).
1513 Choosing this option will cause the kernel to initialise secret keys
1514 for each process at exec() time, with these keys being
1515 context-switched along with the process.
1517 If the compiler supports the -mbranch-protection or
1518 -msign-return-address flag (e.g. GCC 7 or later), then this option
1519 will also cause the kernel itself to be compiled with return address
1520 protection. In this case, and if the target hardware is known to
1521 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1522 disabled with minimal loss of protection.
1524 The feature is detected at runtime. If the feature is not present in
1525 hardware it will not be advertised to userspace/KVM guest nor will it
1528 If the feature is present on the boot CPU but not on a late CPU, then
1529 the late CPU will be parked. Also, if the boot CPU does not have
1530 address auth and the late CPU has then the late CPU will still boot
1531 but with the feature disabled. On such a system, this option should
1534 This feature works with FUNCTION_GRAPH_TRACER option only if
1535 DYNAMIC_FTRACE_WITH_REGS is enabled.
1537 config CC_HAS_BRANCH_PROT_PAC_RET
1538 # GCC 9 or later, clang 8 or later
1539 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1541 config CC_HAS_SIGN_RETURN_ADDRESS
1543 def_bool $(cc-option,-msign-return-address=all)
1546 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1548 config AS_HAS_CFI_NEGATE_RA_STATE
1549 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1553 menu "ARMv8.4 architectural features"
1555 config ARM64_AMU_EXTN
1556 bool "Enable support for the Activity Monitors Unit CPU extension"
1559 The activity monitors extension is an optional extension introduced
1560 by the ARMv8.4 CPU architecture. This enables support for version 1
1561 of the activity monitors architecture, AMUv1.
1563 To enable the use of this extension on CPUs that implement it, say Y.
1565 Note that for architectural reasons, firmware _must_ implement AMU
1566 support when running on CPUs that present the activity monitors
1567 extension. The required support is present in:
1568 * Version 1.5 and later of the ARM Trusted Firmware
1570 For kernels that have this configuration enabled but boot with broken
1571 firmware, you may need to say N here until the firmware is fixed.
1572 Otherwise you may experience firmware panics or lockups when
1573 accessing the counter registers. Even if you are not observing these
1574 symptoms, the values returned by the register reads might not
1575 correctly reflect reality. Most commonly, the value read will be 0,
1576 indicating that the counter is not enabled.
1578 config AS_HAS_ARMV8_4
1579 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1581 config ARM64_TLB_RANGE
1582 bool "Enable support for tlbi range feature"
1584 depends on AS_HAS_ARMV8_4
1586 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1587 range of input addresses.
1589 The feature introduces new assembly instructions, and they were
1590 support when binutils >= 2.30.
1594 menu "ARMv8.5 architectural features"
1597 bool "Branch Target Identification support"
1600 Branch Target Identification (part of the ARMv8.5 Extensions)
1601 provides a mechanism to limit the set of locations to which computed
1602 branch instructions such as BR or BLR can jump.
1604 To make use of BTI on CPUs that support it, say Y.
1606 BTI is intended to provide complementary protection to other control
1607 flow integrity protection mechanisms, such as the Pointer
1608 authentication mechanism provided as part of the ARMv8.3 Extensions.
1609 For this reason, it does not make sense to enable this option without
1610 also enabling support for pointer authentication. Thus, when
1611 enabling this option you should also select ARM64_PTR_AUTH=y.
1613 Userspace binaries must also be specifically compiled to make use of
1614 this mechanism. If you say N here or the hardware does not support
1615 BTI, such binaries can still run, but you get no additional
1616 enforcement of branch destinations.
1618 config ARM64_BTI_KERNEL
1619 bool "Use Branch Target Identification for kernel"
1621 depends on ARM64_BTI
1622 depends on ARM64_PTR_AUTH
1623 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1624 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1625 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1626 depends on !(CC_IS_CLANG && GCOV_KERNEL)
1627 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1629 Build the kernel with Branch Target Identification annotations
1630 and enable enforcement of this for kernel code. When this option
1631 is enabled and the system supports BTI all kernel code including
1632 modular code must have BTI enabled.
1634 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1635 # GCC 9 or later, clang 8 or later
1636 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1639 bool "Enable support for E0PD"
1642 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1643 that EL0 accesses made via TTBR1 always fault in constant time,
1644 providing similar benefits to KASLR as those provided by KPTI, but
1645 with lower overhead and without disrupting legitimate access to
1646 kernel memory such as SPE.
1648 This option enables E0PD for TTBR1 where available.
1651 bool "Enable support for random number generation"
1654 Random number generation (part of the ARMv8.5 Extensions)
1655 provides a high bandwidth, cryptographically secure
1656 hardware random number generator.
1658 config ARM64_AS_HAS_MTE
1659 # Initial support for MTE went in binutils 2.32.0, checked with
1660 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1661 # as a late addition to the final architecture spec (LDGM/STGM)
1662 # is only supported in the newer 2.32.x and 2.33 binutils
1663 # versions, hence the extra "stgm" instruction check below.
1664 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1667 bool "Memory Tagging Extension support"
1669 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1670 select ARCH_USES_HIGH_VMA_FLAGS
1672 Memory Tagging (part of the ARMv8.5 Extensions) provides
1673 architectural support for run-time, always-on detection of
1674 various classes of memory error to aid with software debugging
1675 to eliminate vulnerabilities arising from memory-unsafe
1678 This option enables the support for the Memory Tagging
1679 Extension at EL0 (i.e. for userspace).
1681 Selecting this option allows the feature to be detected at
1682 runtime. Any secondary CPU not implementing this feature will
1683 not be allowed a late bring-up.
1685 Userspace binaries that want to use this feature must
1686 explicitly opt in. The mechanism for the userspace is
1689 Documentation/arm64/memory-tagging-extension.rst.
1694 bool "ARM Scalable Vector Extension support"
1696 depends on !KVM || ARM64_VHE
1698 The Scalable Vector Extension (SVE) is an extension to the AArch64
1699 execution state which complements and extends the SIMD functionality
1700 of the base architecture to support much larger vectors and to enable
1701 additional vectorisation opportunities.
1703 To enable use of this extension on CPUs that implement it, say Y.
1705 On CPUs that support the SVE2 extensions, this option will enable
1708 Note that for architectural reasons, firmware _must_ implement SVE
1709 support when running on SVE capable hardware. The required support
1712 * version 1.5 and later of the ARM Trusted Firmware
1713 * the AArch64 boot wrapper since commit 5e1261e08abf
1714 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1716 For other firmware implementations, consult the firmware documentation
1719 If you need the kernel to boot on SVE-capable hardware with broken
1720 firmware, you may need to say N here until you get your firmware
1721 fixed. Otherwise, you may experience firmware panics or lockups when
1722 booting the kernel. If unsure and you are not observing these
1723 symptoms, you should assume that it is safe to say Y.
1725 CPUs that support SVE are architecturally required to support the
1726 Virtualization Host Extensions (VHE), so the kernel makes no
1727 provision for supporting SVE alongside KVM without VHE enabled.
1728 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1729 KVM in the same kernel image.
1731 config ARM64_MODULE_PLTS
1732 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1734 select HAVE_MOD_ARCH_SPECIFIC
1736 Allocate PLTs when loading modules so that jumps and calls whose
1737 targets are too far away for their relative offsets to be encoded
1738 in the instructions themselves can be bounced via veneers in the
1739 module's PLT. This allows modules to be allocated in the generic
1740 vmalloc area after the dedicated module memory area has been
1743 When running with address space randomization (KASLR), the module
1744 region itself may be too far away for ordinary relative jumps and
1745 calls, and so in that case, module PLTs are required and cannot be
1748 Specific errata workaround(s) might also force module PLTs to be
1749 enabled (ARM64_ERRATUM_843419).
1751 config ARM64_PSEUDO_NMI
1752 bool "Support for NMI-like interrupts"
1755 Adds support for mimicking Non-Maskable Interrupts through the use of
1756 GIC interrupt priority. This support requires version 3 or later of
1759 This high priority configuration for interrupts needs to be
1760 explicitly enabled by setting the kernel parameter
1761 "irqchip.gicv3_pseudo_nmi" to 1.
1766 config ARM64_DEBUG_PRIORITY_MASKING
1767 bool "Debug interrupt priority masking"
1769 This adds runtime checks to functions enabling/disabling
1770 interrupts when using priority masking. The additional checks verify
1771 the validity of ICC_PMR_EL1 when calling concerned functions.
1777 bool "Build a relocatable kernel image" if EXPERT
1778 select ARCH_HAS_RELR
1781 This builds the kernel as a Position Independent Executable (PIE),
1782 which retains all relocation metadata required to relocate the
1783 kernel binary at runtime to a different virtual address than the
1784 address it was linked at.
1785 Since AArch64 uses the RELA relocation format, this requires a
1786 relocation pass at runtime even if the kernel is loaded at the
1787 same address it was linked at.
1789 config RANDOMIZE_BASE
1790 bool "Randomize the address of the kernel image"
1791 select ARM64_MODULE_PLTS if MODULES
1794 Randomizes the virtual address at which the kernel image is
1795 loaded, as a security feature that deters exploit attempts
1796 relying on knowledge of the location of kernel internals.
1798 It is the bootloader's job to provide entropy, by passing a
1799 random u64 value in /chosen/kaslr-seed at kernel entry.
1801 When booting via the UEFI stub, it will invoke the firmware's
1802 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1803 to the kernel proper. In addition, it will randomise the physical
1804 location of the kernel Image as well.
1808 config RANDOMIZE_MODULE_REGION_FULL
1809 bool "Randomize the module region over a 4 GB range"
1810 depends on RANDOMIZE_BASE
1813 Randomizes the location of the module region inside a 4 GB window
1814 covering the core kernel. This way, it is less likely for modules
1815 to leak information about the location of core kernel data structures
1816 but it does imply that function calls between modules and the core
1817 kernel will need to be resolved via veneers in the module PLT.
1819 When this option is not set, the module region will be randomized over
1820 a limited range that contains the [_stext, _etext] interval of the
1821 core kernel, so branch relocations are always in range.
1823 config CC_HAVE_STACKPROTECTOR_SYSREG
1824 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1826 config STACKPROTECTOR_PER_TASK
1828 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1834 config ARM64_ACPI_PARKING_PROTOCOL
1835 bool "Enable support for the ARM64 ACPI parking protocol"
1838 Enable support for the ARM64 ACPI parking protocol. If disabled
1839 the kernel will not allow booting through the ARM64 ACPI parking
1840 protocol even if the corresponding data is present in the ACPI
1844 string "Default kernel command string"
1847 Provide a set of default command-line options at build time by
1848 entering them here. As a minimum, you should specify the the
1849 root device (e.g. root=/dev/nfs).
1851 config CMDLINE_FORCE
1852 bool "Always use the default kernel command string"
1853 depends on CMDLINE != ""
1855 Always use the default kernel command string, even if the boot
1856 loader passes other arguments to the kernel.
1857 This is useful if you cannot or don't want to change the
1858 command-line options your boot loader passes to the kernel.
1864 bool "UEFI runtime support"
1865 depends on OF && !CPU_BIG_ENDIAN
1866 depends on KERNEL_MODE_NEON
1867 select ARCH_SUPPORTS_ACPI
1870 select EFI_PARAMS_FROM_FDT
1871 select EFI_RUNTIME_WRAPPERS
1873 select EFI_GENERIC_STUB
1876 This option provides support for runtime services provided
1877 by UEFI firmware (such as non-volatile variables, realtime
1878 clock, and platform reset). A UEFI stub is also provided to
1879 allow the kernel to be booted as an EFI application. This
1880 is only useful on systems that have UEFI firmware.
1883 bool "Enable support for SMBIOS (DMI) tables"
1887 This enables SMBIOS/DMI feature for systems.
1889 This option is only useful on systems that have UEFI firmware.
1890 However, even with this option, the resultant kernel should
1891 continue to boot on existing non-UEFI platforms.
1895 config SYSVIPC_COMPAT
1897 depends on COMPAT && SYSVIPC
1899 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1901 depends on HUGETLB_PAGE && MIGRATION
1903 config ARCH_ENABLE_THP_MIGRATION
1905 depends on TRANSPARENT_HUGEPAGE
1907 menu "Power management options"
1909 source "kernel/power/Kconfig"
1911 config ARCH_HIBERNATION_POSSIBLE
1915 config ARCH_HIBERNATION_HEADER
1917 depends on HIBERNATION
1919 config ARCH_SUSPEND_POSSIBLE
1924 menu "CPU Power Management"
1926 source "drivers/cpuidle/Kconfig"
1928 source "drivers/cpufreq/Kconfig"
1932 source "drivers/firmware/Kconfig"
1934 source "drivers/acpi/Kconfig"
1936 source "arch/arm64/kvm/Kconfig"
1939 source "arch/arm64/crypto/Kconfig"