3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_DEVMEM_IS_ALLOWED
7 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
8 select ARCH_HAS_ELF_RANDOMIZE
9 select ARCH_HAS_GCOV_PROFILE_ALL
10 select ARCH_HAS_SG_CHAIN
11 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
12 select ARCH_USE_CMPXCHG_LOCKREF
13 select ARCH_SUPPORTS_ATOMIC_RMW
14 select ARCH_WANT_OPTIONAL_GPIOLIB
15 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
16 select ARCH_WANT_FRAME_POINTERS
20 select AUDIT_ARCH_COMPAT_GENERIC
21 select ARM_GIC_V2M if PCI_MSI
23 select ARM_GIC_V3_ITS if PCI_MSI
25 select BUILDTIME_EXTABLE_SORT
26 select CLONE_BACKWARDS
28 select CPU_PM if (SUSPEND || CPU_IDLE)
29 select DCACHE_WORD_ACCESS
32 select GENERIC_ALLOCATOR
33 select GENERIC_CLOCKEVENTS
34 select GENERIC_CLOCKEVENTS_BROADCAST
35 select GENERIC_CPU_AUTOPROBE
36 select GENERIC_EARLY_IOREMAP
37 select GENERIC_IDLE_POLL_SETUP
38 select GENERIC_IRQ_PROBE
39 select GENERIC_IRQ_SHOW
40 select GENERIC_IRQ_SHOW_LEVEL
41 select GENERIC_PCI_IOMAP
42 select GENERIC_SCHED_CLOCK
43 select GENERIC_SMP_IDLE_THREAD
44 select GENERIC_STRNCPY_FROM_USER
45 select GENERIC_STRNLEN_USER
46 select GENERIC_TIME_VSYSCALL
47 select HANDLE_DOMAIN_IRQ
48 select HARDIRQS_SW_RESEND
49 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
50 select HAVE_ARCH_AUDITSYSCALL
51 select HAVE_ARCH_BITREVERSE
52 select HAVE_ARCH_JUMP_LABEL
53 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
55 select HAVE_ARCH_MMAP_RND_BITS
56 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
57 select HAVE_ARCH_SECCOMP_FILTER
58 select HAVE_ARCH_TRACEHOOK
60 select HAVE_C_RECORDMCOUNT
61 select HAVE_CC_STACKPROTECTOR
62 select HAVE_CMPXCHG_DOUBLE
63 select HAVE_CMPXCHG_LOCAL
64 select HAVE_DEBUG_BUGVERBOSE
65 select HAVE_DEBUG_KMEMLEAK
66 select HAVE_DMA_API_DEBUG
67 select HAVE_DMA_CONTIGUOUS
68 select HAVE_DYNAMIC_FTRACE
69 select HAVE_EFFICIENT_UNALIGNED_ACCESS
70 select HAVE_FTRACE_MCOUNT_RECORD
71 select HAVE_FUNCTION_TRACER
72 select HAVE_FUNCTION_GRAPH_TRACER
73 select HAVE_GENERIC_DMA_COHERENT
74 select HAVE_HW_BREAKPOINT if PERF_EVENTS
75 select HAVE_IRQ_TIME_ACCOUNTING
77 select HAVE_PATA_PLATFORM
78 select HAVE_PERF_EVENTS
80 select HAVE_PERF_USER_STACK_DUMP
81 select HAVE_RCU_TABLE_FREE
82 select HAVE_SYSCALL_TRACEPOINTS
83 select IOMMU_DMA if IOMMU_SUPPORT
85 select IRQ_FORCED_THREADING
86 select MODULES_USE_ELF_RELA
89 select OF_EARLY_FLATTREE
90 select OF_RESERVED_MEM
91 select PERF_USE_VMALLOC
96 select SYSCTL_EXCEPTION_TRACE
97 select HAVE_CONTEXT_TRACKING
100 ARM 64-bit (AArch64) Linux support.
105 config ARCH_PHYS_ADDR_T_64BIT
111 config ARCH_MMAP_RND_BITS_MIN
112 default 14 if ARM64_64K_PAGES
113 default 16 if ARM64_16K_PAGES
116 # max bits determined by the following formula:
117 # VA_BITS - PAGE_SHIFT - 3
118 config ARCH_MMAP_RND_BITS_MAX
119 default 19 if ARM64_VA_BITS=36
120 default 24 if ARM64_VA_BITS=39
121 default 27 if ARM64_VA_BITS=42
122 default 30 if ARM64_VA_BITS=47
123 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
124 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
125 default 33 if ARM64_VA_BITS=48
126 default 14 if ARM64_64K_PAGES
127 default 16 if ARM64_16K_PAGES
130 config ARCH_MMAP_RND_COMPAT_BITS_MIN
131 default 7 if ARM64_64K_PAGES
132 default 9 if ARM64_16K_PAGES
135 config ARCH_MMAP_RND_COMPAT_BITS_MAX
141 config STACKTRACE_SUPPORT
144 config ILLEGAL_POINTER_VALUE
146 default 0xdead000000000000
148 config LOCKDEP_SUPPORT
151 config TRACE_IRQFLAGS_SUPPORT
154 config RWSEM_XCHGADD_ALGORITHM
161 config GENERIC_BUG_RELATIVE_POINTERS
163 depends on GENERIC_BUG
165 config GENERIC_HWEIGHT
171 config GENERIC_CALIBRATE_DELAY
177 config HAVE_GENERIC_RCU_GUP
180 config ARCH_DMA_ADDR_T_64BIT
183 config NEED_DMA_MAP_STATE
186 config NEED_SG_DMA_LENGTH
198 config KERNEL_MODE_NEON
201 config FIX_EARLYCON_MEM
204 config PGTABLE_LEVELS
206 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
207 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
208 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
209 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
210 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
211 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
213 source "init/Kconfig"
215 source "kernel/Kconfig.freezer"
217 source "arch/arm64/Kconfig.platforms"
224 This feature enables support for PCI bus system. If you say Y
225 here, the kernel will include drivers and infrastructure code
226 to support PCI bus devices.
231 config PCI_DOMAINS_GENERIC
237 source "drivers/pci/Kconfig"
238 source "drivers/pci/hotplug/Kconfig"
242 menu "Kernel Features"
244 menu "ARM errata workarounds via the alternatives framework"
246 config ARM64_ERRATUM_826319
247 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
250 This option adds an alternative code sequence to work around ARM
251 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
252 AXI master interface and an L2 cache.
254 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
255 and is unable to accept a certain write via this interface, it will
256 not progress on read data presented on the read data channel and the
259 The workaround promotes data cache clean instructions to
260 data cache clean-and-invalidate.
261 Please note that this does not necessarily enable the workaround,
262 as it depends on the alternative framework, which will only patch
263 the kernel if an affected CPU is detected.
267 config ARM64_ERRATUM_827319
268 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
271 This option adds an alternative code sequence to work around ARM
272 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
273 master interface and an L2 cache.
275 Under certain conditions this erratum can cause a clean line eviction
276 to occur at the same time as another transaction to the same address
277 on the AMBA 5 CHI interface, which can cause data corruption if the
278 interconnect reorders the two transactions.
280 The workaround promotes data cache clean instructions to
281 data cache clean-and-invalidate.
282 Please note that this does not necessarily enable the workaround,
283 as it depends on the alternative framework, which will only patch
284 the kernel if an affected CPU is detected.
288 config ARM64_ERRATUM_824069
289 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
292 This option adds an alternative code sequence to work around ARM
293 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
294 to a coherent interconnect.
296 If a Cortex-A53 processor is executing a store or prefetch for
297 write instruction at the same time as a processor in another
298 cluster is executing a cache maintenance operation to the same
299 address, then this erratum might cause a clean cache line to be
300 incorrectly marked as dirty.
302 The workaround promotes data cache clean instructions to
303 data cache clean-and-invalidate.
304 Please note that this option does not necessarily enable the
305 workaround, as it depends on the alternative framework, which will
306 only patch the kernel if an affected CPU is detected.
310 config ARM64_ERRATUM_819472
311 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
314 This option adds an alternative code sequence to work around ARM
315 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
316 present when it is connected to a coherent interconnect.
318 If the processor is executing a load and store exclusive sequence at
319 the same time as a processor in another cluster is executing a cache
320 maintenance operation to the same address, then this erratum might
321 cause data corruption.
323 The workaround promotes data cache clean instructions to
324 data cache clean-and-invalidate.
325 Please note that this does not necessarily enable the workaround,
326 as it depends on the alternative framework, which will only patch
327 the kernel if an affected CPU is detected.
331 config ARM64_ERRATUM_832075
332 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
335 This option adds an alternative code sequence to work around ARM
336 erratum 832075 on Cortex-A57 parts up to r1p2.
338 Affected Cortex-A57 parts might deadlock when exclusive load/store
339 instructions to Write-Back memory are mixed with Device loads.
341 The workaround is to promote device loads to use Load-Acquire
343 Please note that this does not necessarily enable the workaround,
344 as it depends on the alternative framework, which will only patch
345 the kernel if an affected CPU is detected.
349 config ARM64_ERRATUM_834220
350 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
354 This option adds an alternative code sequence to work around ARM
355 erratum 834220 on Cortex-A57 parts up to r1p2.
357 Affected Cortex-A57 parts might report a Stage 2 translation
358 fault as the result of a Stage 1 fault for load crossing a
359 page boundary when there is a permission or device memory
360 alignment fault at Stage 1 and a translation fault at Stage 2.
362 The workaround is to verify that the Stage 1 translation
363 doesn't generate a fault before handling the Stage 2 fault.
364 Please note that this does not necessarily enable the workaround,
365 as it depends on the alternative framework, which will only patch
366 the kernel if an affected CPU is detected.
370 config ARM64_ERRATUM_845719
371 bool "Cortex-A53: 845719: a load might read incorrect data"
375 This option adds an alternative code sequence to work around ARM
376 erratum 845719 on Cortex-A53 parts up to r0p4.
378 When running a compat (AArch32) userspace on an affected Cortex-A53
379 part, a load at EL0 from a virtual address that matches the bottom 32
380 bits of the virtual address used by a recent load at (AArch64) EL1
381 might return incorrect data.
383 The workaround is to write the contextidr_el1 register on exception
384 return to a 32-bit task.
385 Please note that this does not necessarily enable the workaround,
386 as it depends on the alternative framework, which will only patch
387 the kernel if an affected CPU is detected.
391 config ARM64_ERRATUM_843419
392 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
396 This option builds kernel modules using the large memory model in
397 order to avoid the use of the ADRP instruction, which can cause
398 a subsequent memory access to use an incorrect address on Cortex-A53
401 Note that the kernel itself must be linked with a version of ld
402 which fixes potentially affected ADRP instructions through the
407 config CAVIUM_ERRATUM_22375
408 bool "Cavium erratum 22375, 24313"
411 Enable workaround for erratum 22375, 24313.
413 This implements two gicv3-its errata workarounds for ThunderX. Both
414 with small impact affecting only ITS table allocation.
416 erratum 22375: only alloc 8MB table size
417 erratum 24313: ignore memory access type
419 The fixes are in ITS initialization and basically ignore memory access
420 type and table size provided by the TYPER and BASER registers.
424 config CAVIUM_ERRATUM_23154
425 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
428 The gicv3 of ThunderX requires a modified version for
429 reading the IAR status to ensure data synchronization
430 (access to icc_iar1_el1 is not sync'ed before and after).
439 default ARM64_4K_PAGES
441 Page size (translation granule) configuration.
443 config ARM64_4K_PAGES
446 This feature enables 4KB pages support.
448 config ARM64_16K_PAGES
451 The system will use 16KB pages support. AArch32 emulation
452 requires applications compiled with 16K (or a multiple of 16K)
455 config ARM64_64K_PAGES
458 This feature enables 64KB pages support (4KB by default)
459 allowing only two levels of page tables and faster TLB
460 look-up. AArch32 emulation requires applications compiled
461 with 64K aligned segments.
466 prompt "Virtual address space size"
467 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
468 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
469 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
471 Allows choosing one of multiple possible virtual address
472 space sizes. The level of translation table is determined by
473 a combination of page size and virtual address space size.
475 config ARM64_VA_BITS_36
476 bool "36-bit" if EXPERT
477 depends on ARM64_16K_PAGES
479 config ARM64_VA_BITS_39
481 depends on ARM64_4K_PAGES
483 config ARM64_VA_BITS_42
485 depends on ARM64_64K_PAGES
487 config ARM64_VA_BITS_47
489 depends on ARM64_16K_PAGES
491 config ARM64_VA_BITS_48
498 default 36 if ARM64_VA_BITS_36
499 default 39 if ARM64_VA_BITS_39
500 default 42 if ARM64_VA_BITS_42
501 default 47 if ARM64_VA_BITS_47
502 default 48 if ARM64_VA_BITS_48
504 config CPU_BIG_ENDIAN
505 bool "Build big-endian kernel"
507 Say Y if you plan on running a kernel in big-endian mode.
510 bool "Multi-core scheduler support"
512 Multi-core scheduler support improves the CPU scheduler's decision
513 making when dealing with multi-core CPU chips at a cost of slightly
514 increased overhead in some places. If unsure say N here.
517 bool "SMT scheduler support"
519 Improves the CPU scheduler's decision making when dealing with
520 MultiThreading at a cost of slightly increased overhead in some
521 places. If unsure say N here.
524 int "Maximum number of CPUs (2-4096)"
526 # These have to remain sorted largest to smallest
530 bool "Support for hot-pluggable CPUs"
531 select GENERIC_IRQ_MIGRATION
533 Say Y here to experiment with turning CPUs off and on. CPUs
534 can be controlled through /sys/devices/system/cpu.
536 source kernel/Kconfig.preempt
537 source kernel/Kconfig.hz
539 config ARCH_HAS_HOLES_MEMORYMODEL
540 def_bool y if SPARSEMEM
542 config ARCH_SPARSEMEM_ENABLE
544 select SPARSEMEM_VMEMMAP_ENABLE
546 config ARCH_SPARSEMEM_DEFAULT
547 def_bool ARCH_SPARSEMEM_ENABLE
549 config ARCH_SELECT_MEMORY_MODEL
550 def_bool ARCH_SPARSEMEM_ENABLE
552 config HAVE_ARCH_PFN_VALID
553 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
555 config HW_PERF_EVENTS
559 config SYS_SUPPORTS_HUGETLBFS
562 config ARCH_WANT_HUGE_PMD_SHARE
563 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
565 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
568 config ARCH_HAS_CACHE_LINE_SIZE
574 bool "Enable seccomp to safely compute untrusted bytecode"
576 This kernel feature is useful for number crunching applications
577 that may need to compute untrusted bytecode during their
578 execution. By using pipes or other transports made available to
579 the process as file descriptors supporting the read/write
580 syscalls, it's possible to isolate those applications in
581 their own address space using seccomp. Once seccomp is
582 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
583 and the task is only allowed to execute a few safe syscalls
584 defined by each seccomp mode.
587 bool "Enable paravirtualization code"
589 This changes the kernel so it can modify itself when it is run
590 under a hypervisor, potentially improving performance significantly
591 over full virtualization.
593 config PARAVIRT_TIME_ACCOUNTING
594 bool "Paravirtual steal time accounting"
598 Select this option to enable fine granularity task steal time
599 accounting. Time spent executing other tasks in parallel with
600 the current vCPU is discounted from the vCPU power. To account for
601 that, there can be a small performance impact.
603 If in doubt, say N here.
610 bool "Xen guest support on ARM64"
611 depends on ARM64 && OF
615 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
617 config FORCE_MAX_ZONEORDER
619 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
620 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
623 The kernel memory allocator divides physically contiguous memory
624 blocks into "zones", where each zone is a power of two number of
625 pages. This option selects the largest power of two that the kernel
626 keeps in the memory allocator. If you need to allocate very large
627 blocks of physically contiguous memory, then you may need to
630 This config option is actually maximum order plus one. For example,
631 a value of 11 means that the largest free memory block is 2^10 pages.
633 We make sure that we can allocate upto a HugePage size for each configuration.
635 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
637 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
638 4M allocations matching the default size used by generic code.
640 menuconfig ARMV8_DEPRECATED
641 bool "Emulate deprecated/obsolete ARMv8 instructions"
644 Legacy software support may require certain instructions
645 that have been deprecated or obsoleted in the architecture.
647 Enable this config to enable selective emulation of these
655 bool "Emulate SWP/SWPB instructions"
657 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
658 they are always undefined. Say Y here to enable software
659 emulation of these instructions for userspace using LDXR/STXR.
661 In some older versions of glibc [<=2.8] SWP is used during futex
662 trylock() operations with the assumption that the code will not
663 be preempted. This invalid assumption may be more likely to fail
664 with SWP emulation enabled, leading to deadlock of the user
667 NOTE: when accessing uncached shared regions, LDXR/STXR rely
668 on an external transaction monitoring block called a global
669 monitor to maintain update atomicity. If your system does not
670 implement a global monitor, this option can cause programs that
671 perform SWP operations to uncached memory to deadlock.
675 config CP15_BARRIER_EMULATION
676 bool "Emulate CP15 Barrier instructions"
678 The CP15 barrier instructions - CP15ISB, CP15DSB, and
679 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
680 strongly recommended to use the ISB, DSB, and DMB
681 instructions instead.
683 Say Y here to enable software emulation of these
684 instructions for AArch32 userspace code. When this option is
685 enabled, CP15 barrier usage is traced which can help
686 identify software that needs updating.
690 config SETEND_EMULATION
691 bool "Emulate SETEND instruction"
693 The SETEND instruction alters the data-endianness of the
694 AArch32 EL0, and is deprecated in ARMv8.
696 Say Y here to enable software emulation of the instruction
697 for AArch32 userspace code.
699 Note: All the cpus on the system must have mixed endian support at EL0
700 for this feature to be enabled. If a new CPU - which doesn't support mixed
701 endian - is hotplugged in after this feature has been enabled, there could
702 be unexpected results in the applications.
707 menu "ARMv8.1 architectural features"
709 config ARM64_HW_AFDBM
710 bool "Support for hardware updates of the Access and Dirty page flags"
713 The ARMv8.1 architecture extensions introduce support for
714 hardware updates of the access and dirty information in page
715 table entries. When enabled in TCR_EL1 (HA and HD bits) on
716 capable processors, accesses to pages with PTE_AF cleared will
717 set this bit instead of raising an access flag fault.
718 Similarly, writes to read-only pages with the DBM bit set will
719 clear the read-only bit (AP[2]) instead of raising a
722 Kernels built with this configuration option enabled continue
723 to work on pre-ARMv8.1 hardware and the performance impact is
724 minimal. If unsure, say Y.
727 bool "Enable support for Privileged Access Never (PAN)"
730 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
731 prevents the kernel or hypervisor from accessing user-space (EL0)
734 Choosing this option will cause any unprotected (not using
735 copy_to_user et al) memory access to fail with a permission fault.
737 The feature is detected at runtime, and will remain as a 'nop'
738 instruction if the cpu does not implement the feature.
740 config ARM64_LSE_ATOMICS
741 bool "Atomic instructions"
743 As part of the Large System Extensions, ARMv8.1 introduces new
744 atomic instructions that are designed specifically to scale in
747 Say Y here to make use of these instructions for the in-kernel
748 atomic routines. This incurs a small overhead on CPUs that do
749 not support these instructions and requires the kernel to be
750 built with binutils >= 2.25.
759 string "Default kernel command string"
762 Provide a set of default command-line options at build time by
763 entering them here. As a minimum, you should specify the the
764 root device (e.g. root=/dev/nfs).
767 bool "Always use the default kernel command string"
769 Always use the default kernel command string, even if the boot
770 loader passes other arguments to the kernel.
771 This is useful if you cannot or don't want to change the
772 command-line options your boot loader passes to the kernel.
778 bool "UEFI runtime support"
779 depends on OF && !CPU_BIG_ENDIAN
782 select EFI_PARAMS_FROM_FDT
783 select EFI_RUNTIME_WRAPPERS
788 This option provides support for runtime services provided
789 by UEFI firmware (such as non-volatile variables, realtime
790 clock, and platform reset). A UEFI stub is also provided to
791 allow the kernel to be booted as an EFI application. This
792 is only useful on systems that have UEFI firmware.
795 bool "Enable support for SMBIOS (DMI) tables"
799 This enables SMBIOS/DMI feature for systems.
801 This option is only useful on systems that have UEFI firmware.
802 However, even with this option, the resultant kernel should
803 continue to boot on existing non-UEFI platforms.
807 menu "Userspace binary formats"
809 source "fs/Kconfig.binfmt"
812 bool "Kernel support for 32-bit EL0"
813 depends on ARM64_4K_PAGES || EXPERT
814 select COMPAT_BINFMT_ELF
816 select OLD_SIGSUSPEND3
817 select COMPAT_OLD_SIGACTION
819 This option enables support for a 32-bit EL0 running under a 64-bit
820 kernel at EL1. AArch32-specific components such as system calls,
821 the user helper functions, VFP support and the ptrace interface are
822 handled appropriately by the kernel.
824 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
825 that you will only be able to execute AArch32 binaries that were compiled
826 with page size aligned segments.
828 If you want to execute 32-bit userspace applications, say Y.
830 config SYSVIPC_COMPAT
832 depends on COMPAT && SYSVIPC
836 menu "Power management options"
838 source "kernel/power/Kconfig"
840 config ARCH_SUSPEND_POSSIBLE
845 menu "CPU Power Management"
847 source "drivers/cpuidle/Kconfig"
849 source "drivers/cpufreq/Kconfig"
855 source "drivers/Kconfig"
857 source "drivers/firmware/Kconfig"
859 source "drivers/acpi/Kconfig"
863 source "arch/arm64/kvm/Kconfig"
865 source "arch/arm64/Kconfig.debug"
867 source "security/Kconfig"
869 source "crypto/Kconfig"
871 source "arch/arm64/crypto/Kconfig"