1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_WX
13 select ARCH_BINFMT_ELF_STATE
14 select ARCH_HAS_CACHE_LINE_SIZE
15 select ARCH_HAS_DEBUG_VIRTUAL
16 select ARCH_HAS_DEBUG_VM_PGTABLE
17 select ARCH_HAS_DMA_PREP_COHERENT
18 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
19 select ARCH_HAS_FAST_MULTIPLIER
20 select ARCH_HAS_FORTIFY_SOURCE
21 select ARCH_HAS_GCOV_PROFILE_ALL
22 select ARCH_HAS_GIGANTIC_PAGE
24 select ARCH_HAS_KEEPINITRD
25 select ARCH_HAS_MEMBARRIER_SYNC_CORE
26 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
27 select ARCH_HAS_PTE_DEVMAP
28 select ARCH_HAS_PTE_SPECIAL
29 select ARCH_HAS_SETUP_DMA_OPS
30 select ARCH_HAS_SET_DIRECT_MAP
31 select ARCH_HAS_SET_MEMORY
33 select ARCH_HAS_STRICT_KERNEL_RWX
34 select ARCH_HAS_STRICT_MODULE_RWX
35 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
36 select ARCH_HAS_SYNC_DMA_FOR_CPU
37 select ARCH_HAS_SYSCALL_WRAPPER
38 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
39 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
40 select ARCH_HAVE_ELF_PROT
41 select ARCH_HAVE_NMI_SAFE_CMPXCHG
42 select ARCH_INLINE_READ_LOCK if !PREEMPTION
43 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
44 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
45 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
46 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
47 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
48 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
49 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
50 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
51 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
52 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
53 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
54 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
55 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
56 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
57 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
58 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
59 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
60 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
61 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
62 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
63 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
64 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
65 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
66 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
67 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
68 select ARCH_KEEP_MEMBLOCK
69 select ARCH_USE_CMPXCHG_LOCKREF
70 select ARCH_USE_GNU_PROPERTY
71 select ARCH_USE_MEMTEST
72 select ARCH_USE_QUEUED_RWLOCKS
73 select ARCH_USE_QUEUED_SPINLOCKS
74 select ARCH_USE_SYM_ANNOTATIONS
75 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
76 select ARCH_SUPPORTS_HUGETLBFS
77 select ARCH_SUPPORTS_MEMORY_FAILURE
78 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
79 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
80 select ARCH_SUPPORTS_LTO_CLANG_THIN
81 select ARCH_SUPPORTS_CFI_CLANG
82 select ARCH_SUPPORTS_ATOMIC_RMW
83 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG)
84 select ARCH_SUPPORTS_NUMA_BALANCING
85 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
86 select ARCH_WANT_DEFAULT_BPF_JIT
87 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
88 select ARCH_WANT_FRAME_POINTERS
89 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
90 select ARCH_WANT_LD_ORPHAN_WARN
91 select ARCH_HAS_UBSAN_SANITIZE_ALL
95 select AUDIT_ARCH_COMPAT_GENERIC
96 select ARM_GIC_V2M if PCI
98 select ARM_GIC_V3_ITS if PCI
100 select BUILDTIME_TABLE_SORT
101 select CLONE_BACKWARDS
103 select CPU_PM if (SUSPEND || CPU_IDLE)
105 select DCACHE_WORD_ACCESS
106 select DMA_DIRECT_REMAP
109 select GENERIC_ALLOCATOR
110 select GENERIC_ARCH_TOPOLOGY
111 select GENERIC_CLOCKEVENTS_BROADCAST
112 select GENERIC_CPU_AUTOPROBE
113 select GENERIC_CPU_VULNERABILITIES
114 select GENERIC_EARLY_IOREMAP
115 select GENERIC_FIND_FIRST_BIT
116 select GENERIC_IDLE_POLL_SETUP
117 select GENERIC_IRQ_IPI
118 select GENERIC_IRQ_PROBE
119 select GENERIC_IRQ_SHOW
120 select GENERIC_IRQ_SHOW_LEVEL
121 select GENERIC_LIB_DEVMEM_IS_ALLOWED
122 select GENERIC_PCI_IOMAP
123 select GENERIC_PTDUMP
124 select GENERIC_SCHED_CLOCK
125 select GENERIC_SMP_IDLE_THREAD
126 select GENERIC_STRNCPY_FROM_USER
127 select GENERIC_STRNLEN_USER
128 select GENERIC_TIME_VSYSCALL
129 select GENERIC_GETTIMEOFDAY
130 select GENERIC_VDSO_TIME_NS
131 select HANDLE_DOMAIN_IRQ
132 select HARDIRQS_SW_RESEND
136 select HAVE_ACPI_APEI if (ACPI && EFI)
137 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
138 select HAVE_ARCH_AUDITSYSCALL
139 select HAVE_ARCH_BITREVERSE
140 select HAVE_ARCH_COMPILER_H
141 select HAVE_ARCH_HUGE_VMAP
142 select HAVE_ARCH_JUMP_LABEL
143 select HAVE_ARCH_JUMP_LABEL_RELATIVE
144 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
145 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
146 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
147 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
148 select HAVE_ARCH_KFENCE
149 select HAVE_ARCH_KGDB
150 select HAVE_ARCH_MMAP_RND_BITS
151 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
152 select HAVE_ARCH_PFN_VALID
153 select HAVE_ARCH_PREL32_RELOCATIONS
154 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
155 select HAVE_ARCH_SECCOMP_FILTER
156 select HAVE_ARCH_STACKLEAK
157 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
158 select HAVE_ARCH_TRACEHOOK
159 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
160 select HAVE_ARCH_VMAP_STACK
161 select HAVE_ARM_SMCCC
162 select HAVE_ASM_MODVERSIONS
164 select HAVE_C_RECORDMCOUNT
165 select HAVE_CMPXCHG_DOUBLE
166 select HAVE_CMPXCHG_LOCAL
167 select HAVE_CONTEXT_TRACKING
168 select HAVE_DEBUG_BUGVERBOSE
169 select HAVE_DEBUG_KMEMLEAK
170 select HAVE_DMA_CONTIGUOUS
171 select HAVE_DYNAMIC_FTRACE
172 select HAVE_DYNAMIC_FTRACE_WITH_REGS \
173 if $(cc-option,-fpatchable-function-entry=2)
174 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
175 if DYNAMIC_FTRACE_WITH_REGS
176 select HAVE_EFFICIENT_UNALIGNED_ACCESS
178 select HAVE_FTRACE_MCOUNT_RECORD
179 select HAVE_FUNCTION_TRACER
180 select HAVE_FUNCTION_ERROR_INJECTION
181 select HAVE_FUNCTION_GRAPH_TRACER
182 select HAVE_GCC_PLUGINS
183 select HAVE_HW_BREAKPOINT if PERF_EVENTS
184 select HAVE_IRQ_TIME_ACCOUNTING
186 select HAVE_PATA_PLATFORM
187 select HAVE_PERF_EVENTS
188 select HAVE_PERF_REGS
189 select HAVE_PERF_USER_STACK_DUMP
190 select HAVE_REGS_AND_STACK_ACCESS_API
191 select HAVE_FUNCTION_ARG_ACCESS_API
192 select HAVE_FUTEX_CMPXCHG if FUTEX
193 select MMU_GATHER_RCU_TABLE_FREE
195 select HAVE_STACKPROTECTOR
196 select HAVE_SYSCALL_TRACEPOINTS
198 select HAVE_KRETPROBES
199 select HAVE_GENERIC_VDSO
200 select IOMMU_DMA if IOMMU_SUPPORT
202 select IRQ_FORCED_THREADING
203 select KASAN_VMALLOC if KASAN_GENERIC
204 select MODULES_USE_ELF_RELA
205 select NEED_DMA_MAP_STATE
206 select NEED_SG_DMA_LENGTH
208 select OF_EARLY_FLATTREE
209 select PCI_DOMAINS_GENERIC if PCI
210 select PCI_ECAM if (ACPI && PCI)
211 select PCI_SYSCALL if PCI
216 select SYSCTL_EXCEPTION_TRACE
217 select THREAD_INFO_IN_TASK
218 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
220 ARM 64-bit (AArch64) Linux support.
228 config ARM64_PAGE_SHIFT
230 default 16 if ARM64_64K_PAGES
231 default 14 if ARM64_16K_PAGES
234 config ARM64_CONT_PTE_SHIFT
236 default 5 if ARM64_64K_PAGES
237 default 7 if ARM64_16K_PAGES
240 config ARM64_CONT_PMD_SHIFT
242 default 5 if ARM64_64K_PAGES
243 default 5 if ARM64_16K_PAGES
246 config ARCH_MMAP_RND_BITS_MIN
247 default 14 if ARM64_64K_PAGES
248 default 16 if ARM64_16K_PAGES
251 # max bits determined by the following formula:
252 # VA_BITS - PAGE_SHIFT - 3
253 config ARCH_MMAP_RND_BITS_MAX
254 default 19 if ARM64_VA_BITS=36
255 default 24 if ARM64_VA_BITS=39
256 default 27 if ARM64_VA_BITS=42
257 default 30 if ARM64_VA_BITS=47
258 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
259 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
260 default 33 if ARM64_VA_BITS=48
261 default 14 if ARM64_64K_PAGES
262 default 16 if ARM64_16K_PAGES
265 config ARCH_MMAP_RND_COMPAT_BITS_MIN
266 default 7 if ARM64_64K_PAGES
267 default 9 if ARM64_16K_PAGES
270 config ARCH_MMAP_RND_COMPAT_BITS_MAX
276 config STACKTRACE_SUPPORT
279 config ILLEGAL_POINTER_VALUE
281 default 0xdead000000000000
283 config LOCKDEP_SUPPORT
286 config TRACE_IRQFLAGS_SUPPORT
293 config GENERIC_BUG_RELATIVE_POINTERS
295 depends on GENERIC_BUG
297 config GENERIC_HWEIGHT
303 config GENERIC_CALIBRATE_DELAY
307 bool "Support DMA zone" if EXPERT
311 bool "Support DMA32 zone" if EXPERT
314 config ARCH_ENABLE_MEMORY_HOTPLUG
317 config ARCH_ENABLE_MEMORY_HOTREMOVE
323 config KERNEL_MODE_NEON
326 config FIX_EARLYCON_MEM
329 config PGTABLE_LEVELS
331 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
332 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
333 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
334 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
335 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
336 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
338 config ARCH_SUPPORTS_UPROBES
341 config ARCH_PROC_KCORE_TEXT
344 config BROKEN_GAS_INST
345 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
347 config KASAN_SHADOW_OFFSET
349 depends on KASAN_GENERIC || KASAN_SW_TAGS
350 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
351 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
352 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
353 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
354 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
355 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
356 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
357 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
358 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
359 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
360 default 0xffffffffffffffff
362 source "arch/arm64/Kconfig.platforms"
364 menu "Kernel Features"
366 menu "ARM errata workarounds via the alternatives framework"
368 config ARM64_WORKAROUND_CLEAN_CACHE
371 config ARM64_ERRATUM_826319
372 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
374 select ARM64_WORKAROUND_CLEAN_CACHE
376 This option adds an alternative code sequence to work around ARM
377 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
378 AXI master interface and an L2 cache.
380 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
381 and is unable to accept a certain write via this interface, it will
382 not progress on read data presented on the read data channel and the
385 The workaround promotes data cache clean instructions to
386 data cache clean-and-invalidate.
387 Please note that this does not necessarily enable the workaround,
388 as it depends on the alternative framework, which will only patch
389 the kernel if an affected CPU is detected.
393 config ARM64_ERRATUM_827319
394 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
396 select ARM64_WORKAROUND_CLEAN_CACHE
398 This option adds an alternative code sequence to work around ARM
399 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
400 master interface and an L2 cache.
402 Under certain conditions this erratum can cause a clean line eviction
403 to occur at the same time as another transaction to the same address
404 on the AMBA 5 CHI interface, which can cause data corruption if the
405 interconnect reorders the two transactions.
407 The workaround promotes data cache clean instructions to
408 data cache clean-and-invalidate.
409 Please note that this does not necessarily enable the workaround,
410 as it depends on the alternative framework, which will only patch
411 the kernel if an affected CPU is detected.
415 config ARM64_ERRATUM_824069
416 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
418 select ARM64_WORKAROUND_CLEAN_CACHE
420 This option adds an alternative code sequence to work around ARM
421 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
422 to a coherent interconnect.
424 If a Cortex-A53 processor is executing a store or prefetch for
425 write instruction at the same time as a processor in another
426 cluster is executing a cache maintenance operation to the same
427 address, then this erratum might cause a clean cache line to be
428 incorrectly marked as dirty.
430 The workaround promotes data cache clean instructions to
431 data cache clean-and-invalidate.
432 Please note that this option does not necessarily enable the
433 workaround, as it depends on the alternative framework, which will
434 only patch the kernel if an affected CPU is detected.
438 config ARM64_ERRATUM_819472
439 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
441 select ARM64_WORKAROUND_CLEAN_CACHE
443 This option adds an alternative code sequence to work around ARM
444 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
445 present when it is connected to a coherent interconnect.
447 If the processor is executing a load and store exclusive sequence at
448 the same time as a processor in another cluster is executing a cache
449 maintenance operation to the same address, then this erratum might
450 cause data corruption.
452 The workaround promotes data cache clean instructions to
453 data cache clean-and-invalidate.
454 Please note that this does not necessarily enable the workaround,
455 as it depends on the alternative framework, which will only patch
456 the kernel if an affected CPU is detected.
460 config ARM64_ERRATUM_832075
461 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
464 This option adds an alternative code sequence to work around ARM
465 erratum 832075 on Cortex-A57 parts up to r1p2.
467 Affected Cortex-A57 parts might deadlock when exclusive load/store
468 instructions to Write-Back memory are mixed with Device loads.
470 The workaround is to promote device loads to use Load-Acquire
472 Please note that this does not necessarily enable the workaround,
473 as it depends on the alternative framework, which will only patch
474 the kernel if an affected CPU is detected.
478 config ARM64_ERRATUM_834220
479 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
483 This option adds an alternative code sequence to work around ARM
484 erratum 834220 on Cortex-A57 parts up to r1p2.
486 Affected Cortex-A57 parts might report a Stage 2 translation
487 fault as the result of a Stage 1 fault for load crossing a
488 page boundary when there is a permission or device memory
489 alignment fault at Stage 1 and a translation fault at Stage 2.
491 The workaround is to verify that the Stage 1 translation
492 doesn't generate a fault before handling the Stage 2 fault.
493 Please note that this does not necessarily enable the workaround,
494 as it depends on the alternative framework, which will only patch
495 the kernel if an affected CPU is detected.
499 config ARM64_ERRATUM_845719
500 bool "Cortex-A53: 845719: a load might read incorrect data"
504 This option adds an alternative code sequence to work around ARM
505 erratum 845719 on Cortex-A53 parts up to r0p4.
507 When running a compat (AArch32) userspace on an affected Cortex-A53
508 part, a load at EL0 from a virtual address that matches the bottom 32
509 bits of the virtual address used by a recent load at (AArch64) EL1
510 might return incorrect data.
512 The workaround is to write the contextidr_el1 register on exception
513 return to a 32-bit task.
514 Please note that this does not necessarily enable the workaround,
515 as it depends on the alternative framework, which will only patch
516 the kernel if an affected CPU is detected.
520 config ARM64_ERRATUM_843419
521 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
523 select ARM64_MODULE_PLTS if MODULES
525 This option links the kernel with '--fix-cortex-a53-843419' and
526 enables PLT support to replace certain ADRP instructions, which can
527 cause subsequent memory accesses to use an incorrect address on
528 Cortex-A53 parts up to r0p4.
532 config ARM64_LD_HAS_FIX_ERRATUM_843419
533 def_bool $(ld-option,--fix-cortex-a53-843419)
535 config ARM64_ERRATUM_1024718
536 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
539 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
541 Affected Cortex-A55 cores (all revisions) could cause incorrect
542 update of the hardware dirty bit when the DBM/AP bits are updated
543 without a break-before-make. The workaround is to disable the usage
544 of hardware DBM locally on the affected cores. CPUs not affected by
545 this erratum will continue to use the feature.
549 config ARM64_ERRATUM_1418040
550 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
554 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
555 errata 1188873 and 1418040.
557 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
558 cause register corruption when accessing the timer registers
559 from AArch32 userspace.
563 config ARM64_WORKAROUND_SPECULATIVE_AT
566 config ARM64_ERRATUM_1165522
567 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
569 select ARM64_WORKAROUND_SPECULATIVE_AT
571 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
573 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
574 corrupted TLBs by speculating an AT instruction during a guest
579 config ARM64_ERRATUM_1319367
580 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
582 select ARM64_WORKAROUND_SPECULATIVE_AT
584 This option adds work arounds for ARM Cortex-A57 erratum 1319537
585 and A72 erratum 1319367
587 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
588 speculating an AT instruction during a guest context switch.
592 config ARM64_ERRATUM_1530923
593 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
595 select ARM64_WORKAROUND_SPECULATIVE_AT
597 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
599 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
600 corrupted TLBs by speculating an AT instruction during a guest
605 config ARM64_WORKAROUND_REPEAT_TLBI
608 config ARM64_ERRATUM_1286807
609 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
611 select ARM64_WORKAROUND_REPEAT_TLBI
613 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
615 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
616 address for a cacheable mapping of a location is being
617 accessed by a core while another core is remapping the virtual
618 address to a new physical page using the recommended
619 break-before-make sequence, then under very rare circumstances
620 TLBI+DSB completes before a read using the translation being
621 invalidated has been observed by other observers. The
622 workaround repeats the TLBI+DSB operation.
624 config ARM64_ERRATUM_1463225
625 bool "Cortex-A76: Software Step might prevent interrupt recognition"
628 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
630 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
631 of a system call instruction (SVC) can prevent recognition of
632 subsequent interrupts when software stepping is disabled in the
633 exception handler of the system call and either kernel debugging
634 is enabled or VHE is in use.
636 Work around the erratum by triggering a dummy step exception
637 when handling a system call from a task that is being stepped
638 in a VHE configuration of the kernel.
642 config ARM64_ERRATUM_1542419
643 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
646 This option adds a workaround for ARM Neoverse-N1 erratum
649 Affected Neoverse-N1 cores could execute a stale instruction when
650 modified by another CPU. The workaround depends on a firmware
653 Workaround the issue by hiding the DIC feature from EL0. This
654 forces user-space to perform cache maintenance.
658 config ARM64_ERRATUM_1508412
659 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
662 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
664 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
665 of a store-exclusive or read of PAR_EL1 and a load with device or
666 non-cacheable memory attributes. The workaround depends on a firmware
669 KVM guests must also have the workaround implemented or they can
672 Work around the issue by inserting DMB SY barriers around PAR_EL1
673 register reads and warning KVM users. The DMB barrier is sufficient
674 to prevent a speculative PAR_EL1 read.
678 config CAVIUM_ERRATUM_22375
679 bool "Cavium erratum 22375, 24313"
682 Enable workaround for errata 22375 and 24313.
684 This implements two gicv3-its errata workarounds for ThunderX. Both
685 with a small impact affecting only ITS table allocation.
687 erratum 22375: only alloc 8MB table size
688 erratum 24313: ignore memory access type
690 The fixes are in ITS initialization and basically ignore memory access
691 type and table size provided by the TYPER and BASER registers.
695 config CAVIUM_ERRATUM_23144
696 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
700 ITS SYNC command hang for cross node io and collections/cpu mapping.
704 config CAVIUM_ERRATUM_23154
705 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
708 The gicv3 of ThunderX requires a modified version for
709 reading the IAR status to ensure data synchronization
710 (access to icc_iar1_el1 is not sync'ed before and after).
714 config CAVIUM_ERRATUM_27456
715 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
718 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
719 instructions may cause the icache to become corrupted if it
720 contains data for a non-current ASID. The fix is to
721 invalidate the icache when changing the mm context.
725 config CAVIUM_ERRATUM_30115
726 bool "Cavium erratum 30115: Guest may disable interrupts in host"
729 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
730 1.2, and T83 Pass 1.0, KVM guest execution may disable
731 interrupts in host. Trapping both GICv3 group-0 and group-1
732 accesses sidesteps the issue.
736 config CAVIUM_TX2_ERRATUM_219
737 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
740 On Cavium ThunderX2, a load, store or prefetch instruction between a
741 TTBR update and the corresponding context synchronizing operation can
742 cause a spurious Data Abort to be delivered to any hardware thread in
745 Work around the issue by avoiding the problematic code sequence and
746 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
747 trap handler performs the corresponding register access, skips the
748 instruction and ensures context synchronization by virtue of the
753 config FUJITSU_ERRATUM_010001
754 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
757 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
758 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
759 accesses may cause undefined fault (Data abort, DFSC=0b111111).
760 This fault occurs under a specific hardware condition when a
761 load/store instruction performs an address translation using:
762 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
763 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
764 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
765 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
767 The workaround is to ensure these bits are clear in TCR_ELx.
768 The workaround only affects the Fujitsu-A64FX.
772 config HISILICON_ERRATUM_161600802
773 bool "Hip07 161600802: Erroneous redistributor VLPI base"
776 The HiSilicon Hip07 SoC uses the wrong redistributor base
777 when issued ITS commands such as VMOVP and VMAPP, and requires
778 a 128kB offset to be applied to the target address in this commands.
782 config QCOM_FALKOR_ERRATUM_1003
783 bool "Falkor E1003: Incorrect translation due to ASID change"
786 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
787 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
788 in TTBR1_EL1, this situation only occurs in the entry trampoline and
789 then only for entries in the walk cache, since the leaf translation
790 is unchanged. Work around the erratum by invalidating the walk cache
791 entries for the trampoline before entering the kernel proper.
793 config QCOM_FALKOR_ERRATUM_1009
794 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
796 select ARM64_WORKAROUND_REPEAT_TLBI
798 On Falkor v1, the CPU may prematurely complete a DSB following a
799 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
800 one more time to fix the issue.
804 config QCOM_QDF2400_ERRATUM_0065
805 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
808 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
809 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
810 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
814 config QCOM_FALKOR_ERRATUM_E1041
815 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
818 Falkor CPU may speculatively fetch instructions from an improper
819 memory location when MMU translation is changed from SCTLR_ELn[M]=1
820 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
824 config NVIDIA_CARMEL_CNP_ERRATUM
825 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
828 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
829 invalidate shared TLB entries installed by a different core, as it would
830 on standard ARM cores.
834 config SOCIONEXT_SYNQUACER_PREITS
835 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
838 Socionext Synquacer SoCs implement a separate h/w block to generate
839 MSI doorbell writes with non-zero values for the device ID.
848 default ARM64_4K_PAGES
850 Page size (translation granule) configuration.
852 config ARM64_4K_PAGES
855 This feature enables 4KB pages support.
857 config ARM64_16K_PAGES
860 The system will use 16KB pages support. AArch32 emulation
861 requires applications compiled with 16K (or a multiple of 16K)
864 config ARM64_64K_PAGES
867 This feature enables 64KB pages support (4KB by default)
868 allowing only two levels of page tables and faster TLB
869 look-up. AArch32 emulation requires applications compiled
870 with 64K aligned segments.
875 prompt "Virtual address space size"
876 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
877 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
878 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
880 Allows choosing one of multiple possible virtual address
881 space sizes. The level of translation table is determined by
882 a combination of page size and virtual address space size.
884 config ARM64_VA_BITS_36
885 bool "36-bit" if EXPERT
886 depends on ARM64_16K_PAGES
888 config ARM64_VA_BITS_39
890 depends on ARM64_4K_PAGES
892 config ARM64_VA_BITS_42
894 depends on ARM64_64K_PAGES
896 config ARM64_VA_BITS_47
898 depends on ARM64_16K_PAGES
900 config ARM64_VA_BITS_48
903 config ARM64_VA_BITS_52
905 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
907 Enable 52-bit virtual addressing for userspace when explicitly
908 requested via a hint to mmap(). The kernel will also use 52-bit
909 virtual addresses for its own mappings (provided HW support for
910 this feature is available, otherwise it reverts to 48-bit).
912 NOTE: Enabling 52-bit virtual addressing in conjunction with
913 ARMv8.3 Pointer Authentication will result in the PAC being
914 reduced from 7 bits to 3 bits, which may have a significant
915 impact on its susceptibility to brute-force attacks.
917 If unsure, select 48-bit virtual addressing instead.
921 config ARM64_FORCE_52BIT
922 bool "Force 52-bit virtual addresses for userspace"
923 depends on ARM64_VA_BITS_52 && EXPERT
925 For systems with 52-bit userspace VAs enabled, the kernel will attempt
926 to maintain compatibility with older software by providing 48-bit VAs
927 unless a hint is supplied to mmap.
929 This configuration option disables the 48-bit compatibility logic, and
930 forces all userspace addresses to be 52-bit on HW that supports it. One
931 should only enable this configuration option for stress testing userspace
932 memory management code. If unsure say N here.
936 default 36 if ARM64_VA_BITS_36
937 default 39 if ARM64_VA_BITS_39
938 default 42 if ARM64_VA_BITS_42
939 default 47 if ARM64_VA_BITS_47
940 default 48 if ARM64_VA_BITS_48
941 default 52 if ARM64_VA_BITS_52
944 prompt "Physical address space size"
945 default ARM64_PA_BITS_48
947 Choose the maximum physical address range that the kernel will
950 config ARM64_PA_BITS_48
953 config ARM64_PA_BITS_52
954 bool "52-bit (ARMv8.2)"
955 depends on ARM64_64K_PAGES
956 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
958 Enable support for a 52-bit physical address space, introduced as
959 part of the ARMv8.2-LPA extension.
961 With this enabled, the kernel will also continue to work on CPUs that
962 do not support ARMv8.2-LPA, but with some added memory overhead (and
963 minor performance overhead).
969 default 48 if ARM64_PA_BITS_48
970 default 52 if ARM64_PA_BITS_52
974 default CPU_LITTLE_ENDIAN
976 Select the endianness of data accesses performed by the CPU. Userspace
977 applications will need to be compiled and linked for the endianness
978 that is selected here.
980 config CPU_BIG_ENDIAN
981 bool "Build big-endian kernel"
982 depends on !LD_IS_LLD || LLD_VERSION >= 130000
984 Say Y if you plan on running a kernel with a big-endian userspace.
986 config CPU_LITTLE_ENDIAN
987 bool "Build little-endian kernel"
989 Say Y if you plan on running a kernel with a little-endian userspace.
990 This is usually the case for distributions targeting arm64.
995 bool "Multi-core scheduler support"
997 Multi-core scheduler support improves the CPU scheduler's decision
998 making when dealing with multi-core CPU chips at a cost of slightly
999 increased overhead in some places. If unsure say N here.
1002 bool "SMT scheduler support"
1004 Improves the CPU scheduler's decision making when dealing with
1005 MultiThreading at a cost of slightly increased overhead in some
1006 places. If unsure say N here.
1009 int "Maximum number of CPUs (2-4096)"
1014 bool "Support for hot-pluggable CPUs"
1015 select GENERIC_IRQ_MIGRATION
1017 Say Y here to experiment with turning CPUs off and on. CPUs
1018 can be controlled through /sys/devices/system/cpu.
1020 # Common NUMA Features
1022 bool "NUMA Memory Allocation and Scheduler Support"
1023 select GENERIC_ARCH_NUMA
1024 select ACPI_NUMA if ACPI
1027 Enable NUMA (Non-Uniform Memory Access) support.
1029 The kernel will try to allocate memory used by a CPU on the
1030 local memory of the CPU and add some more
1031 NUMA awareness to the kernel.
1034 int "Maximum NUMA Nodes (as a power of 2)"
1037 depends on NEED_MULTIPLE_NODES
1039 Specify the maximum number of NUMA Nodes available on the target
1040 system. Increases memory reserved to accommodate various tables.
1042 config USE_PERCPU_NUMA_NODE_ID
1046 config HAVE_SETUP_PER_CPU_AREA
1050 config NEED_PER_CPU_EMBED_FIRST_CHUNK
1054 config HOLES_IN_ZONE
1057 source "kernel/Kconfig.hz"
1059 config ARCH_SPARSEMEM_ENABLE
1061 select SPARSEMEM_VMEMMAP_ENABLE
1063 config ARCH_SPARSEMEM_DEFAULT
1064 def_bool ARCH_SPARSEMEM_ENABLE
1066 config ARCH_SELECT_MEMORY_MODEL
1067 def_bool ARCH_SPARSEMEM_ENABLE
1069 config ARCH_FLATMEM_ENABLE
1072 config HW_PERF_EVENTS
1076 config ARCH_HAS_FILTER_PGPROT
1079 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
1080 def_bool y if PGTABLE_LEVELS > 2
1082 # Supported by clang >= 7.0
1083 config CC_HAVE_SHADOW_CALL_STACK
1084 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1087 bool "Enable paravirtualization code"
1089 This changes the kernel so it can modify itself when it is run
1090 under a hypervisor, potentially improving performance significantly
1091 over full virtualization.
1093 config PARAVIRT_TIME_ACCOUNTING
1094 bool "Paravirtual steal time accounting"
1097 Select this option to enable fine granularity task steal time
1098 accounting. Time spent executing other tasks in parallel with
1099 the current vCPU is discounted from the vCPU power. To account for
1100 that, there can be a small performance impact.
1102 If in doubt, say N here.
1105 depends on PM_SLEEP_SMP
1107 bool "kexec system call"
1109 kexec is a system call that implements the ability to shutdown your
1110 current kernel, and to start another kernel. It is like a reboot
1111 but it is independent of the system firmware. And like a reboot
1112 you can start any kernel with it, not just Linux.
1115 bool "kexec file based system call"
1117 select HAVE_IMA_KEXEC if IMA
1119 This is new version of kexec system call. This system call is
1120 file based and takes file descriptors as system call argument
1121 for kernel and initramfs as opposed to list of segments as
1122 accepted by previous system call.
1125 bool "Verify kernel signature during kexec_file_load() syscall"
1126 depends on KEXEC_FILE
1128 Select this option to verify a signature with loaded kernel
1129 image. If configured, any attempt of loading a image without
1130 valid signature will fail.
1132 In addition to that option, you need to enable signature
1133 verification for the corresponding kernel image type being
1134 loaded in order for this to work.
1136 config KEXEC_IMAGE_VERIFY_SIG
1137 bool "Enable Image signature verification support"
1139 depends on KEXEC_SIG
1140 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1142 Enable Image signature verification support.
1144 comment "Support for PE file signature verification disabled"
1145 depends on KEXEC_SIG
1146 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1149 bool "Build kdump crash kernel"
1151 Generate crash dump after being started by kexec. This should
1152 be normally only set in special crash dump kernels which are
1153 loaded in the main kernel with kexec-tools into a specially
1154 reserved region and then later executed after a crash by
1157 For more details see Documentation/admin-guide/kdump/kdump.rst
1161 depends on HIBERNATION
1168 bool "Xen guest support on ARM64"
1169 depends on ARM64 && OF
1173 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1175 config FORCE_MAX_ZONEORDER
1177 default "14" if ARM64_64K_PAGES
1178 default "12" if ARM64_16K_PAGES
1181 The kernel memory allocator divides physically contiguous memory
1182 blocks into "zones", where each zone is a power of two number of
1183 pages. This option selects the largest power of two that the kernel
1184 keeps in the memory allocator. If you need to allocate very large
1185 blocks of physically contiguous memory, then you may need to
1186 increase this value.
1188 This config option is actually maximum order plus one. For example,
1189 a value of 11 means that the largest free memory block is 2^10 pages.
1191 We make sure that we can allocate upto a HugePage size for each configuration.
1193 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1195 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1196 4M allocations matching the default size used by generic code.
1198 config UNMAP_KERNEL_AT_EL0
1199 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1202 Speculation attacks against some high-performance processors can
1203 be used to bypass MMU permission checks and leak kernel data to
1204 userspace. This can be defended against by unmapping the kernel
1205 when running in userspace, mapping it back in on exception entry
1206 via a trampoline page in the vector table.
1210 config RODATA_FULL_DEFAULT_ENABLED
1211 bool "Apply r/o permissions of VM areas also to their linear aliases"
1214 Apply read-only attributes of VM areas to the linear alias of
1215 the backing pages as well. This prevents code or read-only data
1216 from being modified (inadvertently or intentionally) via another
1217 mapping of the same memory page. This additional enhancement can
1218 be turned off at runtime by passing rodata=[off|on] (and turned on
1219 with rodata=full if this option is set to 'n')
1221 This requires the linear region to be mapped down to pages,
1222 which may adversely affect performance in some cases.
1224 config ARM64_SW_TTBR0_PAN
1225 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1227 Enabling this option prevents the kernel from accessing
1228 user-space memory directly by pointing TTBR0_EL1 to a reserved
1229 zeroed area and reserved ASID. The user access routines
1230 restore the valid TTBR0_EL1 temporarily.
1232 config ARM64_TAGGED_ADDR_ABI
1233 bool "Enable the tagged user addresses syscall ABI"
1236 When this option is enabled, user applications can opt in to a
1237 relaxed ABI via prctl() allowing tagged addresses to be passed
1238 to system calls as pointer arguments. For details, see
1239 Documentation/arm64/tagged-address-abi.rst.
1242 bool "Kernel support for 32-bit EL0"
1243 depends on ARM64_4K_PAGES || EXPERT
1245 select OLD_SIGSUSPEND3
1246 select COMPAT_OLD_SIGACTION
1248 This option enables support for a 32-bit EL0 running under a 64-bit
1249 kernel at EL1. AArch32-specific components such as system calls,
1250 the user helper functions, VFP support and the ptrace interface are
1251 handled appropriately by the kernel.
1253 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1254 that you will only be able to execute AArch32 binaries that were compiled
1255 with page size aligned segments.
1257 If you want to execute 32-bit userspace applications, say Y.
1261 config KUSER_HELPERS
1262 bool "Enable kuser helpers page for 32-bit applications"
1265 Warning: disabling this option may break 32-bit user programs.
1267 Provide kuser helpers to compat tasks. The kernel provides
1268 helper code to userspace in read only form at a fixed location
1269 to allow userspace to be independent of the CPU type fitted to
1270 the system. This permits binaries to be run on ARMv4 through
1271 to ARMv8 without modification.
1273 See Documentation/arm/kernel_user_helpers.rst for details.
1275 However, the fixed address nature of these helpers can be used
1276 by ROP (return orientated programming) authors when creating
1279 If all of the binaries and libraries which run on your platform
1280 are built specifically for your platform, and make no use of
1281 these helpers, then you can turn this option off to hinder
1282 such exploits. However, in that case, if a binary or library
1283 relying on those helpers is run, it will not function correctly.
1285 Say N here only if you are absolutely certain that you do not
1286 need these helpers; otherwise, the safe option is to say Y.
1289 bool "Enable vDSO for 32-bit applications"
1290 depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1291 select GENERIC_COMPAT_VDSO
1294 Place in the process address space of 32-bit applications an
1295 ELF shared object providing fast implementations of gettimeofday
1298 You must have a 32-bit build of glibc 2.22 or later for programs
1299 to seamlessly take advantage of this.
1301 config THUMB2_COMPAT_VDSO
1302 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1303 depends on COMPAT_VDSO
1306 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1307 otherwise with '-marm'.
1309 menuconfig ARMV8_DEPRECATED
1310 bool "Emulate deprecated/obsolete ARMv8 instructions"
1313 Legacy software support may require certain instructions
1314 that have been deprecated or obsoleted in the architecture.
1316 Enable this config to enable selective emulation of these
1323 config SWP_EMULATION
1324 bool "Emulate SWP/SWPB instructions"
1326 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1327 they are always undefined. Say Y here to enable software
1328 emulation of these instructions for userspace using LDXR/STXR.
1329 This feature can be controlled at runtime with the abi.swp
1330 sysctl which is disabled by default.
1332 In some older versions of glibc [<=2.8] SWP is used during futex
1333 trylock() operations with the assumption that the code will not
1334 be preempted. This invalid assumption may be more likely to fail
1335 with SWP emulation enabled, leading to deadlock of the user
1338 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1339 on an external transaction monitoring block called a global
1340 monitor to maintain update atomicity. If your system does not
1341 implement a global monitor, this option can cause programs that
1342 perform SWP operations to uncached memory to deadlock.
1346 config CP15_BARRIER_EMULATION
1347 bool "Emulate CP15 Barrier instructions"
1349 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1350 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1351 strongly recommended to use the ISB, DSB, and DMB
1352 instructions instead.
1354 Say Y here to enable software emulation of these
1355 instructions for AArch32 userspace code. When this option is
1356 enabled, CP15 barrier usage is traced which can help
1357 identify software that needs updating. This feature can be
1358 controlled at runtime with the abi.cp15_barrier sysctl.
1362 config SETEND_EMULATION
1363 bool "Emulate SETEND instruction"
1365 The SETEND instruction alters the data-endianness of the
1366 AArch32 EL0, and is deprecated in ARMv8.
1368 Say Y here to enable software emulation of the instruction
1369 for AArch32 userspace code. This feature can be controlled
1370 at runtime with the abi.setend sysctl.
1372 Note: All the cpus on the system must have mixed endian support at EL0
1373 for this feature to be enabled. If a new CPU - which doesn't support mixed
1374 endian - is hotplugged in after this feature has been enabled, there could
1375 be unexpected results in the applications.
1382 menu "ARMv8.1 architectural features"
1384 config ARM64_HW_AFDBM
1385 bool "Support for hardware updates of the Access and Dirty page flags"
1388 The ARMv8.1 architecture extensions introduce support for
1389 hardware updates of the access and dirty information in page
1390 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1391 capable processors, accesses to pages with PTE_AF cleared will
1392 set this bit instead of raising an access flag fault.
1393 Similarly, writes to read-only pages with the DBM bit set will
1394 clear the read-only bit (AP[2]) instead of raising a
1397 Kernels built with this configuration option enabled continue
1398 to work on pre-ARMv8.1 hardware and the performance impact is
1399 minimal. If unsure, say Y.
1402 bool "Enable support for Privileged Access Never (PAN)"
1405 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1406 prevents the kernel or hypervisor from accessing user-space (EL0)
1409 Choosing this option will cause any unprotected (not using
1410 copy_to_user et al) memory access to fail with a permission fault.
1412 The feature is detected at runtime, and will remain as a 'nop'
1413 instruction if the cpu does not implement the feature.
1416 def_bool $(as-instr,.arch_extension rcpc)
1418 config AS_HAS_LSE_ATOMICS
1419 def_bool $(as-instr,.arch_extension lse)
1421 config ARM64_LSE_ATOMICS
1423 default ARM64_USE_LSE_ATOMICS
1424 depends on AS_HAS_LSE_ATOMICS
1426 config ARM64_USE_LSE_ATOMICS
1427 bool "Atomic instructions"
1428 depends on JUMP_LABEL
1431 As part of the Large System Extensions, ARMv8.1 introduces new
1432 atomic instructions that are designed specifically to scale in
1435 Say Y here to make use of these instructions for the in-kernel
1436 atomic routines. This incurs a small overhead on CPUs that do
1437 not support these instructions and requires the kernel to be
1438 built with binutils >= 2.25 in order for the new instructions
1443 menu "ARMv8.2 architectural features"
1446 bool "Enable support for persistent memory"
1447 select ARCH_HAS_PMEM_API
1448 select ARCH_HAS_UACCESS_FLUSHCACHE
1450 Say Y to enable support for the persistent memory API based on the
1451 ARMv8.2 DCPoP feature.
1453 The feature is detected at runtime, and the kernel will use DC CVAC
1454 operations if DC CVAP is not supported (following the behaviour of
1455 DC CVAP itself if the system does not define a point of persistence).
1457 config ARM64_RAS_EXTN
1458 bool "Enable support for RAS CPU Extensions"
1461 CPUs that support the Reliability, Availability and Serviceability
1462 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1463 errors, classify them and report them to software.
1465 On CPUs with these extensions system software can use additional
1466 barriers to determine if faults are pending and read the
1467 classification from a new set of registers.
1469 Selecting this feature will allow the kernel to use these barriers
1470 and access the new registers if the system supports the extension.
1471 Platform RAS features may additionally depend on firmware support.
1474 bool "Enable support for Common Not Private (CNP) translations"
1476 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1478 Common Not Private (CNP) allows translation table entries to
1479 be shared between different PEs in the same inner shareable
1480 domain, so the hardware can use this fact to optimise the
1481 caching of such entries in the TLB.
1483 Selecting this option allows the CNP feature to be detected
1484 at runtime, and does not affect PEs that do not implement
1489 menu "ARMv8.3 architectural features"
1491 config ARM64_PTR_AUTH
1492 bool "Enable support for pointer authentication"
1494 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1495 # Modern compilers insert a .note.gnu.property section note for PAC
1496 # which is only understood by binutils starting with version 2.33.1.
1497 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1498 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1499 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1501 Pointer authentication (part of the ARMv8.3 Extensions) provides
1502 instructions for signing and authenticating pointers against secret
1503 keys, which can be used to mitigate Return Oriented Programming (ROP)
1506 This option enables these instructions at EL0 (i.e. for userspace).
1507 Choosing this option will cause the kernel to initialise secret keys
1508 for each process at exec() time, with these keys being
1509 context-switched along with the process.
1511 If the compiler supports the -mbranch-protection or
1512 -msign-return-address flag (e.g. GCC 7 or later), then this option
1513 will also cause the kernel itself to be compiled with return address
1514 protection. In this case, and if the target hardware is known to
1515 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1516 disabled with minimal loss of protection.
1518 The feature is detected at runtime. If the feature is not present in
1519 hardware it will not be advertised to userspace/KVM guest nor will it
1522 If the feature is present on the boot CPU but not on a late CPU, then
1523 the late CPU will be parked. Also, if the boot CPU does not have
1524 address auth and the late CPU has then the late CPU will still boot
1525 but with the feature disabled. On such a system, this option should
1528 This feature works with FUNCTION_GRAPH_TRACER option only if
1529 DYNAMIC_FTRACE_WITH_REGS is enabled.
1531 config CC_HAS_BRANCH_PROT_PAC_RET
1532 # GCC 9 or later, clang 8 or later
1533 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1535 config CC_HAS_SIGN_RETURN_ADDRESS
1537 def_bool $(cc-option,-msign-return-address=all)
1540 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1542 config AS_HAS_CFI_NEGATE_RA_STATE
1543 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1547 menu "ARMv8.4 architectural features"
1549 config ARM64_AMU_EXTN
1550 bool "Enable support for the Activity Monitors Unit CPU extension"
1553 The activity monitors extension is an optional extension introduced
1554 by the ARMv8.4 CPU architecture. This enables support for version 1
1555 of the activity monitors architecture, AMUv1.
1557 To enable the use of this extension on CPUs that implement it, say Y.
1559 Note that for architectural reasons, firmware _must_ implement AMU
1560 support when running on CPUs that present the activity monitors
1561 extension. The required support is present in:
1562 * Version 1.5 and later of the ARM Trusted Firmware
1564 For kernels that have this configuration enabled but boot with broken
1565 firmware, you may need to say N here until the firmware is fixed.
1566 Otherwise you may experience firmware panics or lockups when
1567 accessing the counter registers. Even if you are not observing these
1568 symptoms, the values returned by the register reads might not
1569 correctly reflect reality. Most commonly, the value read will be 0,
1570 indicating that the counter is not enabled.
1572 config AS_HAS_ARMV8_4
1573 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1575 config ARM64_TLB_RANGE
1576 bool "Enable support for tlbi range feature"
1578 depends on AS_HAS_ARMV8_4
1580 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1581 range of input addresses.
1583 The feature introduces new assembly instructions, and they were
1584 support when binutils >= 2.30.
1588 menu "ARMv8.5 architectural features"
1590 config AS_HAS_ARMV8_5
1591 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1594 bool "Branch Target Identification support"
1597 Branch Target Identification (part of the ARMv8.5 Extensions)
1598 provides a mechanism to limit the set of locations to which computed
1599 branch instructions such as BR or BLR can jump.
1601 To make use of BTI on CPUs that support it, say Y.
1603 BTI is intended to provide complementary protection to other control
1604 flow integrity protection mechanisms, such as the Pointer
1605 authentication mechanism provided as part of the ARMv8.3 Extensions.
1606 For this reason, it does not make sense to enable this option without
1607 also enabling support for pointer authentication. Thus, when
1608 enabling this option you should also select ARM64_PTR_AUTH=y.
1610 Userspace binaries must also be specifically compiled to make use of
1611 this mechanism. If you say N here or the hardware does not support
1612 BTI, such binaries can still run, but you get no additional
1613 enforcement of branch destinations.
1615 config ARM64_BTI_KERNEL
1616 bool "Use Branch Target Identification for kernel"
1618 depends on ARM64_BTI
1619 depends on ARM64_PTR_AUTH
1620 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1621 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1622 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1623 depends on !(CC_IS_CLANG && GCOV_KERNEL)
1624 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1626 Build the kernel with Branch Target Identification annotations
1627 and enable enforcement of this for kernel code. When this option
1628 is enabled and the system supports BTI all kernel code including
1629 modular code must have BTI enabled.
1631 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1632 # GCC 9 or later, clang 8 or later
1633 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1636 bool "Enable support for E0PD"
1639 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1640 that EL0 accesses made via TTBR1 always fault in constant time,
1641 providing similar benefits to KASLR as those provided by KPTI, but
1642 with lower overhead and without disrupting legitimate access to
1643 kernel memory such as SPE.
1645 This option enables E0PD for TTBR1 where available.
1648 bool "Enable support for random number generation"
1651 Random number generation (part of the ARMv8.5 Extensions)
1652 provides a high bandwidth, cryptographically secure
1653 hardware random number generator.
1655 config ARM64_AS_HAS_MTE
1656 # Initial support for MTE went in binutils 2.32.0, checked with
1657 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1658 # as a late addition to the final architecture spec (LDGM/STGM)
1659 # is only supported in the newer 2.32.x and 2.33 binutils
1660 # versions, hence the extra "stgm" instruction check below.
1661 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1664 bool "Memory Tagging Extension support"
1666 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1667 depends on AS_HAS_ARMV8_5
1668 depends on AS_HAS_LSE_ATOMICS
1669 # Required for tag checking in the uaccess routines
1670 depends on ARM64_PAN
1671 select ARCH_USES_HIGH_VMA_FLAGS
1673 Memory Tagging (part of the ARMv8.5 Extensions) provides
1674 architectural support for run-time, always-on detection of
1675 various classes of memory error to aid with software debugging
1676 to eliminate vulnerabilities arising from memory-unsafe
1679 This option enables the support for the Memory Tagging
1680 Extension at EL0 (i.e. for userspace).
1682 Selecting this option allows the feature to be detected at
1683 runtime. Any secondary CPU not implementing this feature will
1684 not be allowed a late bring-up.
1686 Userspace binaries that want to use this feature must
1687 explicitly opt in. The mechanism for the userspace is
1690 Documentation/arm64/memory-tagging-extension.rst.
1694 menu "ARMv8.7 architectural features"
1697 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
1699 depends on ARM64_PAN
1701 Enhanced Privileged Access Never (EPAN) allows Privileged
1702 Access Never to be used with Execute-only mappings.
1704 The feature is detected at runtime, and will remain disabled
1705 if the cpu does not implement the feature.
1709 bool "ARM Scalable Vector Extension support"
1712 The Scalable Vector Extension (SVE) is an extension to the AArch64
1713 execution state which complements and extends the SIMD functionality
1714 of the base architecture to support much larger vectors and to enable
1715 additional vectorisation opportunities.
1717 To enable use of this extension on CPUs that implement it, say Y.
1719 On CPUs that support the SVE2 extensions, this option will enable
1722 Note that for architectural reasons, firmware _must_ implement SVE
1723 support when running on SVE capable hardware. The required support
1726 * version 1.5 and later of the ARM Trusted Firmware
1727 * the AArch64 boot wrapper since commit 5e1261e08abf
1728 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1730 For other firmware implementations, consult the firmware documentation
1733 If you need the kernel to boot on SVE-capable hardware with broken
1734 firmware, you may need to say N here until you get your firmware
1735 fixed. Otherwise, you may experience firmware panics or lockups when
1736 booting the kernel. If unsure and you are not observing these
1737 symptoms, you should assume that it is safe to say Y.
1739 config ARM64_MODULE_PLTS
1740 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1742 select HAVE_MOD_ARCH_SPECIFIC
1744 Allocate PLTs when loading modules so that jumps and calls whose
1745 targets are too far away for their relative offsets to be encoded
1746 in the instructions themselves can be bounced via veneers in the
1747 module's PLT. This allows modules to be allocated in the generic
1748 vmalloc area after the dedicated module memory area has been
1751 When running with address space randomization (KASLR), the module
1752 region itself may be too far away for ordinary relative jumps and
1753 calls, and so in that case, module PLTs are required and cannot be
1756 Specific errata workaround(s) might also force module PLTs to be
1757 enabled (ARM64_ERRATUM_843419).
1759 config ARM64_PSEUDO_NMI
1760 bool "Support for NMI-like interrupts"
1763 Adds support for mimicking Non-Maskable Interrupts through the use of
1764 GIC interrupt priority. This support requires version 3 or later of
1767 This high priority configuration for interrupts needs to be
1768 explicitly enabled by setting the kernel parameter
1769 "irqchip.gicv3_pseudo_nmi" to 1.
1774 config ARM64_DEBUG_PRIORITY_MASKING
1775 bool "Debug interrupt priority masking"
1777 This adds runtime checks to functions enabling/disabling
1778 interrupts when using priority masking. The additional checks verify
1779 the validity of ICC_PMR_EL1 when calling concerned functions.
1785 bool "Build a relocatable kernel image" if EXPERT
1786 select ARCH_HAS_RELR
1789 This builds the kernel as a Position Independent Executable (PIE),
1790 which retains all relocation metadata required to relocate the
1791 kernel binary at runtime to a different virtual address than the
1792 address it was linked at.
1793 Since AArch64 uses the RELA relocation format, this requires a
1794 relocation pass at runtime even if the kernel is loaded at the
1795 same address it was linked at.
1797 config RANDOMIZE_BASE
1798 bool "Randomize the address of the kernel image"
1799 select ARM64_MODULE_PLTS if MODULES
1802 Randomizes the virtual address at which the kernel image is
1803 loaded, as a security feature that deters exploit attempts
1804 relying on knowledge of the location of kernel internals.
1806 It is the bootloader's job to provide entropy, by passing a
1807 random u64 value in /chosen/kaslr-seed at kernel entry.
1809 When booting via the UEFI stub, it will invoke the firmware's
1810 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1811 to the kernel proper. In addition, it will randomise the physical
1812 location of the kernel Image as well.
1816 config RANDOMIZE_MODULE_REGION_FULL
1817 bool "Randomize the module region over a 4 GB range"
1818 depends on RANDOMIZE_BASE
1821 Randomizes the location of the module region inside a 4 GB window
1822 covering the core kernel. This way, it is less likely for modules
1823 to leak information about the location of core kernel data structures
1824 but it does imply that function calls between modules and the core
1825 kernel will need to be resolved via veneers in the module PLT.
1827 When this option is not set, the module region will be randomized over
1828 a limited range that contains the [_stext, _etext] interval of the
1829 core kernel, so branch relocations are always in range.
1831 config CC_HAVE_STACKPROTECTOR_SYSREG
1832 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1834 config STACKPROTECTOR_PER_TASK
1836 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1842 config ARM64_ACPI_PARKING_PROTOCOL
1843 bool "Enable support for the ARM64 ACPI parking protocol"
1846 Enable support for the ARM64 ACPI parking protocol. If disabled
1847 the kernel will not allow booting through the ARM64 ACPI parking
1848 protocol even if the corresponding data is present in the ACPI
1852 string "Default kernel command string"
1855 Provide a set of default command-line options at build time by
1856 entering them here. As a minimum, you should specify the the
1857 root device (e.g. root=/dev/nfs).
1860 prompt "Kernel command line type" if CMDLINE != ""
1861 default CMDLINE_FROM_BOOTLOADER
1863 Choose how the kernel will handle the provided default kernel
1864 command line string.
1866 config CMDLINE_FROM_BOOTLOADER
1867 bool "Use bootloader kernel arguments if available"
1869 Uses the command-line options passed by the boot loader. If
1870 the boot loader doesn't provide any, the default kernel command
1871 string provided in CMDLINE will be used.
1873 config CMDLINE_FORCE
1874 bool "Always use the default kernel command string"
1876 Always use the default kernel command string, even if the boot
1877 loader passes other arguments to the kernel.
1878 This is useful if you cannot or don't want to change the
1879 command-line options your boot loader passes to the kernel.
1887 bool "UEFI runtime support"
1888 depends on OF && !CPU_BIG_ENDIAN
1889 depends on KERNEL_MODE_NEON
1890 select ARCH_SUPPORTS_ACPI
1893 select EFI_PARAMS_FROM_FDT
1894 select EFI_RUNTIME_WRAPPERS
1896 select EFI_GENERIC_STUB
1897 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
1900 This option provides support for runtime services provided
1901 by UEFI firmware (such as non-volatile variables, realtime
1902 clock, and platform reset). A UEFI stub is also provided to
1903 allow the kernel to be booted as an EFI application. This
1904 is only useful on systems that have UEFI firmware.
1907 bool "Enable support for SMBIOS (DMI) tables"
1911 This enables SMBIOS/DMI feature for systems.
1913 This option is only useful on systems that have UEFI firmware.
1914 However, even with this option, the resultant kernel should
1915 continue to boot on existing non-UEFI platforms.
1919 config SYSVIPC_COMPAT
1921 depends on COMPAT && SYSVIPC
1923 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1925 depends on HUGETLB_PAGE && MIGRATION
1927 config ARCH_ENABLE_THP_MIGRATION
1929 depends on TRANSPARENT_HUGEPAGE
1931 menu "Power management options"
1933 source "kernel/power/Kconfig"
1935 config ARCH_HIBERNATION_POSSIBLE
1939 config ARCH_HIBERNATION_HEADER
1941 depends on HIBERNATION
1943 config ARCH_SUSPEND_POSSIBLE
1948 menu "CPU Power Management"
1950 source "drivers/cpuidle/Kconfig"
1952 source "drivers/cpufreq/Kconfig"
1956 source "drivers/firmware/Kconfig"
1958 source "drivers/acpi/Kconfig"
1960 source "arch/arm64/kvm/Kconfig"
1963 source "arch/arm64/crypto/Kconfig"