2 * linux/arch/arm/plat-versatile/platsmp.c
4 * Copyright (C) 2002 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This code is specific to the hardware found on ARM Realview and
12 * Versatile Express platforms where the CPUs are unable to be individually
13 * woken, and where there is no way to hot-unplug CPUs. Real platforms
14 * should not copy this code.
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/jiffies.h>
21 #include <linux/smp.h>
23 #include <asm/cacheflush.h>
24 #include <asm/smp_plat.h>
26 #include <plat/platsmp.h>
29 * versatile_cpu_release controls the release of CPUs from the holding
30 * pen in headsmp.S, which exists because we are not always able to
31 * control the release of individual CPUs from the board firmware.
32 * Production platforms do not need this.
34 volatile int versatile_cpu_release = -1;
37 * Write versatile_cpu_release in a way that is guaranteed to be visible to
38 * all observers, irrespective of whether they're taking part in coherency
39 * or not. This is necessary for the hotplug code to work reliably.
41 static void versatile_write_cpu_release(int val)
43 versatile_cpu_release = val;
45 sync_cache_w(&versatile_cpu_release);
49 * versatile_lock exists to avoid running the loops_per_jiffy delay loop
50 * calibrations on the secondary CPU while the requesting CPU is using
51 * the limited-bandwidth bus - which affects the calibration value.
52 * Production platforms do not need this.
54 static DEFINE_RAW_SPINLOCK(versatile_lock);
56 void versatile_secondary_init(unsigned int cpu)
59 * let the primary processor know we're out of the
60 * pen, then head off into the C entry point
62 versatile_write_cpu_release(-1);
65 * Synchronise with the boot thread.
67 raw_spin_lock(&versatile_lock);
68 raw_spin_unlock(&versatile_lock);
71 int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
73 unsigned long timeout;
76 * Set synchronisation state between this boot processor
77 * and the secondary one
79 raw_spin_lock(&versatile_lock);
82 * This is really belt and braces; we hold unintended secondary
83 * CPUs in the holding pen until we're ready for them. However,
84 * since we haven't sent them a soft interrupt, they shouldn't
87 versatile_write_cpu_release(cpu_logical_map(cpu));
90 * Send the secondary CPU a soft interrupt, thereby causing
91 * the boot monitor to read the system wide flags register,
92 * and branch to the address found there.
94 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
96 timeout = jiffies + (1 * HZ);
97 while (time_before(jiffies, timeout)) {
99 if (versatile_cpu_release == -1)
106 * now the secondary core is starting up let it run its
107 * calibrations, then wait for it to finish
109 raw_spin_unlock(&versatile_lock);
111 return versatile_cpu_release != -1 ? -ENOSYS : 0;