arch/arm/plat-omap/dma.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * linux/arch/arm/plat-omap/dma.c
   4  *
   5  * Copyright (C) 2003 - 2008 Nokia Corporation
   6  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   7  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   8  * Graphics DMA and LCD DMA graphics tranformations
   9  * by Imre Deak <imre.deak@nokia.com>
  10  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
  11  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
  12  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  13  *
  14  * Copyright (C) 2009 Texas Instruments
  15  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  16  *
  17  * Support functions for the OMAP internal DMA channels.
  18  *
  19  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
  20  * Converted DMA library into DMA platform driver.
  21  *      - G, Manjunath Kondaiah <manjugk@ti.com>
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/init.h>
  26 #include <linux/sched.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/errno.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/irq.h>
  31 #include <linux/io.h>
  32 #include <linux/slab.h>
  33 #include <linux/delay.h>
  34
  35 #include <linux/omap-dma.h>
  36
  37 #ifdef CONFIG_ARCH_OMAP1
  38 #include <mach/soc.h>
  39 #endif
  40
  41 /*
  42  * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
  43  * channels that an instance of the SDMA IP block can support.  Used
  44  * to size arrays.  (The actual maximum on a particular SoC may be less
  45  * than this -- for example, OMAP1 SDMA instances only support 17 logical
  46  * DMA channels.)
  47  */
  48 #define MAX_LOGICAL_DMA_CH_COUNT                32
  49
  50 #undef DEBUG
  51
  52 #ifndef CONFIG_ARCH_OMAP1
  53 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
  54         DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
  55 };
  56
  57 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
  58 #endif
  59
  60 #define OMAP_DMA_ACTIVE                 0x01
  61 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffffffff
  62
  63 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
  64
  65 static struct omap_system_dma_plat_info *p;
  66 static struct omap_dma_dev_attr *d;
  67 static void omap_clear_dma(int lch);
  68 static int enable_1510_mode;
  69 static u32 errata;
  70
  71 static struct omap_dma_global_context_registers {
  72         u32 dma_irqenable_l0;
  73         u32 dma_irqenable_l1;
  74         u32 dma_ocp_sysconfig;
  75         u32 dma_gcr;
  76 } omap_dma_global_context;
  77
  78 struct dma_link_info {
  79         int *linked_dmach_q;
  80         int no_of_lchs_linked;
  81
  82         int q_count;
  83         int q_tail;
  84         int q_head;
  85
  86         int chain_state;
  87         int chain_mode;
  88
  89 };
  90
  91 static struct dma_link_info *dma_linked_lch;
  92
  93 #ifndef CONFIG_ARCH_OMAP1
  94
  95 /* Chain handling macros */
  96 #define OMAP_DMA_CHAIN_QEMPTY(chain_id)                                 \
  97                 (0 == dma_linked_lch[chain_id].q_count)
  98 #define __OMAP_DMA_CHAIN_INCQ(end)                                      \
  99         ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
 100 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id)                               \
 101         do {                                                            \
 102                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
 103                 dma_linked_lch[chain_id].q_count--;                     \
 104         } while (0)
 105 #endif
 106
 107 static int dma_lch_count;
 108 static int dma_chan_count;
 109 static int omap_dma_reserve_channels;
 110
 111 static spinlock_t dma_chan_lock;
 112 static struct omap_dma_lch *dma_chan;
 113
 114 static inline void disable_lnk(int lch);
 115 static void omap_disable_channel_irq(int lch);
 116 static inline void omap_enable_channel_irq(int lch);
 117
 118 #ifdef CONFIG_ARCH_OMAP15XX
 119 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
 120 static int omap_dma_in_1510_mode(void)
 121 {
 122         return enable_1510_mode;
 123 }
 124 #else
 125 #define omap_dma_in_1510_mode()         0
 126 #endif
 127
 128 #ifdef CONFIG_ARCH_OMAP1
 129 static inline void set_gdma_dev(int req, int dev)
 130 {
 131         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 132         int shift = ((req - 1) % 5) * 6;
 133         u32 l;
 134
 135         l = omap_readl(reg);
 136         l &= ~(0x3f << shift);
 137         l |= (dev - 1) << shift;
 138         omap_writel(l, reg);
 139 }
 140 #else
 141 #define set_gdma_dev(req, dev)  do {} while (0)
 142 #define omap_readl(reg)         0
 143 #define omap_writel(val, reg)   do {} while (0)
 144 #endif
 145
 146 #ifdef CONFIG_ARCH_OMAP1
 147 void omap_set_dma_priority(int lch, int dst_port, int priority)
 148 {
 149         unsigned long reg;
 150         u32 l;
 151
 152         if (dma_omap1()) {
 153                 switch (dst_port) {
 154                 case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
 155                         reg = OMAP_TC_OCPT1_PRIOR;
 156                         break;
 157                 case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
 158                         reg = OMAP_TC_OCPT2_PRIOR;
 159                         break;
 160                 case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
 161                         reg = OMAP_TC_EMIFF_PRIOR;
 162                         break;
 163                 case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
 164                         reg = OMAP_TC_EMIFS_PRIOR;
 165                         break;
 166                 default:
 167                         BUG();
 168                         return;
 169                 }
 170                 l = omap_readl(reg);
 171                 l &= ~(0xf << 8);
 172                 l |= (priority & 0xf) << 8;
 173                 omap_writel(l, reg);
 174         }
 175 }
 176 #endif
 177
 178 #ifdef CONFIG_ARCH_OMAP2PLUS
 179 void omap_set_dma_priority(int lch, int dst_port, int priority)
 180 {
 181         u32 ccr;
 182
 183         ccr = p->dma_read(CCR, lch);
 184         if (priority)
 185                 ccr |= (1 << 6);
 186         else
 187                 ccr &= ~(1 << 6);
 188         p->dma_write(ccr, CCR, lch);
 189 }
 190 #endif
 191 EXPORT_SYMBOL(omap_set_dma_priority);
 192
 193 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 194                                   int frame_count, int sync_mode,
 195                                   int dma_trigger, int src_or_dst_synch)
 196 {
 197         u32 l;
 198
 199         l = p->dma_read(CSDP, lch);
 200         l &= ~0x03;
 201         l |= data_type;
 202         p->dma_write(l, CSDP, lch);
 203
 204         if (dma_omap1()) {
 205                 u16 ccr;
 206
 207                 ccr = p->dma_read(CCR, lch);
 208                 ccr &= ~(1 << 5);
 209                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
 210                         ccr |= 1 << 5;
 211                 p->dma_write(ccr, CCR, lch);
 212
 213                 ccr = p->dma_read(CCR2, lch);
 214                 ccr &= ~(1 << 2);
 215                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
 216                         ccr |= 1 << 2;
 217                 p->dma_write(ccr, CCR2, lch);
 218         }
 219
 220         if (dma_omap2plus() && dma_trigger) {
 221                 u32 val;
 222
 223                 val = p->dma_read(CCR, lch);
 224
 225                 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
 226                 val &= ~((1 << 23) | (3 << 19) | 0x1f);
 227                 val |= (dma_trigger & ~0x1f) << 14;
 228                 val |= dma_trigger & 0x1f;
 229
 230                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
 231                         val |= 1 << 5;
 232                 else
 233                         val &= ~(1 << 5);
 234
 235                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
 236                         val |= 1 << 18;
 237                 else
 238                         val &= ~(1 << 18);
 239
 240                 if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
 241                         val &= ~(1 << 24);      /* dest synch */
 242                         val |= (1 << 23);       /* Prefetch */
 243                 } else if (src_or_dst_synch) {
 244                         val |= 1 << 24;         /* source synch */
 245                 } else {
 246                         val &= ~(1 << 24);      /* dest synch */
 247                 }
 248                 p->dma_write(val, CCR, lch);
 249         }
 250
 251         p->dma_write(elem_count, CEN, lch);
 252         p->dma_write(frame_count, CFN, lch);
 253 }
 254 EXPORT_SYMBOL(omap_set_dma_transfer_params);
 255
 256 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
 257 {
 258         if (dma_omap1() && !dma_omap15xx()) {
 259                 u32 l;
 260
 261                 l = p->dma_read(LCH_CTRL, lch);
 262                 l &= ~0x7;
 263                 l |= mode;
 264                 p->dma_write(l, LCH_CTRL, lch);
 265         }
 266 }
 267 EXPORT_SYMBOL(omap_set_dma_channel_mode);
 268
 269 /* Note that src_port is only for omap1 */
 270 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 271                              unsigned long src_start,
 272                              int src_ei, int src_fi)
 273 {
 274         u32 l;
 275
 276         if (dma_omap1()) {
 277                 u16 w;
 278
 279                 w = p->dma_read(CSDP, lch);
 280                 w &= ~(0x1f << 2);
 281                 w |= src_port << 2;
 282                 p->dma_write(w, CSDP, lch);
 283         }
 284
 285         l = p->dma_read(CCR, lch);
 286         l &= ~(0x03 << 12);
 287         l |= src_amode << 12;
 288         p->dma_write(l, CCR, lch);
 289
 290         p->dma_write(src_start, CSSA, lch);
 291
 292         p->dma_write(src_ei, CSEI, lch);
 293         p->dma_write(src_fi, CSFI, lch);
 294 }
 295 EXPORT_SYMBOL(omap_set_dma_src_params);
 296
 297 void omap_set_dma_src_data_pack(int lch, int enable)
 298 {
 299         u32 l;
 300
 301         l = p->dma_read(CSDP, lch);
 302         l &= ~(1 << 6);
 303         if (enable)
 304                 l |= (1 << 6);
 305         p->dma_write(l, CSDP, lch);
 306 }
 307 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
 308
 309 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 310 {
 311         unsigned int burst = 0;
 312         u32 l;
 313
 314         l = p->dma_read(CSDP, lch);
 315         l &= ~(0x03 << 7);
 316
 317         switch (burst_mode) {
 318         case OMAP_DMA_DATA_BURST_DIS:
 319                 break;
 320         case OMAP_DMA_DATA_BURST_4:
 321                 if (dma_omap2plus())
 322                         burst = 0x1;
 323                 else
 324                         burst = 0x2;
 325                 break;
 326         case OMAP_DMA_DATA_BURST_8:
 327                 if (dma_omap2plus()) {
 328                         burst = 0x2;
 329                         break;
 330                 }
 331                 /*
 332                  * not supported by current hardware on OMAP1
 333                  * w |= (0x03 << 7);
 334                  */
 335                 /* fall through */
 336         case OMAP_DMA_DATA_BURST_16:
 337                 if (dma_omap2plus()) {
 338                         burst = 0x3;
 339                         break;
 340                 }
 341                 /* OMAP1 don't support burst 16 */
 342                 /* fall through */
 343         default:
 344                 BUG();
 345         }
 346
 347         l |= (burst << 7);
 348         p->dma_write(l, CSDP, lch);
 349 }
 350 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
 351
 352 /* Note that dest_port is only for OMAP1 */
 353 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 354                               unsigned long dest_start,
 355                               int dst_ei, int dst_fi)
 356 {
 357         u32 l;
 358
 359         if (dma_omap1()) {
 360                 l = p->dma_read(CSDP, lch);
 361                 l &= ~(0x1f << 9);
 362                 l |= dest_port << 9;
 363                 p->dma_write(l, CSDP, lch);
 364         }
 365
 366         l = p->dma_read(CCR, lch);
 367         l &= ~(0x03 << 14);
 368         l |= dest_amode << 14;
 369         p->dma_write(l, CCR, lch);
 370
 371         p->dma_write(dest_start, CDSA, lch);
 372
 373         p->dma_write(dst_ei, CDEI, lch);
 374         p->dma_write(dst_fi, CDFI, lch);
 375 }
 376 EXPORT_SYMBOL(omap_set_dma_dest_params);
 377
 378 void omap_set_dma_dest_data_pack(int lch, int enable)
 379 {
 380         u32 l;
 381
 382         l = p->dma_read(CSDP, lch);
 383         l &= ~(1 << 13);
 384         if (enable)
 385                 l |= 1 << 13;
 386         p->dma_write(l, CSDP, lch);
 387 }
 388 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
 389
 390 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 391 {
 392         unsigned int burst = 0;
 393         u32 l;
 394
 395         l = p->dma_read(CSDP, lch);
 396         l &= ~(0x03 << 14);
 397
 398         switch (burst_mode) {
 399         case OMAP_DMA_DATA_BURST_DIS:
 400                 break;
 401         case OMAP_DMA_DATA_BURST_4:
 402                 if (dma_omap2plus())
 403                         burst = 0x1;
 404                 else
 405                         burst = 0x2;
 406                 break;
 407         case OMAP_DMA_DATA_BURST_8:
 408                 if (dma_omap2plus())
 409                         burst = 0x2;
 410                 else
 411                         burst = 0x3;
 412                 break;
 413         case OMAP_DMA_DATA_BURST_16:
 414                 if (dma_omap2plus()) {
 415                         burst = 0x3;
 416                         break;
 417                 }
 418                 /* OMAP1 don't support burst 16 */
 419                 /* fall through */
 420         default:
 421                 printk(KERN_ERR "Invalid DMA burst mode\n");
 422                 BUG();
 423                 return;
 424         }
 425         l |= (burst << 14);
 426         p->dma_write(l, CSDP, lch);
 427 }
 428 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 429
 430 static inline void omap_enable_channel_irq(int lch)
 431 {
 432         /* Clear CSR */
 433         if (dma_omap1())
 434                 p->dma_read(CSR, lch);
 435         else
 436                 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
 437
 438         /* Enable some nice interrupts. */
 439         p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
 440 }
 441
 442 static inline void omap_disable_channel_irq(int lch)
 443 {
 444         /* disable channel interrupts */
 445         p->dma_write(0, CICR, lch);
 446         /* Clear CSR */
 447         if (dma_omap1())
 448                 p->dma_read(CSR, lch);
 449         else
 450                 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
 451 }
 452
 453 void omap_disable_dma_irq(int lch, u16 bits)
 454 {
 455         dma_chan[lch].enabled_irqs &= ~bits;
 456 }
 457 EXPORT_SYMBOL(omap_disable_dma_irq);
 458
 459 static inline void enable_lnk(int lch)
 460 {
 461         u32 l;
 462
 463         l = p->dma_read(CLNK_CTRL, lch);
 464
 465         if (dma_omap1())
 466                 l &= ~(1 << 14);
 467
 468         /* Set the ENABLE_LNK bits */
 469         if (dma_chan[lch].next_lch != -1)
 470                 l = dma_chan[lch].next_lch | (1 << 15);
 471
 472 #ifndef CONFIG_ARCH_OMAP1
 473         if (dma_omap2plus())
 474                 if (dma_chan[lch].next_linked_ch != -1)
 475                         l = dma_chan[lch].next_linked_ch | (1 << 15);
 476 #endif
 477
 478         p->dma_write(l, CLNK_CTRL, lch);
 479 }
 480
 481 static inline void disable_lnk(int lch)
 482 {
 483         u32 l;
 484
 485         l = p->dma_read(CLNK_CTRL, lch);
 486
 487         /* Disable interrupts */
 488         omap_disable_channel_irq(lch);
 489
 490         if (dma_omap1()) {
 491                 /* Set the STOP_LNK bit */
 492                 l |= 1 << 14;
 493         }
 494
 495         if (dma_omap2plus()) {
 496                 /* Clear the ENABLE_LNK bit */
 497                 l &= ~(1 << 15);
 498         }
 499
 500         p->dma_write(l, CLNK_CTRL, lch);
 501         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 502 }
 503
 504 static inline void omap2_enable_irq_lch(int lch)
 505 {
 506         u32 val;
 507         unsigned long flags;
 508
 509         if (dma_omap1())
 510                 return;
 511
 512         spin_lock_irqsave(&dma_chan_lock, flags);
 513         /* clear IRQ STATUS */
 514         p->dma_write(1 << lch, IRQSTATUS_L0, lch);
 515         /* Enable interrupt */
 516         val = p->dma_read(IRQENABLE_L0, lch);
 517         val |= 1 << lch;
 518         p->dma_write(val, IRQENABLE_L0, lch);
 519         spin_unlock_irqrestore(&dma_chan_lock, flags);
 520 }
 521
 522 static inline void omap2_disable_irq_lch(int lch)
 523 {
 524         u32 val;
 525         unsigned long flags;
 526
 527         if (dma_omap1())
 528                 return;
 529
 530         spin_lock_irqsave(&dma_chan_lock, flags);
 531         /* Disable interrupt */
 532         val = p->dma_read(IRQENABLE_L0, lch);
 533         val &= ~(1 << lch);
 534         p->dma_write(val, IRQENABLE_L0, lch);
 535         /* clear IRQ STATUS */
 536         p->dma_write(1 << lch, IRQSTATUS_L0, lch);
 537         spin_unlock_irqrestore(&dma_chan_lock, flags);
 538 }
 539
 540 int omap_request_dma(int dev_id, const char *dev_name,
 541                      void (*callback)(int lch, u16 ch_status, void *data),
 542                      void *data, int *dma_ch_out)
 543 {
 544         int ch, free_ch = -1;
 545         unsigned long flags;
 546         struct omap_dma_lch *chan;
 547
 548         WARN(strcmp(dev_name, "DMA engine"), "Using deprecated platform DMA API - please update to DMA engine");
 549
 550         spin_lock_irqsave(&dma_chan_lock, flags);
 551         for (ch = 0; ch < dma_chan_count; ch++) {
 552                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
 553                         free_ch = ch;
 554                         /* Exit after first free channel found */
 555                         break;
 556                 }
 557         }
 558         if (free_ch == -1) {
 559                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 560                 return -EBUSY;
 561         }
 562         chan = dma_chan + free_ch;
 563         chan->dev_id = dev_id;
 564
 565         if (p->clear_lch_regs)
 566                 p->clear_lch_regs(free_ch);
 567
 568         if (dma_omap2plus())
 569                 omap_clear_dma(free_ch);
 570
 571         spin_unlock_irqrestore(&dma_chan_lock, flags);
 572
 573         chan->dev_name = dev_name;
 574         chan->callback = callback;
 575         chan->data = data;
 576         chan->flags = 0;
 577
 578 #ifndef CONFIG_ARCH_OMAP1
 579         if (dma_omap2plus()) {
 580                 chan->chain_id = -1;
 581                 chan->next_linked_ch = -1;
 582         }
 583 #endif
 584
 585         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 586
 587         if (dma_omap1())
 588                 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
 589         else if (dma_omap2plus())
 590                 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
 591                         OMAP2_DMA_TRANS_ERR_IRQ;
 592
 593         if (dma_omap16xx()) {
 594                 /* If the sync device is set, configure it dynamically. */
 595                 if (dev_id != 0) {
 596                         set_gdma_dev(free_ch + 1, dev_id);
 597                         dev_id = free_ch + 1;
 598                 }
 599                 /*
 600                  * Disable the 1510 compatibility mode and set the sync device
 601                  * id.
 602                  */
 603                 p->dma_write(dev_id | (1 << 10), CCR, free_ch);
 604         } else if (dma_omap1()) {
 605                 p->dma_write(dev_id, CCR, free_ch);
 606         }
 607
 608         if (dma_omap2plus()) {
 609                 omap_enable_channel_irq(free_ch);
 610                 omap2_enable_irq_lch(free_ch);
 611         }
 612
 613         *dma_ch_out = free_ch;
 614
 615         return 0;
 616 }
 617 EXPORT_SYMBOL(omap_request_dma);
 618
 619 void omap_free_dma(int lch)
 620 {
 621         unsigned long flags;
 622
 623         if (dma_chan[lch].dev_id == -1) {
 624                 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
 625                        lch);
 626                 return;
 627         }
 628
 629         /* Disable interrupt for logical channel */
 630         if (dma_omap2plus())
 631                 omap2_disable_irq_lch(lch);
 632
 633         /* Disable all DMA interrupts for the channel. */
 634         omap_disable_channel_irq(lch);
 635
 636         /* Make sure the DMA transfer is stopped. */
 637         p->dma_write(0, CCR, lch);
 638
 639         /* Clear registers */
 640         if (dma_omap2plus())
 641                 omap_clear_dma(lch);
 642
 643         spin_lock_irqsave(&dma_chan_lock, flags);
 644         dma_chan[lch].dev_id = -1;
 645         dma_chan[lch].next_lch = -1;
 646         dma_chan[lch].callback = NULL;
 647         spin_unlock_irqrestore(&dma_chan_lock, flags);
 648 }
 649 EXPORT_SYMBOL(omap_free_dma);
 650
 651 /**
 652  * @brief omap_dma_set_global_params : Set global priority settings for dma
 653  *
 654  * @param arb_rate
 655  * @param max_fifo_depth
 656  * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
 657  *                                                 DMA_THREAD_RESERVE_ONET
 658  *                                                 DMA_THREAD_RESERVE_TWOT
 659  *                                                 DMA_THREAD_RESERVE_THREET
 660  */
 661 static void
 662 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
 663 {
 664         u32 reg;
 665
 666         if (dma_omap1()) {
 667                 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
 668                 return;
 669         }
 670
 671         if (max_fifo_depth == 0)
 672                 max_fifo_depth = 1;
 673         if (arb_rate == 0)
 674                 arb_rate = 1;
 675
 676         reg = 0xff & max_fifo_depth;
 677         reg |= (0x3 & tparams) << 12;
 678         reg |= (arb_rate & 0xff) << 16;
 679
 680         p->dma_write(reg, GCR, 0);
 681 }
 682
 683 /*
 684  * Clears any DMA state so the DMA engine is ready to restart with new buffers
 685  * through omap_start_dma(). Any buffers in flight are discarded.
 686  */
 687 static void omap_clear_dma(int lch)
 688 {
 689         unsigned long flags;
 690
 691         local_irq_save(flags);
 692         p->clear_dma(lch);
 693         local_irq_restore(flags);
 694 }
 695
 696 void omap_start_dma(int lch)
 697 {
 698         u32 l;
 699
 700         /*
 701          * The CPC/CDAC register needs to be initialized to zero
 702          * before starting dma transfer.
 703          */
 704         if (dma_omap15xx())
 705                 p->dma_write(0, CPC, lch);
 706         else
 707                 p->dma_write(0, CDAC, lch);
 708
 709         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 710                 int next_lch, cur_lch;
 711                 char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
 712
 713                 /* Set the link register of the first channel */
 714                 enable_lnk(lch);
 715
 716                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 717                 dma_chan_link_map[lch] = 1;
 718
 719                 cur_lch = dma_chan[lch].next_lch;
 720                 do {
 721                         next_lch = dma_chan[cur_lch].next_lch;
 722
 723                         /* The loop case: we've been here already */
 724                         if (dma_chan_link_map[cur_lch])
 725                                 break;
 726                         /* Mark the current channel */
 727                         dma_chan_link_map[cur_lch] = 1;
 728
 729                         enable_lnk(cur_lch);
 730                         omap_enable_channel_irq(cur_lch);
 731
 732                         cur_lch = next_lch;
 733                 } while (next_lch != -1);
 734         } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
 735                 p->dma_write(lch, CLNK_CTRL, lch);
 736
 737         omap_enable_channel_irq(lch);
 738
 739         l = p->dma_read(CCR, lch);
 740
 741         if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
 742                         l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
 743         l |= OMAP_DMA_CCR_EN;
 744
 745         /*
 746          * As dma_write() uses IO accessors which are weakly ordered, there
 747          * is no guarantee that data in coherent DMA memory will be visible
 748          * to the DMA device.  Add a memory barrier here to ensure that any
 749          * such data is visible prior to enabling DMA.
 750          */
 751         mb();
 752         p->dma_write(l, CCR, lch);
 753
 754         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 755 }
 756 EXPORT_SYMBOL(omap_start_dma);
 757
 758 void omap_stop_dma(int lch)
 759 {
 760         u32 l;
 761
 762         /* Disable all interrupts on the channel */
 763         omap_disable_channel_irq(lch);
 764
 765         l = p->dma_read(CCR, lch);
 766         if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
 767                         (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
 768                 int i = 0;
 769                 u32 sys_cf;
 770
 771                 /* Configure No-Standby */
 772                 l = p->dma_read(OCP_SYSCONFIG, lch);
 773                 sys_cf = l;
 774                 l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
 775                 l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
 776                 p->dma_write(l , OCP_SYSCONFIG, 0);
 777
 778                 l = p->dma_read(CCR, lch);
 779                 l &= ~OMAP_DMA_CCR_EN;
 780                 p->dma_write(l, CCR, lch);
 781
 782                 /* Wait for sDMA FIFO drain */
 783                 l = p->dma_read(CCR, lch);
 784                 while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
 785                                         OMAP_DMA_CCR_WR_ACTIVE))) {
 786                         udelay(5);
 787                         i++;
 788                         l = p->dma_read(CCR, lch);
 789                 }
 790                 if (i >= 100)
 791                         pr_err("DMA drain did not complete on lch %d\n", lch);
 792                 /* Restore OCP_SYSCONFIG */
 793                 p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
 794         } else {
 795                 l &= ~OMAP_DMA_CCR_EN;
 796                 p->dma_write(l, CCR, lch);
 797         }
 798
 799         /*
 800          * Ensure that data transferred by DMA is visible to any access
 801          * after DMA has been disabled.  This is important for coherent
 802          * DMA regions.
 803          */
 804         mb();
 805
 806         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 807                 int next_lch, cur_lch = lch;
 808                 char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
 809
 810                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 811                 do {
 812                         /* The loop case: we've been here already */
 813                         if (dma_chan_link_map[cur_lch])
 814                                 break;
 815                         /* Mark the current channel */
 816                         dma_chan_link_map[cur_lch] = 1;
 817
 818                         disable_lnk(cur_lch);
 819
 820                         next_lch = dma_chan[cur_lch].next_lch;
 821                         cur_lch = next_lch;
 822                 } while (next_lch != -1);
 823         }
 824
 825         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 826 }
 827 EXPORT_SYMBOL(omap_stop_dma);
 828
 829 /*
 830  * Allows changing the DMA callback function or data. This may be needed if
 831  * the driver shares a single DMA channel for multiple dma triggers.
 832  */
 833 /*
 834  * Returns current physical source address for the given DMA channel.
 835  * If the channel is running the caller must disable interrupts prior calling
 836  * this function and process the returned value before re-enabling interrupt to
 837  * prevent races with the interrupt handler. Note that in continuous mode there
 838  * is a chance for CSSA_L register overflow between the two reads resulting
 839  * in incorrect return value.
 840  */
 841 dma_addr_t omap_get_dma_src_pos(int lch)
 842 {
 843         dma_addr_t offset = 0;
 844
 845         if (dma_omap15xx())
 846                 offset = p->dma_read(CPC, lch);
 847         else
 848                 offset = p->dma_read(CSAC, lch);
 849
 850         if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
 851                 offset = p->dma_read(CSAC, lch);
 852
 853         if (!dma_omap15xx()) {
 854                 /*
 855                  * CDAC == 0 indicates that the DMA transfer on the channel has
 856                  * not been started (no data has been transferred so far).
 857                  * Return the programmed source start address in this case.
 858                  */
 859                 if (likely(p->dma_read(CDAC, lch)))
 860                         offset = p->dma_read(CSAC, lch);
 861                 else
 862                         offset = p->dma_read(CSSA, lch);
 863         }
 864
 865         if (dma_omap1())
 866                 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
 867
 868         return offset;
 869 }
 870 EXPORT_SYMBOL(omap_get_dma_src_pos);
 871
 872 /*
 873  * Returns current physical destination address for the given DMA channel.
 874  * If the channel is running the caller must disable interrupts prior calling
 875  * this function and process the returned value before re-enabling interrupt to
 876  * prevent races with the interrupt handler. Note that in continuous mode there
 877  * is a chance for CDSA_L register overflow between the two reads resulting
 878  * in incorrect return value.
 879  */
 880 dma_addr_t omap_get_dma_dst_pos(int lch)
 881 {
 882         dma_addr_t offset = 0;
 883
 884         if (dma_omap15xx())
 885                 offset = p->dma_read(CPC, lch);
 886         else
 887                 offset = p->dma_read(CDAC, lch);
 888
 889         /*
 890          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
 891          * read before the DMA controller finished disabling the channel.
 892          */
 893         if (!dma_omap15xx() && offset == 0) {
 894                 offset = p->dma_read(CDAC, lch);
 895                 /*
 896                  * CDAC == 0 indicates that the DMA transfer on the channel has
 897                  * not been started (no data has been transferred so far).
 898                  * Return the programmed destination start address in this case.
 899                  */
 900                 if (unlikely(!offset))
 901                         offset = p->dma_read(CDSA, lch);
 902         }
 903
 904         if (dma_omap1())
 905                 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
 906
 907         return offset;
 908 }
 909 EXPORT_SYMBOL(omap_get_dma_dst_pos);
 910
 911 int omap_get_dma_active_status(int lch)
 912 {
 913         return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
 914 }
 915 EXPORT_SYMBOL(omap_get_dma_active_status);
 916
 917 int omap_dma_running(void)
 918 {
 919         int lch;
 920
 921         if (dma_omap1())
 922                 if (omap_lcd_dma_running())
 923                         return 1;
 924
 925         for (lch = 0; lch < dma_chan_count; lch++)
 926                 if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
 927                         return 1;
 928
 929         return 0;
 930 }
 931
 932 /*----------------------------------------------------------------------------*/
 933
 934 #ifdef CONFIG_ARCH_OMAP1
 935
 936 static int omap1_dma_handle_ch(int ch)
 937 {
 938         u32 csr;
 939
 940         if (enable_1510_mode && ch >= 6) {
 941                 csr = dma_chan[ch].saved_csr;
 942                 dma_chan[ch].saved_csr = 0;
 943         } else
 944                 csr = p->dma_read(CSR, ch);
 945         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
 946                 dma_chan[ch + 6].saved_csr = csr >> 7;
 947                 csr &= 0x7f;
 948         }
 949         if ((csr & 0x3f) == 0)
 950                 return 0;
 951         if (unlikely(dma_chan[ch].dev_id == -1)) {
 952                 pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n",
 953                         ch, csr);
 954                 return 0;
 955         }
 956         if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
 957                 pr_warn("DMA timeout with device %d\n", dma_chan[ch].dev_id);
 958         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
 959                 pr_warn("DMA synchronization event drop occurred with device %d\n",
 960                         dma_chan[ch].dev_id);
 961         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
 962                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
 963         if (likely(dma_chan[ch].callback != NULL))
 964                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
 965
 966         return 1;
 967 }
 968
 969 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
 970 {
 971         int ch = ((int) dev_id) - 1;
 972         int handled = 0;
 973
 974         for (;;) {
 975                 int handled_now = 0;
 976
 977                 handled_now += omap1_dma_handle_ch(ch);
 978                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
 979                         handled_now += omap1_dma_handle_ch(ch + 6);
 980                 if (!handled_now)
 981                         break;
 982                 handled += handled_now;
 983         }
 984
 985         return handled ? IRQ_HANDLED : IRQ_NONE;
 986 }
 987
 988 #else
 989 #define omap1_dma_irq_handler   NULL
 990 #endif
 991
 992 #ifdef CONFIG_ARCH_OMAP2PLUS
 993
 994 static int omap2_dma_handle_ch(int ch)
 995 {
 996         u32 status = p->dma_read(CSR, ch);
 997
 998         if (!status) {
 999                 if (printk_ratelimit())
1000                         pr_warn("Spurious DMA IRQ for lch %d\n", ch);
1001                 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1002                 return 0;
1003         }
1004         if (unlikely(dma_chan[ch].dev_id == -1)) {
1005                 if (printk_ratelimit())
1006                         pr_warn("IRQ %04x for non-allocated DMA channel %d\n",
1007                                 status, ch);
1008                 return 0;
1009         }
1010         if (unlikely(status & OMAP_DMA_DROP_IRQ))
1011                 pr_info("DMA synchronization event drop occurred with device %d\n",
1012                         dma_chan[ch].dev_id);
1013         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1014                 printk(KERN_INFO "DMA transaction error with device %d\n",
1015                        dma_chan[ch].dev_id);
1016                 if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
1017                         u32 ccr;
1018
1019                         ccr = p->dma_read(CCR, ch);
1020                         ccr &= ~OMAP_DMA_CCR_EN;
1021                         p->dma_write(ccr, CCR, ch);
1022                         dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1023                 }
1024         }
1025         if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1026                 printk(KERN_INFO "DMA secure error with device %d\n",
1027                        dma_chan[ch].dev_id);
1028         if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1029                 printk(KERN_INFO "DMA misaligned error with device %d\n",
1030                        dma_chan[ch].dev_id);
1031
1032         p->dma_write(status, CSR, ch);
1033         p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1034         /* read back the register to flush the write */
1035         p->dma_read(IRQSTATUS_L0, ch);
1036
1037         /* If the ch is not chained then chain_id will be -1 */
1038         if (dma_chan[ch].chain_id != -1) {
1039                 int chain_id = dma_chan[ch].chain_id;
1040                 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1041                 if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
1042                         dma_chan[dma_chan[ch].next_linked_ch].state =
1043                                                         DMA_CH_STARTED;
1044                 if (dma_linked_lch[chain_id].chain_mode ==
1045                                                 OMAP_DMA_DYNAMIC_CHAIN)
1046                         disable_lnk(ch);
1047
1048                 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1049                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1050
1051                 status = p->dma_read(CSR, ch);
1052                 p->dma_write(status, CSR, ch);
1053         }
1054
1055         if (likely(dma_chan[ch].callback != NULL))
1056                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1057
1058         return 0;
1059 }
1060
1061 /* STATUS register count is from 1-32 while our is 0-31 */
1062 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1063 {
1064         u32 val, enable_reg;
1065         int i;
1066
1067         val = p->dma_read(IRQSTATUS_L0, 0);
1068         if (val == 0) {
1069                 if (printk_ratelimit())
1070                         printk(KERN_WARNING "Spurious DMA IRQ\n");
1071                 return IRQ_HANDLED;
1072         }
1073         enable_reg = p->dma_read(IRQENABLE_L0, 0);
1074         val &= enable_reg; /* Dispatch only relevant interrupts */
1075         for (i = 0; i < dma_lch_count && val != 0; i++) {
1076                 if (val & 1)
1077                         omap2_dma_handle_ch(i);
1078                 val >>= 1;
1079         }
1080
1081         return IRQ_HANDLED;
1082 }
1083
1084 static struct irqaction omap24xx_dma_irq = {
1085         .name = "DMA",
1086         .handler = omap2_dma_irq_handler,
1087 };
1088
1089 #else
1090 static struct irqaction omap24xx_dma_irq;
1091 #endif
1092
1093 /*----------------------------------------------------------------------------*/
1094
1095 /*
1096  * Note that we are currently using only IRQENABLE_L0 and L1.
1097  * As the DSP may be using IRQENABLE_L2 and L3, let's not
1098  * touch those for now.
1099  */
1100 void omap_dma_global_context_save(void)
1101 {
1102         omap_dma_global_context.dma_irqenable_l0 =
1103                 p->dma_read(IRQENABLE_L0, 0);
1104         omap_dma_global_context.dma_irqenable_l1 =
1105                 p->dma_read(IRQENABLE_L1, 0);
1106         omap_dma_global_context.dma_ocp_sysconfig =
1107                 p->dma_read(OCP_SYSCONFIG, 0);
1108         omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
1109 }
1110
1111 void omap_dma_global_context_restore(void)
1112 {
1113         int ch;
1114
1115         p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
1116         p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
1117                 OCP_SYSCONFIG, 0);
1118         p->dma_write(omap_dma_global_context.dma_irqenable_l0,
1119                 IRQENABLE_L0, 0);
1120         p->dma_write(omap_dma_global_context.dma_irqenable_l1,
1121                 IRQENABLE_L1, 0);
1122
1123         if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
1124                 p->dma_write(0x3 , IRQSTATUS_L0, 0);
1125
1126         for (ch = 0; ch < dma_chan_count; ch++)
1127                 if (dma_chan[ch].dev_id != -1)
1128                         omap_clear_dma(ch);
1129 }
1130
1131 struct omap_system_dma_plat_info *omap_get_plat_info(void)
1132 {
1133         return p;
1134 }
1135 EXPORT_SYMBOL_GPL(omap_get_plat_info);
1136
1137 static int omap_system_dma_probe(struct platform_device *pdev)
1138 {
1139         int ch, ret = 0;
1140         int dma_irq;
1141         char irq_name[4];
1142         int irq_rel;
1143
1144         p = pdev->dev.platform_data;
1145         if (!p) {
1146                 dev_err(&pdev->dev,
1147                         "%s: System DMA initialized without platform data\n",
1148                         __func__);
1149                 return -EINVAL;
1150         }
1151
1152         d                       = p->dma_attr;
1153         errata                  = p->errata;
1154
1155         if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
1156                         && (omap_dma_reserve_channels < d->lch_count))
1157                 d->lch_count    = omap_dma_reserve_channels;
1158
1159         dma_lch_count           = d->lch_count;
1160         dma_chan_count          = dma_lch_count;
1161         enable_1510_mode        = d->dev_caps & ENABLE_1510_MODE;
1162
1163         dma_chan = devm_kcalloc(&pdev->dev, dma_lch_count,
1164                                 sizeof(*dma_chan), GFP_KERNEL);
1165         if (!dma_chan)
1166                 return -ENOMEM;
1167
1168         if (dma_omap2plus()) {
1169                 dma_linked_lch = kcalloc(dma_lch_count,
1170                                          sizeof(*dma_linked_lch),
1171                                          GFP_KERNEL);
1172                 if (!dma_linked_lch) {
1173                         ret = -ENOMEM;
1174                         goto exit_dma_lch_fail;
1175                 }
1176         }
1177
1178         spin_lock_init(&dma_chan_lock);
1179         for (ch = 0; ch < dma_chan_count; ch++) {
1180                 omap_clear_dma(ch);
1181                 if (dma_omap2plus())
1182                         omap2_disable_irq_lch(ch);
1183
1184                 dma_chan[ch].dev_id = -1;
1185                 dma_chan[ch].next_lch = -1;
1186
1187                 if (ch >= 6 && enable_1510_mode)
1188                         continue;
1189
1190                 if (dma_omap1()) {
1191                         /*
1192                          * request_irq() doesn't like dev_id (ie. ch) being
1193                          * zero, so we have to kludge around this.
1194                          */
1195                         sprintf(&irq_name[0], "%d", ch);
1196                         dma_irq = platform_get_irq_byname(pdev, irq_name);
1197
1198                         if (dma_irq < 0) {
1199                                 ret = dma_irq;
1200                                 goto exit_dma_irq_fail;
1201                         }
1202
1203                         /* INT_DMA_LCD is handled in lcd_dma.c */
1204                         if (dma_irq == INT_DMA_LCD)
1205                                 continue;
1206
1207                         ret = request_irq(dma_irq,
1208                                         omap1_dma_irq_handler, 0, "DMA",
1209                                         (void *) (ch + 1));
1210                         if (ret != 0)
1211                                 goto exit_dma_irq_fail;
1212                 }
1213         }
1214
1215         if (d->dev_caps & IS_RW_PRIORITY)
1216                 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
1217                                 DMA_DEFAULT_FIFO_DEPTH, 0);
1218
1219         if (dma_omap2plus() && !(d->dev_caps & DMA_ENGINE_HANDLE_IRQ)) {
1220                 strcpy(irq_name, "0");
1221                 dma_irq = platform_get_irq_byname(pdev, irq_name);
1222                 if (dma_irq < 0) {
1223                         dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
1224                         ret = dma_irq;
1225                         goto exit_dma_lch_fail;
1226                 }
1227                 ret = setup_irq(dma_irq, &omap24xx_dma_irq);
1228                 if (ret) {
1229                         dev_err(&pdev->dev, "set_up failed for IRQ %d for DMA (error %d)\n",
1230                                 dma_irq, ret);
1231                         goto exit_dma_lch_fail;
1232                 }
1233         }
1234
1235         /* reserve dma channels 0 and 1 in high security devices on 34xx */
1236         if (d->dev_caps & HS_CHANNELS_RESERVED) {
1237                 pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n");
1238                 dma_chan[0].dev_id = 0;
1239                 dma_chan[1].dev_id = 1;
1240         }
1241         p->show_dma_caps();
1242         return 0;
1243
1244 exit_dma_irq_fail:
1245         dev_err(&pdev->dev, "unable to request IRQ %d for DMA (error %d)\n",
1246                 dma_irq, ret);
1247         for (irq_rel = 0; irq_rel < ch; irq_rel++) {
1248                 dma_irq = platform_get_irq(pdev, irq_rel);
1249                 free_irq(dma_irq, (void *)(irq_rel + 1));
1250         }
1251
1252 exit_dma_lch_fail:
1253         return ret;
1254 }
1255
1256 static int omap_system_dma_remove(struct platform_device *pdev)
1257 {
1258         int dma_irq;
1259
1260         if (dma_omap2plus()) {
1261                 char irq_name[4];
1262                 strcpy(irq_name, "0");
1263                 dma_irq = platform_get_irq_byname(pdev, irq_name);
1264                 if (dma_irq >= 0)
1265                         remove_irq(dma_irq, &omap24xx_dma_irq);
1266         } else {
1267                 int irq_rel = 0;
1268                 for ( ; irq_rel < dma_chan_count; irq_rel++) {
1269                         dma_irq = platform_get_irq(pdev, irq_rel);
1270                         free_irq(dma_irq, (void *)(irq_rel + 1));
1271                 }
1272         }
1273         return 0;
1274 }
1275
1276 static struct platform_driver omap_system_dma_driver = {
1277         .probe          = omap_system_dma_probe,
1278         .remove         = omap_system_dma_remove,
1279         .driver         = {
1280                 .name   = "omap_dma_system"
1281         },
1282 };
1283
1284 static int __init omap_system_dma_init(void)
1285 {
1286         return platform_driver_register(&omap_system_dma_driver);
1287 }
1288 arch_initcall(omap_system_dma_init);
1289
1290 static void __exit omap_system_dma_exit(void)
1291 {
1292         platform_driver_unregister(&omap_system_dma_driver);
1293 }
1294
1295 MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
1296 MODULE_LICENSE("GPL");
1297 MODULE_AUTHOR("Texas Instruments Inc");
1298
1299 /*
1300  * Reserve the omap SDMA channels using cmdline bootarg
1301  * "omap_dma_reserve_ch=". The valid range is 1 to 32
1302  */
1303 static int __init omap_dma_cmdline_reserve_ch(char *str)
1304 {
1305         if (get_option(&str, &omap_dma_reserve_channels) != 1)
1306                 omap_dma_reserve_channels = 0;
1307         return 1;
1308 }
1309
1310 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
1311
1312