1 // SPDX-License-Identifier: GPL-2.0-only
3 * platform device definitions for the iop3xx dma/xor engines
4 * Copyright © 2006, Intel Corporation.
6 #include <linux/platform_device.h>
7 #include <asm/hardware/iop3xx.h>
8 #include <linux/dma-mapping.h>
10 #include <asm/hardware/iop_adma.h>
12 #ifdef CONFIG_ARCH_IOP32X
13 #define IRQ_DMA0_EOT IRQ_IOP32X_DMA0_EOT
14 #define IRQ_DMA0_EOC IRQ_IOP32X_DMA0_EOC
15 #define IRQ_DMA0_ERR IRQ_IOP32X_DMA0_ERR
17 #define IRQ_DMA1_EOT IRQ_IOP32X_DMA1_EOT
18 #define IRQ_DMA1_EOC IRQ_IOP32X_DMA1_EOC
19 #define IRQ_DMA1_ERR IRQ_IOP32X_DMA1_ERR
21 #define IRQ_AA_EOT IRQ_IOP32X_AA_EOT
22 #define IRQ_AA_EOC IRQ_IOP32X_AA_EOC
23 #define IRQ_AA_ERR IRQ_IOP32X_AA_ERR
25 #ifdef CONFIG_ARCH_IOP33X
26 #define IRQ_DMA0_EOT IRQ_IOP33X_DMA0_EOT
27 #define IRQ_DMA0_EOC IRQ_IOP33X_DMA0_EOC
28 #define IRQ_DMA0_ERR IRQ_IOP33X_DMA0_ERR
30 #define IRQ_DMA1_EOT IRQ_IOP33X_DMA1_EOT
31 #define IRQ_DMA1_EOC IRQ_IOP33X_DMA1_EOC
32 #define IRQ_DMA1_ERR IRQ_IOP33X_DMA1_ERR
34 #define IRQ_AA_EOT IRQ_IOP33X_AA_EOT
35 #define IRQ_AA_EOC IRQ_IOP33X_AA_EOC
36 #define IRQ_AA_ERR IRQ_IOP33X_AA_ERR
38 /* AAU and DMA Channels */
39 static struct resource iop3xx_dma_0_resources[] = {
41 .start = IOP3XX_DMA_PHYS_BASE(0),
42 .end = IOP3XX_DMA_UPPER_PA(0),
43 .flags = IORESOURCE_MEM,
46 .start = IRQ_DMA0_EOT,
48 .flags = IORESOURCE_IRQ
51 .start = IRQ_DMA0_EOC,
53 .flags = IORESOURCE_IRQ
56 .start = IRQ_DMA0_ERR,
58 .flags = IORESOURCE_IRQ
62 static struct resource iop3xx_dma_1_resources[] = {
64 .start = IOP3XX_DMA_PHYS_BASE(1),
65 .end = IOP3XX_DMA_UPPER_PA(1),
66 .flags = IORESOURCE_MEM,
69 .start = IRQ_DMA1_EOT,
71 .flags = IORESOURCE_IRQ
74 .start = IRQ_DMA1_EOC,
76 .flags = IORESOURCE_IRQ
79 .start = IRQ_DMA1_ERR,
81 .flags = IORESOURCE_IRQ
86 static struct resource iop3xx_aau_resources[] = {
88 .start = IOP3XX_AAU_PHYS_BASE,
89 .end = IOP3XX_AAU_UPPER_PA,
90 .flags = IORESOURCE_MEM,
95 .flags = IORESOURCE_IRQ
100 .flags = IORESOURCE_IRQ
105 .flags = IORESOURCE_IRQ
109 static u64 iop3xx_adma_dmamask = DMA_BIT_MASK(32);
111 static struct iop_adma_platform_data iop3xx_dma_0_data = {
113 .pool_size = PAGE_SIZE,
116 static struct iop_adma_platform_data iop3xx_dma_1_data = {
118 .pool_size = PAGE_SIZE,
121 static struct iop_adma_platform_data iop3xx_aau_data = {
123 .pool_size = 3 * PAGE_SIZE,
126 struct platform_device iop3xx_dma_0_channel = {
130 .resource = iop3xx_dma_0_resources,
132 .dma_mask = &iop3xx_adma_dmamask,
133 .coherent_dma_mask = DMA_BIT_MASK(32),
134 .platform_data = (void *) &iop3xx_dma_0_data,
138 struct platform_device iop3xx_dma_1_channel = {
142 .resource = iop3xx_dma_1_resources,
144 .dma_mask = &iop3xx_adma_dmamask,
145 .coherent_dma_mask = DMA_BIT_MASK(32),
146 .platform_data = (void *) &iop3xx_dma_1_data,
150 struct platform_device iop3xx_aau_channel = {
154 .resource = iop3xx_aau_resources,
156 .dma_mask = &iop3xx_adma_dmamask,
157 .coherent_dma_mask = DMA_BIT_MASK(32),
158 .platform_data = (void *) &iop3xx_aau_data,
162 static int __init iop3xx_adma_cap_init(void)
164 #ifdef CONFIG_ARCH_IOP32X /* the 32x DMA does not perform CRC32C */
165 dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask);
166 dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask);
168 dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask);
169 dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask);
172 #ifdef CONFIG_ARCH_IOP32X /* the 32x DMA does not perform CRC32C */
173 dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask);
174 dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask);
176 dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask);
177 dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask);
180 #ifdef CONFIG_ARCH_IOP32X /* the 32x AAU does not perform zero sum */
181 dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask);
182 dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask);
184 dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask);
185 dma_cap_set(DMA_XOR_VAL, iop3xx_aau_data.cap_mask);
186 dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask);
192 arch_initcall(iop3xx_adma_cap_init);