1 /* SPDX-License-Identifier: GPL-2.0 */
3 * We need constants.h for:
8 #include <asm/asm-offsets.h>
9 #include <asm/thread_info.h>
16 * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
18 .macro vma_vm_mm, rd, rn
19 ldr \rd, [\rn, #VMA_VM_MM]
23 * vma_vm_flags - get vma->vm_flags
25 .macro vma_vm_flags, rd, rn
26 ldr \rd, [\rn, #VMA_VM_FLAGS]
30 * act_mm - get current->active_mm
34 .if (TSK_ACTIVE_MM > IMM12_MASK)
35 add \rd, \rd, #TSK_ACTIVE_MM & ~IMM12_MASK
37 ldr \rd, [\rd, #TSK_ACTIVE_MM & IMM12_MASK]
41 * mmid - get context id from mm pointer (mm->context.id)
42 * note, this field is 64bit, so in big-endian the two words are swapped too.
46 ldr \rd, [\rn, #MM_CONTEXT_ID + 4 ]
48 ldr \rd, [\rn, #MM_CONTEXT_ID]
53 * mask_asid - mask the ASID from the context ID
59 .macro crval, clear, mmuset, ucset
70 * dcache_line_size - get the minimum D-cache line size from the CTR register
73 .macro dcache_line_size, reg, tmp
75 movw \tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR
76 movt \tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR
79 mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
82 and \tmp, \tmp, #0xf @ cache line size encoding
83 mov \reg, #4 @ bytes per word
84 mov \reg, \reg, lsl \tmp @ actual cache line size
88 * icache_line_size - get the minimum I-cache line size from the CTR register
91 .macro icache_line_size, reg, tmp
93 movw \tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR
94 movt \tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR
97 mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
99 and \tmp, \tmp, #0xf @ cache line size encoding
100 mov \reg, #4 @ bytes per word
101 mov \reg, \reg, lsl \tmp @ actual cache line size
105 * Sanity check the PTE configuration for the code below - which makes
106 * certain assumptions about how these bits are laid out.
109 #if L_PTE_SHARED != PTE_EXT_SHARED
110 #error PTE shared bit mismatch
112 #if !defined (CONFIG_ARM_LPAE) && \
113 (L_PTE_XN+L_PTE_USER+L_PTE_RDONLY+L_PTE_DIRTY+L_PTE_YOUNG+\
114 L_PTE_PRESENT) > L_PTE_SHARED
115 #error Invalid Linux PTE bit settings
117 #endif /* CONFIG_MMU */
120 * The ARMv6 and ARMv7 set_pte_ext translation function.
122 * Permission translation:
123 * YUWD APX AP1 AP0 SVC User
124 * 0xxx 0 0 0 no acc no acc
125 * 100x 1 0 1 r/o no acc
126 * 10x0 1 0 1 r/o no acc
127 * 1011 0 0 1 r/w no acc
132 .macro armv6_mt_table pfx
134 .long 0x00 @ L_PTE_MT_UNCACHED
135 .long PTE_EXT_TEX(1) @ L_PTE_MT_BUFFERABLE
136 .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
137 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
138 .long PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
140 .long 0x00 @ L_PTE_MT_MINICACHE (not present)
141 .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
143 .long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC
145 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
146 .long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
149 .long PTE_CACHEABLE | PTE_BUFFERABLE | PTE_EXT_APX @ L_PTE_MT_VECTORS
152 .macro armv6_set_pte_ext pfx
153 str r1, [r0], #2048 @ linux version
155 bic r3, r1, #0x000003fc
156 bic r3, r3, #PTE_TYPE_MASK
158 orr r3, r3, #PTE_EXT_AP0 | 2
160 adr ip, \pfx\()_mt_table
161 and r2, r1, #L_PTE_MT_MASK
164 eor r1, r1, #L_PTE_DIRTY
165 tst r1, #L_PTE_DIRTY|L_PTE_RDONLY
166 orrne r3, r3, #PTE_EXT_APX
169 orrne r3, r3, #PTE_EXT_AP1
170 tstne r3, #PTE_EXT_APX
172 @ user read-only -> kernel read-only
173 bicne r3, r3, #PTE_EXT_AP0
176 orrne r3, r3, #PTE_EXT_XN
181 tstne r1, #L_PTE_PRESENT
183 tstne r1, #L_PTE_NONE
187 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
192 * The ARMv3, ARMv4 and ARMv5 set_pte_ext translation function,
193 * covering most CPUs except Xscale and Xscale 3.
195 * Permission translation:
197 * 0xxx 0x00 no acc no acc
198 * 100x 0x00 r/o no acc
199 * 10x0 0x00 r/o no acc
200 * 1011 0x55 r/w no acc
205 .macro armv3_set_pte_ext wc_disable=1
206 str r1, [r0], #2048 @ linux version
208 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY
210 bic r2, r1, #PTE_SMALL_AP_MASK @ keep C, B bits
211 bic r2, r2, #PTE_TYPE_MASK
212 orr r2, r2, #PTE_TYPE_SMALL
214 tst r3, #L_PTE_USER @ user?
215 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
217 tst r3, #L_PTE_RDONLY | L_PTE_DIRTY @ write and dirty?
218 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
220 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ present and young?
224 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
225 tst r2, #PTE_CACHEABLE
226 bicne r2, r2, #PTE_BUFFERABLE
229 str r2, [r0] @ hardware version
234 * Xscale set_pte_ext translation, split into two halves to cope
235 * with work-arounds. r3 must be preserved by code between these
238 * Permission translation:
240 * 0xxx 00 no acc no acc
248 .macro xscale_set_pte_ext_prologue
249 str r1, [r0] @ linux version
251 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY
253 bic r2, r1, #PTE_SMALL_AP_MASK @ keep C, B bits
254 orr r2, r2, #PTE_TYPE_EXT @ extended page
256 tst r3, #L_PTE_USER @ user?
257 orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
259 tst r3, #L_PTE_RDONLY | L_PTE_DIRTY @ write and dirty?
260 orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
261 @ combined with user -> user r/w
264 .macro xscale_set_pte_ext_epilogue
265 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ present and young?
266 movne r2, #0 @ no -> fault
268 str r2, [r0, #2048]! @ hardware version
270 mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
271 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
274 .macro define_processor_functions name:req, dabort:req, pabort:req, nommu=0, suspend=0, bugs=0
276 * If we are building for big.Little with branch predictor hardening,
277 * we need the processor function tables to remain available after boot.
279 #if defined(CONFIG_BIG_LITTLE) && defined(CONFIG_HARDEN_BRANCH_PREDICTOR)
282 .type \name\()_processor_functions, #object
284 ENTRY(\name\()_processor_functions)
287 .word cpu_\name\()_proc_init
289 .word cpu_\name\()_proc_fin
290 .word cpu_\name\()_reset
291 .word cpu_\name\()_do_idle
292 .word cpu_\name\()_dcache_clean_area
293 .word cpu_\name\()_switch_mm
298 .word cpu_\name\()_set_pte_ext
302 .word cpu_\name\()_suspend_size
303 #ifdef CONFIG_ARM_CPU_SUSPEND
304 .word cpu_\name\()_do_suspend
305 .word cpu_\name\()_do_resume
316 .size \name\()_processor_functions, . - \name\()_processor_functions
317 #if defined(CONFIG_BIG_LITTLE) && defined(CONFIG_HARDEN_BRANCH_PREDICTOR)
322 .macro define_cache_functions name:req
324 .type \name\()_cache_fns, #object
325 ENTRY(\name\()_cache_fns)
326 .long \name\()_flush_icache_all
327 .long \name\()_flush_kern_cache_all
328 .long \name\()_flush_kern_cache_louis
329 .long \name\()_flush_user_cache_all
330 .long \name\()_flush_user_cache_range
331 .long \name\()_coherent_kern_range
332 .long \name\()_coherent_user_range
333 .long \name\()_flush_kern_dcache_area
334 .long \name\()_dma_map_area
335 .long \name\()_dma_unmap_area
336 .long \name\()_dma_flush_range
337 .size \name\()_cache_fns, . - \name\()_cache_fns
340 .macro define_tlb_functions name:req, flags_up:req, flags_smp
341 .type \name\()_tlb_fns, #object
343 ENTRY(\name\()_tlb_fns)
344 .long \name\()_flush_user_tlb_range
345 .long \name\()_flush_kern_tlb_range
347 ALT_SMP(.long \flags_smp )
348 ALT_UP(.long \flags_up )
352 .size \name\()_tlb_fns, . - \name\()_tlb_fns
355 .macro globl_equ x, y
360 .macro initfn, func, base
365 * Macro to calculate the log2 size for the protection region
366 * registers. This calculates rd = log2(size) - 1. tmp must
367 * not be the same register as rd.
369 .macro pr_sz, rd, size, tmp
370 mov \tmp, \size, lsr #12
372 1: movs \tmp, \tmp, lsr #1
378 * Macro to generate a protection region register value
379 * given a pre-masked address, size, and enable bit.
382 .macro pr_val, dest, addr, size, enable
383 pr_sz \dest, \size, \size @ calculate log2(size) - 1
384 orr \dest, \addr, \dest, lsl #1 @ mask in the region size
385 orr \dest, \dest, \enable