1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mm/mmu.c
5 * Copyright (C) 1995-2005 Russell King
7 #include <linux/module.h>
8 #include <linux/kernel.h>
9 #include <linux/errno.h>
10 #include <linux/init.h>
11 #include <linux/mman.h>
12 #include <linux/nodemask.h>
13 #include <linux/memblock.h>
15 #include <linux/vmalloc.h>
16 #include <linux/sizes.h>
19 #include <asm/cputype.h>
20 #include <asm/cachetype.h>
21 #include <asm/fixmap.h>
22 #include <asm/sections.h>
23 #include <asm/setup.h>
24 #include <asm/smp_plat.h>
26 #include <asm/highmem.h>
27 #include <asm/system_info.h>
28 #include <asm/traps.h>
29 #include <asm/procinfo.h>
30 #include <asm/memory.h>
31 #include <asm/pgalloc.h>
33 #include <asm/mach/arch.h>
34 #include <asm/mach/map.h>
35 #include <asm/mach/pci.h>
36 #include <asm/fixmap.h>
43 * empty_zero_page is a special page that is used for
44 * zero-initialized data and COW.
46 struct page *empty_zero_page;
47 EXPORT_SYMBOL(empty_zero_page);
50 * The pmd table for the upper-most set of pages.
54 pmdval_t user_pmd_table = _PAGE_USER_TABLE;
56 #define CPOLICY_UNCACHED 0
57 #define CPOLICY_BUFFERED 1
58 #define CPOLICY_WRITETHROUGH 2
59 #define CPOLICY_WRITEBACK 3
60 #define CPOLICY_WRITEALLOC 4
62 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
63 static unsigned int ecc_mask __initdata = 0;
65 pgprot_t pgprot_kernel;
67 EXPORT_SYMBOL(pgprot_user);
68 EXPORT_SYMBOL(pgprot_kernel);
71 const char policy[16];
77 static struct cachepolicy cache_policies[] __initdata = {
81 .pmd = PMD_SECT_UNCACHED,
82 .pte = L_PTE_MT_UNCACHED,
86 .pmd = PMD_SECT_BUFFERED,
87 .pte = L_PTE_MT_BUFFERABLE,
89 .policy = "writethrough",
92 .pte = L_PTE_MT_WRITETHROUGH,
94 .policy = "writeback",
97 .pte = L_PTE_MT_WRITEBACK,
99 .policy = "writealloc",
101 .pmd = PMD_SECT_WBWA,
102 .pte = L_PTE_MT_WRITEALLOC,
106 #ifdef CONFIG_CPU_CP15
107 static unsigned long initial_pmd_value __initdata = 0;
110 * Initialise the cache_policy variable with the initial state specified
111 * via the "pmd" value. This is used to ensure that on ARMv6 and later,
112 * the C code sets the page tables up with the same policy as the head
113 * assembly code, which avoids an illegal state where the TLBs can get
114 * confused. See comments in early_cachepolicy() for more information.
116 void __init init_default_cache_policy(unsigned long pmd)
120 initial_pmd_value = pmd;
122 pmd &= PMD_SECT_CACHE_MASK;
124 for (i = 0; i < ARRAY_SIZE(cache_policies); i++)
125 if (cache_policies[i].pmd == pmd) {
130 if (i == ARRAY_SIZE(cache_policies))
131 pr_err("ERROR: could not find cache policy\n");
135 * These are useful for identifying cache coherency problems by allowing
136 * the cache or the cache and writebuffer to be turned off. (Note: the
137 * write buffer should not be on and the cache off).
139 static int __init early_cachepolicy(char *p)
141 int i, selected = -1;
143 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
144 int len = strlen(cache_policies[i].policy);
146 if (memcmp(p, cache_policies[i].policy, len) == 0) {
153 pr_err("ERROR: unknown or unsupported cache policy\n");
156 * This restriction is partly to do with the way we boot; it is
157 * unpredictable to have memory mapped using two different sets of
158 * memory attributes (shared, type, and cache attribs). We can not
159 * change these attributes once the initial assembly has setup the
162 if (cpu_architecture() >= CPU_ARCH_ARMv6 && selected != cachepolicy) {
163 pr_warn("Only cachepolicy=%s supported on ARMv6 and later\n",
164 cache_policies[cachepolicy].policy);
168 if (selected != cachepolicy) {
169 unsigned long cr = __clear_cr(cache_policies[selected].cr_mask);
170 cachepolicy = selected;
176 early_param("cachepolicy", early_cachepolicy);
178 static int __init early_nocache(char *__unused)
180 char *p = "buffered";
181 pr_warn("nocache is deprecated; use cachepolicy=%s\n", p);
182 early_cachepolicy(p);
185 early_param("nocache", early_nocache);
187 static int __init early_nowrite(char *__unused)
189 char *p = "uncached";
190 pr_warn("nowb is deprecated; use cachepolicy=%s\n", p);
191 early_cachepolicy(p);
194 early_param("nowb", early_nowrite);
196 #ifndef CONFIG_ARM_LPAE
197 static int __init early_ecc(char *p)
199 if (memcmp(p, "on", 2) == 0)
200 ecc_mask = PMD_PROTECTION;
201 else if (memcmp(p, "off", 3) == 0)
205 early_param("ecc", early_ecc);
208 #else /* ifdef CONFIG_CPU_CP15 */
210 static int __init early_cachepolicy(char *p)
212 pr_warn("cachepolicy kernel parameter not supported without cp15\n");
214 early_param("cachepolicy", early_cachepolicy);
216 static int __init noalign_setup(char *__unused)
218 pr_warn("noalign kernel parameter not supported without cp15\n");
220 __setup("noalign", noalign_setup);
222 #endif /* ifdef CONFIG_CPU_CP15 / else */
224 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
225 #define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE
226 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
228 static struct mem_type mem_types[] __ro_after_init = {
229 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
230 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
232 .prot_l1 = PMD_TYPE_TABLE,
233 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
236 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
237 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
238 .prot_l1 = PMD_TYPE_TABLE,
239 .prot_sect = PROT_SECT_DEVICE,
242 [MT_DEVICE_CACHED] = { /* ioremap_cache */
243 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
244 .prot_l1 = PMD_TYPE_TABLE,
245 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
248 [MT_DEVICE_WC] = { /* ioremap_wc */
249 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
250 .prot_l1 = PMD_TYPE_TABLE,
251 .prot_sect = PROT_SECT_DEVICE,
255 .prot_pte = PROT_PTE_DEVICE,
256 .prot_l1 = PMD_TYPE_TABLE,
257 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
261 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
262 .domain = DOMAIN_KERNEL,
264 #ifndef CONFIG_ARM_LPAE
266 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
267 .domain = DOMAIN_KERNEL,
271 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
273 .prot_l1 = PMD_TYPE_TABLE,
274 .domain = DOMAIN_VECTORS,
276 [MT_HIGH_VECTORS] = {
277 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
278 L_PTE_USER | L_PTE_RDONLY,
279 .prot_l1 = PMD_TYPE_TABLE,
280 .domain = DOMAIN_VECTORS,
283 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
284 .prot_l1 = PMD_TYPE_TABLE,
285 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
286 .domain = DOMAIN_KERNEL,
289 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
291 .prot_l1 = PMD_TYPE_TABLE,
292 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
293 .domain = DOMAIN_KERNEL,
296 .prot_sect = PMD_TYPE_SECT,
297 .domain = DOMAIN_KERNEL,
299 [MT_MEMORY_RWX_NONCACHED] = {
300 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
302 .prot_l1 = PMD_TYPE_TABLE,
303 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
304 .domain = DOMAIN_KERNEL,
306 [MT_MEMORY_RW_DTCM] = {
307 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
309 .prot_l1 = PMD_TYPE_TABLE,
310 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
311 .domain = DOMAIN_KERNEL,
313 [MT_MEMORY_RWX_ITCM] = {
314 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
315 .prot_l1 = PMD_TYPE_TABLE,
316 .domain = DOMAIN_KERNEL,
318 [MT_MEMORY_RW_SO] = {
319 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
320 L_PTE_MT_UNCACHED | L_PTE_XN,
321 .prot_l1 = PMD_TYPE_TABLE,
322 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
323 PMD_SECT_UNCACHED | PMD_SECT_XN,
324 .domain = DOMAIN_KERNEL,
326 [MT_MEMORY_DMA_READY] = {
327 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
329 .prot_l1 = PMD_TYPE_TABLE,
330 .domain = DOMAIN_KERNEL,
334 const struct mem_type *get_mem_type(unsigned int type)
336 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
338 EXPORT_SYMBOL(get_mem_type);
340 static pte_t *(*pte_offset_fixmap)(pmd_t *dir, unsigned long addr);
342 static pte_t bm_pte[PTRS_PER_PTE + PTE_HWTABLE_PTRS]
343 __aligned(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE) __initdata;
345 static pte_t * __init pte_offset_early_fixmap(pmd_t *dir, unsigned long addr)
347 return &bm_pte[pte_index(addr)];
350 static pte_t *pte_offset_late_fixmap(pmd_t *dir, unsigned long addr)
352 return pte_offset_kernel(dir, addr);
355 static inline pmd_t * __init fixmap_pmd(unsigned long addr)
357 return pmd_off_k(addr);
360 void __init early_fixmap_init(void)
365 * The early fixmap range spans multiple pmds, for which
366 * we are not prepared:
368 BUILD_BUG_ON((__fix_to_virt(__end_of_early_ioremap_region) >> PMD_SHIFT)
369 != FIXADDR_TOP >> PMD_SHIFT);
371 pmd = fixmap_pmd(FIXADDR_TOP);
372 pmd_populate_kernel(&init_mm, pmd, bm_pte);
374 pte_offset_fixmap = pte_offset_early_fixmap;
378 * To avoid TLB flush broadcasts, this uses local_flush_tlb_kernel_range().
379 * As a result, this can only be called with preemption disabled, as under
382 void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot)
384 unsigned long vaddr = __fix_to_virt(idx);
385 pte_t *pte = pte_offset_fixmap(pmd_off_k(vaddr), vaddr);
387 /* Make sure fixmap region does not exceed available allocation. */
388 BUILD_BUG_ON(FIXADDR_START + (__end_of_fixed_addresses * PAGE_SIZE) >
390 BUG_ON(idx >= __end_of_fixed_addresses);
392 /* we only support device mappings until pgprot_kernel has been set */
393 if (WARN_ON(pgprot_val(prot) != pgprot_val(FIXMAP_PAGE_IO) &&
394 pgprot_val(pgprot_kernel) == 0))
397 if (pgprot_val(prot))
398 set_pte_at(NULL, vaddr, pte,
399 pfn_pte(phys >> PAGE_SHIFT, prot));
401 pte_clear(NULL, vaddr, pte);
402 local_flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE);
406 * Adjust the PMD section entries according to the CPU in use.
408 static void __init build_mem_type_table(void)
410 struct cachepolicy *cp;
411 unsigned int cr = get_cr();
412 pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
413 int cpu_arch = cpu_architecture();
416 if (cpu_arch < CPU_ARCH_ARMv6) {
417 #if defined(CONFIG_CPU_DCACHE_DISABLE)
418 if (cachepolicy > CPOLICY_BUFFERED)
419 cachepolicy = CPOLICY_BUFFERED;
420 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
421 if (cachepolicy > CPOLICY_WRITETHROUGH)
422 cachepolicy = CPOLICY_WRITETHROUGH;
425 if (cpu_arch < CPU_ARCH_ARMv5) {
426 if (cachepolicy >= CPOLICY_WRITEALLOC)
427 cachepolicy = CPOLICY_WRITEBACK;
432 if (cachepolicy != CPOLICY_WRITEALLOC) {
433 pr_warn("Forcing write-allocate cache policy for SMP\n");
434 cachepolicy = CPOLICY_WRITEALLOC;
436 if (!(initial_pmd_value & PMD_SECT_S)) {
437 pr_warn("Forcing shared mappings for SMP\n");
438 initial_pmd_value |= PMD_SECT_S;
443 * Strip out features not present on earlier architectures.
444 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
445 * without extended page tables don't have the 'Shared' bit.
447 if (cpu_arch < CPU_ARCH_ARMv5)
448 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
449 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
450 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
451 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
452 mem_types[i].prot_sect &= ~PMD_SECT_S;
455 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
456 * "update-able on write" bit on ARM610). However, Xscale and
457 * Xscale3 require this bit to be cleared.
459 if (cpu_is_xscale_family()) {
460 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
461 mem_types[i].prot_sect &= ~PMD_BIT4;
462 mem_types[i].prot_l1 &= ~PMD_BIT4;
464 } else if (cpu_arch < CPU_ARCH_ARMv6) {
465 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
466 if (mem_types[i].prot_l1)
467 mem_types[i].prot_l1 |= PMD_BIT4;
468 if (mem_types[i].prot_sect)
469 mem_types[i].prot_sect |= PMD_BIT4;
474 * Mark the device areas according to the CPU/architecture.
476 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
477 if (!cpu_is_xsc3()) {
479 * Mark device regions on ARMv6+ as execute-never
480 * to prevent speculative instruction fetches.
482 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
483 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
484 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
485 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
487 /* Also setup NX memory mapping */
488 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN;
490 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
492 * For ARMv7 with TEX remapping,
493 * - shared device is SXCB=1100
494 * - nonshared device is SXCB=0100
495 * - write combine device mem is SXCB=0001
496 * (Uncached Normal memory)
498 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
499 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
500 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
501 } else if (cpu_is_xsc3()) {
504 * - shared device is TEXCB=00101
505 * - nonshared device is TEXCB=01000
506 * - write combine device mem is TEXCB=00100
507 * (Inner/Outer Uncacheable in xsc3 parlance)
509 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
510 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
511 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
514 * For ARMv6 and ARMv7 without TEX remapping,
515 * - shared device is TEXCB=00001
516 * - nonshared device is TEXCB=01000
517 * - write combine device mem is TEXCB=00100
518 * (Uncached Normal in ARMv6 parlance).
520 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
521 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
522 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
526 * On others, write combining is "Uncached/Buffered"
528 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
532 * Now deal with the memory-type mappings
534 cp = &cache_policies[cachepolicy];
535 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
537 #ifndef CONFIG_ARM_LPAE
539 * We don't use domains on ARMv6 (since this causes problems with
540 * v6/v7 kernels), so we must use a separate memory type for user
541 * r/o, kernel r/w to map the vectors page.
543 if (cpu_arch == CPU_ARCH_ARMv6)
544 vecs_pgprot |= L_PTE_MT_VECTORS;
547 * Check is it with support for the PXN bit
548 * in the Short-descriptor translation table format descriptors.
550 if (cpu_arch == CPU_ARCH_ARMv7 &&
551 (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xF) >= 4) {
552 user_pmd_table |= PMD_PXNTABLE;
557 * ARMv6 and above have extended page tables.
559 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
560 #ifndef CONFIG_ARM_LPAE
562 * Mark cache clean areas and XIP ROM read only
563 * from SVC mode and no access from userspace.
565 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
566 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
567 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
571 * If the initial page tables were created with the S bit
572 * set, then we need to do the same here for the same
573 * reasons given in early_cachepolicy().
575 if (initial_pmd_value & PMD_SECT_S) {
576 user_pgprot |= L_PTE_SHARED;
577 kern_pgprot |= L_PTE_SHARED;
578 vecs_pgprot |= L_PTE_SHARED;
579 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
580 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
581 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
582 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
583 mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S;
584 mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED;
585 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S;
586 mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED;
587 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
588 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S;
589 mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED;
594 * Non-cacheable Normal - intended for memory areas that must
595 * not cause dirty cache line writebacks when used
597 if (cpu_arch >= CPU_ARCH_ARMv6) {
598 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
599 /* Non-cacheable Normal is XCB = 001 */
600 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
603 /* For both ARMv6 and non-TEX-remapping ARMv7 */
604 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
608 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
611 #ifdef CONFIG_ARM_LPAE
613 * Do not generate access flag faults for the kernel mappings.
615 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
616 mem_types[i].prot_pte |= PTE_EXT_AF;
617 if (mem_types[i].prot_sect)
618 mem_types[i].prot_sect |= PMD_SECT_AF;
620 kern_pgprot |= PTE_EXT_AF;
621 vecs_pgprot |= PTE_EXT_AF;
624 * Set PXN for user mappings
626 user_pgprot |= PTE_EXT_PXN;
629 for (i = 0; i < 16; i++) {
630 pteval_t v = pgprot_val(protection_map[i]);
631 protection_map[i] = __pgprot(v | user_pgprot);
634 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
635 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
637 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
638 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
639 L_PTE_DIRTY | kern_pgprot);
641 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
642 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
643 mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd;
644 mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
645 mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
646 mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
647 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
648 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
649 mem_types[MT_ROM].prot_sect |= cp->pmd;
653 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
657 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
660 pr_info("Memory policy: %sData cache %s\n",
661 ecc_mask ? "ECC enabled, " : "", cp->policy);
663 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
664 struct mem_type *t = &mem_types[i];
666 t->prot_l1 |= PMD_DOMAIN(t->domain);
668 t->prot_sect |= PMD_DOMAIN(t->domain);
672 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
673 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
674 unsigned long size, pgprot_t vma_prot)
677 return pgprot_noncached(vma_prot);
678 else if (file->f_flags & O_SYNC)
679 return pgprot_writecombine(vma_prot);
682 EXPORT_SYMBOL(phys_mem_access_prot);
685 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
687 static void __init *early_alloc(unsigned long sz)
689 void *ptr = memblock_alloc(sz, sz);
692 panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
698 static void *__init late_alloc(unsigned long sz)
700 void *ptr = (void *)__get_free_pages(GFP_PGTABLE_KERNEL, get_order(sz));
702 if (!ptr || !pgtable_pte_page_ctor(virt_to_page(ptr)))
707 static pte_t * __init arm_pte_alloc(pmd_t *pmd, unsigned long addr,
709 void *(*alloc)(unsigned long sz))
711 if (pmd_none(*pmd)) {
712 pte_t *pte = alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
713 __pmd_populate(pmd, __pa(pte), prot);
715 BUG_ON(pmd_bad(*pmd));
716 return pte_offset_kernel(pmd, addr);
719 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr,
722 return arm_pte_alloc(pmd, addr, prot, early_alloc);
725 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
726 unsigned long end, unsigned long pfn,
727 const struct mem_type *type,
728 void *(*alloc)(unsigned long sz),
731 pte_t *pte = arm_pte_alloc(pmd, addr, type->prot_l1, alloc);
733 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)),
734 ng ? PTE_EXT_NG : 0);
736 } while (pte++, addr += PAGE_SIZE, addr != end);
739 static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
740 unsigned long end, phys_addr_t phys,
741 const struct mem_type *type, bool ng)
745 #ifndef CONFIG_ARM_LPAE
747 * In classic MMU format, puds and pmds are folded in to
748 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
749 * group of L1 entries making up one logical pointer to
750 * an L2 table (2MB), where as PMDs refer to the individual
751 * L1 entries (1MB). Hence increment to get the correct
752 * offset for odd 1MB sections.
753 * (See arch/arm/include/asm/pgtable-2level.h)
755 if (addr & SECTION_SIZE)
759 *pmd = __pmd(phys | type->prot_sect | (ng ? PMD_SECT_nG : 0));
760 phys += SECTION_SIZE;
761 } while (pmd++, addr += SECTION_SIZE, addr != end);
766 static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
767 unsigned long end, phys_addr_t phys,
768 const struct mem_type *type,
769 void *(*alloc)(unsigned long sz), bool ng)
771 pmd_t *pmd = pmd_offset(pud, addr);
776 * With LPAE, we must loop over to map
777 * all the pmds for the given range.
779 next = pmd_addr_end(addr, end);
782 * Try a section mapping - addr, next and phys must all be
783 * aligned to a section boundary.
785 if (type->prot_sect &&
786 ((addr | next | phys) & ~SECTION_MASK) == 0) {
787 __map_init_section(pmd, addr, next, phys, type, ng);
789 alloc_init_pte(pmd, addr, next,
790 __phys_to_pfn(phys), type, alloc, ng);
795 } while (pmd++, addr = next, addr != end);
798 static void __init alloc_init_pud(p4d_t *p4d, unsigned long addr,
799 unsigned long end, phys_addr_t phys,
800 const struct mem_type *type,
801 void *(*alloc)(unsigned long sz), bool ng)
803 pud_t *pud = pud_offset(p4d, addr);
807 next = pud_addr_end(addr, end);
808 alloc_init_pmd(pud, addr, next, phys, type, alloc, ng);
810 } while (pud++, addr = next, addr != end);
813 static void __init alloc_init_p4d(pgd_t *pgd, unsigned long addr,
814 unsigned long end, phys_addr_t phys,
815 const struct mem_type *type,
816 void *(*alloc)(unsigned long sz), bool ng)
818 p4d_t *p4d = p4d_offset(pgd, addr);
822 next = p4d_addr_end(addr, end);
823 alloc_init_pud(p4d, addr, next, phys, type, alloc, ng);
825 } while (p4d++, addr = next, addr != end);
828 #ifndef CONFIG_ARM_LPAE
829 static void __init create_36bit_mapping(struct mm_struct *mm,
831 const struct mem_type *type,
834 unsigned long addr, length, end;
839 phys = __pfn_to_phys(md->pfn);
840 length = PAGE_ALIGN(md->length);
842 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
843 pr_err("MM: CPU does not support supersection mapping for 0x%08llx at 0x%08lx\n",
844 (long long)__pfn_to_phys((u64)md->pfn), addr);
848 /* N.B. ARMv6 supersections are only defined to work with domain 0.
849 * Since domain assignments can in fact be arbitrary, the
850 * 'domain == 0' check below is required to insure that ARMv6
851 * supersections are only allocated for domain 0 regardless
852 * of the actual domain assignments in use.
855 pr_err("MM: invalid domain in supersection mapping for 0x%08llx at 0x%08lx\n",
856 (long long)__pfn_to_phys((u64)md->pfn), addr);
860 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
861 pr_err("MM: cannot create mapping for 0x%08llx at 0x%08lx invalid alignment\n",
862 (long long)__pfn_to_phys((u64)md->pfn), addr);
867 * Shift bits [35:32] of address into bits [23:20] of PMD
870 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
872 pgd = pgd_offset(mm, addr);
875 p4d_t *p4d = p4d_offset(pgd, addr);
876 pud_t *pud = pud_offset(p4d, addr);
877 pmd_t *pmd = pmd_offset(pud, addr);
880 for (i = 0; i < 16; i++)
881 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER |
882 (ng ? PMD_SECT_nG : 0));
884 addr += SUPERSECTION_SIZE;
885 phys += SUPERSECTION_SIZE;
886 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
887 } while (addr != end);
889 #endif /* !CONFIG_ARM_LPAE */
891 static void __init __create_mapping(struct mm_struct *mm, struct map_desc *md,
892 void *(*alloc)(unsigned long sz),
895 unsigned long addr, length, end;
897 const struct mem_type *type;
900 type = &mem_types[md->type];
902 #ifndef CONFIG_ARM_LPAE
904 * Catch 36-bit addresses
906 if (md->pfn >= 0x100000) {
907 create_36bit_mapping(mm, md, type, ng);
912 addr = md->virtual & PAGE_MASK;
913 phys = __pfn_to_phys(md->pfn);
914 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
916 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
917 pr_warn("BUG: map for 0x%08llx at 0x%08lx can not be mapped using pages, ignoring.\n",
918 (long long)__pfn_to_phys(md->pfn), addr);
922 pgd = pgd_offset(mm, addr);
925 unsigned long next = pgd_addr_end(addr, end);
927 alloc_init_p4d(pgd, addr, next, phys, type, alloc, ng);
931 } while (pgd++, addr != end);
935 * Create the page directory entries and any necessary
936 * page tables for the mapping specified by `md'. We
937 * are able to cope here with varying sizes and address
938 * offsets, and we take full advantage of sections and
941 static void __init create_mapping(struct map_desc *md)
943 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
944 pr_warn("BUG: not creating mapping for 0x%08llx at 0x%08lx in user region\n",
945 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
949 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
950 md->virtual >= PAGE_OFFSET && md->virtual < FIXADDR_START &&
951 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
952 pr_warn("BUG: mapping for 0x%08llx at 0x%08lx out of vmalloc space\n",
953 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
956 __create_mapping(&init_mm, md, early_alloc, false);
959 void __init create_mapping_late(struct mm_struct *mm, struct map_desc *md,
962 #ifdef CONFIG_ARM_LPAE
966 p4d = p4d_alloc(mm, pgd_offset(mm, md->virtual), md->virtual);
969 pud = pud_alloc(mm, p4d, md->virtual);
972 pmd_alloc(mm, pud, 0);
974 __create_mapping(mm, md, late_alloc, ng);
978 * Create the architecture specific mappings
980 void __init iotable_init(struct map_desc *io_desc, int nr)
983 struct vm_struct *vm;
984 struct static_vm *svm;
989 svm = memblock_alloc(sizeof(*svm) * nr, __alignof__(*svm));
991 panic("%s: Failed to allocate %zu bytes align=0x%zx\n",
992 __func__, sizeof(*svm) * nr, __alignof__(*svm));
994 for (md = io_desc; nr; md++, nr--) {
998 vm->addr = (void *)(md->virtual & PAGE_MASK);
999 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
1000 vm->phys_addr = __pfn_to_phys(md->pfn);
1001 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
1002 vm->flags |= VM_ARM_MTYPE(md->type);
1003 vm->caller = iotable_init;
1004 add_static_vm_early(svm++);
1008 void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
1011 struct vm_struct *vm;
1012 struct static_vm *svm;
1014 svm = memblock_alloc(sizeof(*svm), __alignof__(*svm));
1016 panic("%s: Failed to allocate %zu bytes align=0x%zx\n",
1017 __func__, sizeof(*svm), __alignof__(*svm));
1020 vm->addr = (void *)addr;
1022 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
1023 vm->caller = caller;
1024 add_static_vm_early(svm);
1027 #ifndef CONFIG_ARM_LPAE
1030 * The Linux PMD is made of two consecutive section entries covering 2MB
1031 * (see definition in include/asm/pgtable-2level.h). However a call to
1032 * create_mapping() may optimize static mappings by using individual
1033 * 1MB section mappings. This leaves the actual PMD potentially half
1034 * initialized if the top or bottom section entry isn't used, leaving it
1035 * open to problems if a subsequent ioremap() or vmalloc() tries to use
1036 * the virtual space left free by that unused section entry.
1038 * Let's avoid the issue by inserting dummy vm entries covering the unused
1039 * PMD halves once the static mappings are in place.
1042 static void __init pmd_empty_section_gap(unsigned long addr)
1044 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
1047 static void __init fill_pmd_gaps(void)
1049 struct static_vm *svm;
1050 struct vm_struct *vm;
1051 unsigned long addr, next = 0;
1054 list_for_each_entry(svm, &static_vmlist, list) {
1056 addr = (unsigned long)vm->addr;
1061 * Check if this vm starts on an odd section boundary.
1062 * If so and the first section entry for this PMD is free
1063 * then we block the corresponding virtual address.
1065 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1066 pmd = pmd_off_k(addr);
1068 pmd_empty_section_gap(addr & PMD_MASK);
1072 * Then check if this vm ends on an odd section boundary.
1073 * If so and the second section entry for this PMD is empty
1074 * then we block the corresponding virtual address.
1077 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1078 pmd = pmd_off_k(addr) + 1;
1080 pmd_empty_section_gap(addr);
1083 /* no need to look at any vm entry until we hit the next PMD */
1084 next = (addr + PMD_SIZE - 1) & PMD_MASK;
1089 #define fill_pmd_gaps() do { } while (0)
1092 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
1093 static void __init pci_reserve_io(void)
1095 struct static_vm *svm;
1097 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
1101 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
1104 #define pci_reserve_io() do { } while (0)
1107 #ifdef CONFIG_DEBUG_LL
1108 void __init debug_ll_io_init(void)
1110 struct map_desc map;
1112 debug_ll_addr(&map.pfn, &map.virtual);
1113 if (!map.pfn || !map.virtual)
1115 map.pfn = __phys_to_pfn(map.pfn);
1116 map.virtual &= PAGE_MASK;
1117 map.length = PAGE_SIZE;
1118 map.type = MT_DEVICE;
1119 iotable_init(&map, 1);
1123 static void * __initdata vmalloc_min =
1124 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
1127 * vmalloc=size forces the vmalloc area to be exactly 'size'
1128 * bytes. This can be used to increase (or decrease) the vmalloc
1129 * area - the default is 240m.
1131 static int __init early_vmalloc(char *arg)
1133 unsigned long vmalloc_reserve = memparse(arg, NULL);
1135 if (vmalloc_reserve < SZ_16M) {
1136 vmalloc_reserve = SZ_16M;
1137 pr_warn("vmalloc area too small, limiting to %luMB\n",
1138 vmalloc_reserve >> 20);
1141 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
1142 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
1143 pr_warn("vmalloc area is too big, limiting to %luMB\n",
1144 vmalloc_reserve >> 20);
1147 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
1150 early_param("vmalloc", early_vmalloc);
1152 phys_addr_t arm_lowmem_limit __initdata = 0;
1154 void __init adjust_lowmem_bounds(void)
1156 phys_addr_t block_start, block_end, memblock_limit = 0;
1157 u64 vmalloc_limit, i;
1158 phys_addr_t lowmem_limit = 0;
1161 * Let's use our own (unoptimized) equivalent of __pa() that is
1162 * not affected by wrap-arounds when sizeof(phys_addr_t) == 4.
1163 * The result is used as the upper bound on physical memory address
1164 * and may itself be outside the valid range for which phys_addr_t
1165 * and therefore __pa() is defined.
1167 vmalloc_limit = (u64)(uintptr_t)vmalloc_min - PAGE_OFFSET + PHYS_OFFSET;
1170 * The first usable region must be PMD aligned. Mark its start
1171 * as MEMBLOCK_NOMAP if it isn't
1173 for_each_mem_range(i, &block_start, &block_end) {
1174 if (!IS_ALIGNED(block_start, PMD_SIZE)) {
1177 len = round_up(block_start, PMD_SIZE) - block_start;
1178 memblock_mark_nomap(block_start, len);
1183 for_each_mem_range(i, &block_start, &block_end) {
1184 if (block_start < vmalloc_limit) {
1185 if (block_end > lowmem_limit)
1187 * Compare as u64 to ensure vmalloc_limit does
1188 * not get truncated. block_end should always
1189 * fit in phys_addr_t so there should be no
1190 * issue with assignment.
1192 lowmem_limit = min_t(u64,
1197 * Find the first non-pmd-aligned page, and point
1198 * memblock_limit at it. This relies on rounding the
1199 * limit down to be pmd-aligned, which happens at the
1200 * end of this function.
1202 * With this algorithm, the start or end of almost any
1203 * bank can be non-pmd-aligned. The only exception is
1204 * that the start of the bank 0 must be section-
1205 * aligned, since otherwise memory would need to be
1206 * allocated when mapping the start of bank 0, which
1207 * occurs before any free memory is mapped.
1209 if (!memblock_limit) {
1210 if (!IS_ALIGNED(block_start, PMD_SIZE))
1211 memblock_limit = block_start;
1212 else if (!IS_ALIGNED(block_end, PMD_SIZE))
1213 memblock_limit = lowmem_limit;
1219 arm_lowmem_limit = lowmem_limit;
1221 high_memory = __va(arm_lowmem_limit - 1) + 1;
1223 if (!memblock_limit)
1224 memblock_limit = arm_lowmem_limit;
1227 * Round the memblock limit down to a pmd size. This
1228 * helps to ensure that we will allocate memory from the
1229 * last full pmd, which should be mapped.
1231 memblock_limit = round_down(memblock_limit, PMD_SIZE);
1233 if (!IS_ENABLED(CONFIG_HIGHMEM) || cache_is_vipt_aliasing()) {
1234 if (memblock_end_of_DRAM() > arm_lowmem_limit) {
1235 phys_addr_t end = memblock_end_of_DRAM();
1237 pr_notice("Ignoring RAM at %pa-%pa\n",
1238 &memblock_limit, &end);
1239 pr_notice("Consider using a HIGHMEM enabled kernel.\n");
1241 memblock_remove(memblock_limit, end - memblock_limit);
1245 memblock_set_current_limit(memblock_limit);
1248 static inline void prepare_page_table(void)
1254 * Clear out all the mappings below the kernel image.
1256 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1257 pmd_clear(pmd_off_k(addr));
1259 #ifdef CONFIG_XIP_KERNEL
1260 /* The XIP kernel is mapped in the module area -- skip over it */
1261 addr = ((unsigned long)_exiprom + PMD_SIZE - 1) & PMD_MASK;
1263 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1264 pmd_clear(pmd_off_k(addr));
1267 * Find the end of the first block of lowmem.
1269 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1270 if (end >= arm_lowmem_limit)
1271 end = arm_lowmem_limit;
1274 * Clear out all the kernel space mappings, except for the first
1275 * memory bank, up to the vmalloc region.
1277 for (addr = __phys_to_virt(end);
1278 addr < VMALLOC_START; addr += PMD_SIZE)
1279 pmd_clear(pmd_off_k(addr));
1282 #ifdef CONFIG_ARM_LPAE
1283 /* the first page is reserved for pgd */
1284 #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
1285 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1287 #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
1291 * Reserve the special regions of memory
1293 void __init arm_mm_memblock_reserve(void)
1296 * Reserve the page tables. These are already in use,
1297 * and can only be in node 0.
1299 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1301 #ifdef CONFIG_SA1111
1303 * Because of the SA1111 DMA bug, we want to preserve our
1304 * precious DMA-able memory...
1306 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1311 * Set up the device mappings. Since we clear out the page tables for all
1312 * mappings above VMALLOC_START, except early fixmap, we might remove debug
1313 * device mappings. This means earlycon can be used to debug this function
1314 * Any other function or debugging method which may touch any device _will_
1317 static void __init devicemaps_init(const struct machine_desc *mdesc)
1319 struct map_desc map;
1324 * Allocate the vector page early.
1326 vectors = early_alloc(PAGE_SIZE * 2);
1328 early_trap_init(vectors);
1331 * Clear page table except top pmd used by early fixmaps
1333 for (addr = VMALLOC_START; addr < (FIXADDR_TOP & PMD_MASK); addr += PMD_SIZE)
1334 pmd_clear(pmd_off_k(addr));
1337 * Map the kernel if it is XIP.
1338 * It is always first in the modulearea.
1340 #ifdef CONFIG_XIP_KERNEL
1341 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1342 map.virtual = MODULES_VADDR;
1343 map.length = ((unsigned long)_exiprom - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1345 create_mapping(&map);
1349 * Map the cache flushing regions.
1352 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1353 map.virtual = FLUSH_BASE;
1355 map.type = MT_CACHECLEAN;
1356 create_mapping(&map);
1358 #ifdef FLUSH_BASE_MINICACHE
1359 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1360 map.virtual = FLUSH_BASE_MINICACHE;
1362 map.type = MT_MINICLEAN;
1363 create_mapping(&map);
1367 * Create a mapping for the machine vectors at the high-vectors
1368 * location (0xffff0000). If we aren't using high-vectors, also
1369 * create a mapping at the low-vectors virtual address.
1371 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1372 map.virtual = 0xffff0000;
1373 map.length = PAGE_SIZE;
1374 #ifdef CONFIG_KUSER_HELPERS
1375 map.type = MT_HIGH_VECTORS;
1377 map.type = MT_LOW_VECTORS;
1379 create_mapping(&map);
1381 if (!vectors_high()) {
1383 map.length = PAGE_SIZE * 2;
1384 map.type = MT_LOW_VECTORS;
1385 create_mapping(&map);
1388 /* Now create a kernel read-only mapping */
1390 map.virtual = 0xffff0000 + PAGE_SIZE;
1391 map.length = PAGE_SIZE;
1392 map.type = MT_LOW_VECTORS;
1393 create_mapping(&map);
1396 * Ask the machine support to map in the statically mapped devices.
1404 /* Reserve fixed i/o space in VMALLOC region */
1408 * Finally flush the caches and tlb to ensure that we're in a
1409 * consistent state wrt the writebuffer. This also ensures that
1410 * any write-allocated cache lines in the vector page are written
1411 * back. After this point, we can start to touch devices again.
1413 local_flush_tlb_all();
1416 /* Enable asynchronous aborts */
1420 static void __init kmap_init(void)
1422 #ifdef CONFIG_HIGHMEM
1423 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1424 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1427 early_pte_alloc(pmd_off_k(FIXADDR_START), FIXADDR_START,
1428 _PAGE_KERNEL_TABLE);
1431 static void __init map_lowmem(void)
1433 phys_addr_t kernel_x_start = round_down(__pa(KERNEL_START), SECTION_SIZE);
1434 phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE);
1435 phys_addr_t start, end;
1438 /* Map all the lowmem memory banks. */
1439 for_each_mem_range(i, &start, &end) {
1440 struct map_desc map;
1442 if (end > arm_lowmem_limit)
1443 end = arm_lowmem_limit;
1447 if (end < kernel_x_start) {
1448 map.pfn = __phys_to_pfn(start);
1449 map.virtual = __phys_to_virt(start);
1450 map.length = end - start;
1451 map.type = MT_MEMORY_RWX;
1453 create_mapping(&map);
1454 } else if (start >= kernel_x_end) {
1455 map.pfn = __phys_to_pfn(start);
1456 map.virtual = __phys_to_virt(start);
1457 map.length = end - start;
1458 map.type = MT_MEMORY_RW;
1460 create_mapping(&map);
1462 /* This better cover the entire kernel */
1463 if (start < kernel_x_start) {
1464 map.pfn = __phys_to_pfn(start);
1465 map.virtual = __phys_to_virt(start);
1466 map.length = kernel_x_start - start;
1467 map.type = MT_MEMORY_RW;
1469 create_mapping(&map);
1472 map.pfn = __phys_to_pfn(kernel_x_start);
1473 map.virtual = __phys_to_virt(kernel_x_start);
1474 map.length = kernel_x_end - kernel_x_start;
1475 map.type = MT_MEMORY_RWX;
1477 create_mapping(&map);
1479 if (kernel_x_end < end) {
1480 map.pfn = __phys_to_pfn(kernel_x_end);
1481 map.virtual = __phys_to_virt(kernel_x_end);
1482 map.length = end - kernel_x_end;
1483 map.type = MT_MEMORY_RW;
1485 create_mapping(&map);
1491 #ifdef CONFIG_ARM_PV_FIXUP
1492 extern unsigned long __atags_pointer;
1493 typedef void pgtables_remap(long long offset, unsigned long pgd, void *bdata);
1494 pgtables_remap lpae_pgtables_remap_asm;
1497 * early_paging_init() recreates boot time page table setup, allowing machines
1498 * to switch over to a high (>4G) address space on LPAE systems
1500 static void __init early_paging_init(const struct machine_desc *mdesc)
1502 pgtables_remap *lpae_pgtables_remap;
1503 unsigned long pa_pgd;
1504 unsigned int cr, ttbcr;
1508 if (!mdesc->pv_fixup)
1511 offset = mdesc->pv_fixup();
1516 * Get the address of the remap function in the 1:1 identity
1517 * mapping setup by the early page table assembly code. We
1518 * must get this prior to the pv update. The following barrier
1519 * ensures that this is complete before we fixup any P:V offsets.
1521 lpae_pgtables_remap = (pgtables_remap *)(unsigned long)__pa(lpae_pgtables_remap_asm);
1522 pa_pgd = __pa(swapper_pg_dir);
1523 boot_data = __va(__atags_pointer);
1526 pr_info("Switching physical address space to 0x%08llx\n",
1527 (u64)PHYS_OFFSET + offset);
1529 /* Re-set the phys pfn offset, and the pv offset */
1530 __pv_offset += offset;
1531 __pv_phys_pfn_offset += PFN_DOWN(offset);
1533 /* Run the patch stub to update the constants */
1534 fixup_pv_table(&__pv_table_begin,
1535 (&__pv_table_end - &__pv_table_begin) << 2);
1538 * We changing not only the virtual to physical mapping, but also
1539 * the physical addresses used to access memory. We need to flush
1540 * all levels of cache in the system with caching disabled to
1541 * ensure that all data is written back, and nothing is prefetched
1542 * into the caches. We also need to prevent the TLB walkers
1543 * allocating into the caches too. Note that this is ARMv7 LPAE
1547 set_cr(cr & ~(CR_I | CR_C));
1548 asm("mrc p15, 0, %0, c2, c0, 2" : "=r" (ttbcr));
1549 asm volatile("mcr p15, 0, %0, c2, c0, 2"
1550 : : "r" (ttbcr & ~(3 << 8 | 3 << 10)));
1554 * Fixup the page tables - this must be in the idmap region as
1555 * we need to disable the MMU to do this safely, and hence it
1556 * needs to be assembly. It's fairly simple, as we're using the
1557 * temporary tables setup by the initial assembly code.
1559 lpae_pgtables_remap(offset, pa_pgd, boot_data);
1561 /* Re-enable the caches and cacheable TLB walks */
1562 asm volatile("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr));
1568 static void __init early_paging_init(const struct machine_desc *mdesc)
1572 if (!mdesc->pv_fixup)
1575 offset = mdesc->pv_fixup();
1579 pr_crit("Physical address space modification is only to support Keystone2.\n");
1580 pr_crit("Please enable ARM_LPAE and ARM_PATCH_PHYS_VIRT support to use this\n");
1581 pr_crit("feature. Your kernel may crash now, have a good day.\n");
1582 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1587 static void __init early_fixmap_shutdown(void)
1590 unsigned long va = fix_to_virt(__end_of_permanent_fixed_addresses - 1);
1592 pte_offset_fixmap = pte_offset_late_fixmap;
1593 pmd_clear(fixmap_pmd(va));
1594 local_flush_tlb_kernel_page(va);
1596 for (i = 0; i < __end_of_permanent_fixed_addresses; i++) {
1598 struct map_desc map;
1600 map.virtual = fix_to_virt(i);
1601 pte = pte_offset_early_fixmap(pmd_off_k(map.virtual), map.virtual);
1603 /* Only i/o device mappings are supported ATM */
1604 if (pte_none(*pte) ||
1605 (pte_val(*pte) & L_PTE_MT_MASK) != L_PTE_MT_DEV_SHARED)
1608 map.pfn = pte_pfn(*pte);
1609 map.type = MT_DEVICE;
1610 map.length = PAGE_SIZE;
1612 create_mapping(&map);
1617 * paging_init() sets up the page tables, initialises the zone memory
1618 * maps, and sets up the zero page, bad page and bad page tables.
1620 void __init paging_init(const struct machine_desc *mdesc)
1624 prepare_page_table();
1626 memblock_set_current_limit(arm_lowmem_limit);
1627 dma_contiguous_remap();
1628 early_fixmap_shutdown();
1629 devicemaps_init(mdesc);
1633 top_pmd = pmd_off_k(0xffff0000);
1635 /* allocate the zero page. */
1636 zero_page = early_alloc(PAGE_SIZE);
1640 empty_zero_page = virt_to_page(zero_page);
1641 __flush_dcache_page(NULL, empty_zero_page);
1644 void __init early_mm_init(const struct machine_desc *mdesc)
1646 build_mem_type_table();
1647 early_paging_init(mdesc);
1650 void set_pte_at(struct mm_struct *mm, unsigned long addr,
1651 pte_t *ptep, pte_t pteval)
1653 unsigned long ext = 0;
1655 if (addr < TASK_SIZE && pte_valid_user(pteval)) {
1656 if (!pte_special(pteval))
1657 __sync_icache_dcache(pteval);
1661 set_pte_ext(ptep, pteval, ext);