1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mm/mmu.c
5 * Copyright (C) 1995-2005 Russell King
7 #include <linux/module.h>
8 #include <linux/kernel.h>
9 #include <linux/errno.h>
10 #include <linux/init.h>
11 #include <linux/mman.h>
12 #include <linux/nodemask.h>
13 #include <linux/memblock.h>
15 #include <linux/vmalloc.h>
16 #include <linux/sizes.h>
19 #include <asm/cputype.h>
20 #include <asm/cachetype.h>
21 #include <asm/sections.h>
22 #include <asm/setup.h>
23 #include <asm/smp_plat.h>
25 #include <asm/highmem.h>
26 #include <asm/system_info.h>
27 #include <asm/traps.h>
28 #include <asm/procinfo.h>
29 #include <asm/memory.h>
30 #include <asm/pgalloc.h>
31 #include <asm/kasan_def.h>
33 #include <asm/mach/arch.h>
34 #include <asm/mach/map.h>
35 #include <asm/mach/pci.h>
36 #include <asm/fixmap.h>
42 extern unsigned long __atags_pointer;
45 * empty_zero_page is a special page that is used for
46 * zero-initialized data and COW.
48 struct page *empty_zero_page;
49 EXPORT_SYMBOL(empty_zero_page);
52 * The pmd table for the upper-most set of pages.
56 pmdval_t user_pmd_table = _PAGE_USER_TABLE;
58 #define CPOLICY_UNCACHED 0
59 #define CPOLICY_BUFFERED 1
60 #define CPOLICY_WRITETHROUGH 2
61 #define CPOLICY_WRITEBACK 3
62 #define CPOLICY_WRITEALLOC 4
64 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
65 static unsigned int ecc_mask __initdata = 0;
67 pgprot_t pgprot_kernel;
69 EXPORT_SYMBOL(pgprot_user);
70 EXPORT_SYMBOL(pgprot_kernel);
73 const char policy[16];
79 static struct cachepolicy cache_policies[] __initdata = {
83 .pmd = PMD_SECT_UNCACHED,
84 .pte = L_PTE_MT_UNCACHED,
88 .pmd = PMD_SECT_BUFFERED,
89 .pte = L_PTE_MT_BUFFERABLE,
91 .policy = "writethrough",
94 .pte = L_PTE_MT_WRITETHROUGH,
96 .policy = "writeback",
99 .pte = L_PTE_MT_WRITEBACK,
101 .policy = "writealloc",
103 .pmd = PMD_SECT_WBWA,
104 .pte = L_PTE_MT_WRITEALLOC,
108 #ifdef CONFIG_CPU_CP15
109 static unsigned long initial_pmd_value __initdata = 0;
112 * Initialise the cache_policy variable with the initial state specified
113 * via the "pmd" value. This is used to ensure that on ARMv6 and later,
114 * the C code sets the page tables up with the same policy as the head
115 * assembly code, which avoids an illegal state where the TLBs can get
116 * confused. See comments in early_cachepolicy() for more information.
118 void __init init_default_cache_policy(unsigned long pmd)
122 initial_pmd_value = pmd;
124 pmd &= PMD_SECT_CACHE_MASK;
126 for (i = 0; i < ARRAY_SIZE(cache_policies); i++)
127 if (cache_policies[i].pmd == pmd) {
132 if (i == ARRAY_SIZE(cache_policies))
133 pr_err("ERROR: could not find cache policy\n");
137 * These are useful for identifying cache coherency problems by allowing
138 * the cache or the cache and writebuffer to be turned off. (Note: the
139 * write buffer should not be on and the cache off).
141 static int __init early_cachepolicy(char *p)
143 int i, selected = -1;
145 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
146 int len = strlen(cache_policies[i].policy);
148 if (memcmp(p, cache_policies[i].policy, len) == 0) {
155 pr_err("ERROR: unknown or unsupported cache policy\n");
158 * This restriction is partly to do with the way we boot; it is
159 * unpredictable to have memory mapped using two different sets of
160 * memory attributes (shared, type, and cache attribs). We can not
161 * change these attributes once the initial assembly has setup the
164 if (cpu_architecture() >= CPU_ARCH_ARMv6 && selected != cachepolicy) {
165 pr_warn("Only cachepolicy=%s supported on ARMv6 and later\n",
166 cache_policies[cachepolicy].policy);
170 if (selected != cachepolicy) {
171 unsigned long cr = __clear_cr(cache_policies[selected].cr_mask);
172 cachepolicy = selected;
178 early_param("cachepolicy", early_cachepolicy);
180 static int __init early_nocache(char *__unused)
182 char *p = "buffered";
183 pr_warn("nocache is deprecated; use cachepolicy=%s\n", p);
184 early_cachepolicy(p);
187 early_param("nocache", early_nocache);
189 static int __init early_nowrite(char *__unused)
191 char *p = "uncached";
192 pr_warn("nowb is deprecated; use cachepolicy=%s\n", p);
193 early_cachepolicy(p);
196 early_param("nowb", early_nowrite);
198 #ifndef CONFIG_ARM_LPAE
199 static int __init early_ecc(char *p)
201 if (memcmp(p, "on", 2) == 0)
202 ecc_mask = PMD_PROTECTION;
203 else if (memcmp(p, "off", 3) == 0)
207 early_param("ecc", early_ecc);
210 #else /* ifdef CONFIG_CPU_CP15 */
212 static int __init early_cachepolicy(char *p)
214 pr_warn("cachepolicy kernel parameter not supported without cp15\n");
217 early_param("cachepolicy", early_cachepolicy);
219 static int __init noalign_setup(char *__unused)
221 pr_warn("noalign kernel parameter not supported without cp15\n");
224 __setup("noalign", noalign_setup);
226 #endif /* ifdef CONFIG_CPU_CP15 / else */
228 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
229 #define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE
230 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
232 static struct mem_type mem_types[] __ro_after_init = {
233 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
234 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
236 .prot_l1 = PMD_TYPE_TABLE,
237 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
240 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
241 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
242 .prot_l1 = PMD_TYPE_TABLE,
243 .prot_sect = PROT_SECT_DEVICE,
246 [MT_DEVICE_CACHED] = { /* ioremap_cache */
247 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
248 .prot_l1 = PMD_TYPE_TABLE,
249 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
252 [MT_DEVICE_WC] = { /* ioremap_wc */
253 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
254 .prot_l1 = PMD_TYPE_TABLE,
255 .prot_sect = PROT_SECT_DEVICE,
259 .prot_pte = PROT_PTE_DEVICE,
260 .prot_l1 = PMD_TYPE_TABLE,
261 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
265 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
266 .domain = DOMAIN_KERNEL,
268 #ifndef CONFIG_ARM_LPAE
270 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
271 .domain = DOMAIN_KERNEL,
275 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
277 .prot_l1 = PMD_TYPE_TABLE,
278 .domain = DOMAIN_VECTORS,
280 [MT_HIGH_VECTORS] = {
281 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
282 L_PTE_USER | L_PTE_RDONLY,
283 .prot_l1 = PMD_TYPE_TABLE,
284 .domain = DOMAIN_VECTORS,
287 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
288 .prot_l1 = PMD_TYPE_TABLE,
289 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
290 .domain = DOMAIN_KERNEL,
293 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
295 .prot_l1 = PMD_TYPE_TABLE,
296 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
297 .domain = DOMAIN_KERNEL,
300 .prot_sect = PMD_TYPE_SECT,
301 .domain = DOMAIN_KERNEL,
303 [MT_MEMORY_RWX_NONCACHED] = {
304 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
306 .prot_l1 = PMD_TYPE_TABLE,
307 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
308 .domain = DOMAIN_KERNEL,
310 [MT_MEMORY_RW_DTCM] = {
311 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
313 .prot_l1 = PMD_TYPE_TABLE,
314 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
315 .domain = DOMAIN_KERNEL,
317 [MT_MEMORY_RWX_ITCM] = {
318 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
319 .prot_l1 = PMD_TYPE_TABLE,
320 .domain = DOMAIN_KERNEL,
322 [MT_MEMORY_RW_SO] = {
323 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
324 L_PTE_MT_UNCACHED | L_PTE_XN,
325 .prot_l1 = PMD_TYPE_TABLE,
326 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
327 PMD_SECT_UNCACHED | PMD_SECT_XN,
328 .domain = DOMAIN_KERNEL,
330 [MT_MEMORY_DMA_READY] = {
331 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
333 .prot_l1 = PMD_TYPE_TABLE,
334 .domain = DOMAIN_KERNEL,
338 const struct mem_type *get_mem_type(unsigned int type)
340 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
342 EXPORT_SYMBOL(get_mem_type);
344 static pte_t *(*pte_offset_fixmap)(pmd_t *dir, unsigned long addr);
346 static pte_t bm_pte[PTRS_PER_PTE + PTE_HWTABLE_PTRS]
347 __aligned(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE) __initdata;
349 static pte_t * __init pte_offset_early_fixmap(pmd_t *dir, unsigned long addr)
351 return &bm_pte[pte_index(addr)];
354 static pte_t *pte_offset_late_fixmap(pmd_t *dir, unsigned long addr)
356 return pte_offset_kernel(dir, addr);
359 static inline pmd_t * __init fixmap_pmd(unsigned long addr)
361 return pmd_off_k(addr);
364 void __init early_fixmap_init(void)
369 * The early fixmap range spans multiple pmds, for which
370 * we are not prepared:
372 BUILD_BUG_ON((__fix_to_virt(__end_of_early_ioremap_region) >> PMD_SHIFT)
373 != FIXADDR_TOP >> PMD_SHIFT);
375 pmd = fixmap_pmd(FIXADDR_TOP);
376 pmd_populate_kernel(&init_mm, pmd, bm_pte);
378 pte_offset_fixmap = pte_offset_early_fixmap;
382 * To avoid TLB flush broadcasts, this uses local_flush_tlb_kernel_range().
383 * As a result, this can only be called with preemption disabled, as under
386 void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot)
388 unsigned long vaddr = __fix_to_virt(idx);
389 pte_t *pte = pte_offset_fixmap(pmd_off_k(vaddr), vaddr);
391 /* Make sure fixmap region does not exceed available allocation. */
392 BUILD_BUG_ON(__fix_to_virt(__end_of_fixed_addresses) < FIXADDR_START);
393 BUG_ON(idx >= __end_of_fixed_addresses);
395 /* We support only device mappings before pgprot_kernel is set. */
396 if (WARN_ON(pgprot_val(prot) != pgprot_val(FIXMAP_PAGE_IO) &&
397 pgprot_val(prot) && pgprot_val(pgprot_kernel) == 0))
400 if (pgprot_val(prot))
401 set_pte_at(NULL, vaddr, pte,
402 pfn_pte(phys >> PAGE_SHIFT, prot));
404 pte_clear(NULL, vaddr, pte);
405 local_flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE);
409 * Adjust the PMD section entries according to the CPU in use.
411 static void __init build_mem_type_table(void)
413 struct cachepolicy *cp;
414 unsigned int cr = get_cr();
415 pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
416 int cpu_arch = cpu_architecture();
419 if (cpu_arch < CPU_ARCH_ARMv6) {
420 #if defined(CONFIG_CPU_DCACHE_DISABLE)
421 if (cachepolicy > CPOLICY_BUFFERED)
422 cachepolicy = CPOLICY_BUFFERED;
423 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
424 if (cachepolicy > CPOLICY_WRITETHROUGH)
425 cachepolicy = CPOLICY_WRITETHROUGH;
428 if (cpu_arch < CPU_ARCH_ARMv5) {
429 if (cachepolicy >= CPOLICY_WRITEALLOC)
430 cachepolicy = CPOLICY_WRITEBACK;
435 if (cachepolicy != CPOLICY_WRITEALLOC) {
436 pr_warn("Forcing write-allocate cache policy for SMP\n");
437 cachepolicy = CPOLICY_WRITEALLOC;
439 if (!(initial_pmd_value & PMD_SECT_S)) {
440 pr_warn("Forcing shared mappings for SMP\n");
441 initial_pmd_value |= PMD_SECT_S;
446 * Strip out features not present on earlier architectures.
447 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
448 * without extended page tables don't have the 'Shared' bit.
450 if (cpu_arch < CPU_ARCH_ARMv5)
451 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
452 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
453 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
454 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
455 mem_types[i].prot_sect &= ~PMD_SECT_S;
458 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
459 * "update-able on write" bit on ARM610). However, Xscale and
460 * Xscale3 require this bit to be cleared.
462 if (cpu_is_xscale_family()) {
463 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
464 mem_types[i].prot_sect &= ~PMD_BIT4;
465 mem_types[i].prot_l1 &= ~PMD_BIT4;
467 } else if (cpu_arch < CPU_ARCH_ARMv6) {
468 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
469 if (mem_types[i].prot_l1)
470 mem_types[i].prot_l1 |= PMD_BIT4;
471 if (mem_types[i].prot_sect)
472 mem_types[i].prot_sect |= PMD_BIT4;
477 * Mark the device areas according to the CPU/architecture.
479 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
480 if (!cpu_is_xsc3()) {
482 * Mark device regions on ARMv6+ as execute-never
483 * to prevent speculative instruction fetches.
485 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
486 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
487 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
488 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
490 /* Also setup NX memory mapping */
491 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN;
493 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
495 * For ARMv7 with TEX remapping,
496 * - shared device is SXCB=1100
497 * - nonshared device is SXCB=0100
498 * - write combine device mem is SXCB=0001
499 * (Uncached Normal memory)
501 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
502 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
503 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
504 } else if (cpu_is_xsc3()) {
507 * - shared device is TEXCB=00101
508 * - nonshared device is TEXCB=01000
509 * - write combine device mem is TEXCB=00100
510 * (Inner/Outer Uncacheable in xsc3 parlance)
512 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
513 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
514 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
517 * For ARMv6 and ARMv7 without TEX remapping,
518 * - shared device is TEXCB=00001
519 * - nonshared device is TEXCB=01000
520 * - write combine device mem is TEXCB=00100
521 * (Uncached Normal in ARMv6 parlance).
523 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
524 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
525 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
529 * On others, write combining is "Uncached/Buffered"
531 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
535 * Now deal with the memory-type mappings
537 cp = &cache_policies[cachepolicy];
538 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
540 #ifndef CONFIG_ARM_LPAE
542 * We don't use domains on ARMv6 (since this causes problems with
543 * v6/v7 kernels), so we must use a separate memory type for user
544 * r/o, kernel r/w to map the vectors page.
546 if (cpu_arch == CPU_ARCH_ARMv6)
547 vecs_pgprot |= L_PTE_MT_VECTORS;
550 * Check is it with support for the PXN bit
551 * in the Short-descriptor translation table format descriptors.
553 if (cpu_arch == CPU_ARCH_ARMv7 &&
554 (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xF) >= 4) {
555 user_pmd_table |= PMD_PXNTABLE;
560 * ARMv6 and above have extended page tables.
562 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
563 #ifndef CONFIG_ARM_LPAE
565 * Mark cache clean areas and XIP ROM read only
566 * from SVC mode and no access from userspace.
568 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
569 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
570 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
574 * If the initial page tables were created with the S bit
575 * set, then we need to do the same here for the same
576 * reasons given in early_cachepolicy().
578 if (initial_pmd_value & PMD_SECT_S) {
579 user_pgprot |= L_PTE_SHARED;
580 kern_pgprot |= L_PTE_SHARED;
581 vecs_pgprot |= L_PTE_SHARED;
582 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
583 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
584 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
585 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
586 mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S;
587 mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED;
588 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S;
589 mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED;
590 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
591 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S;
592 mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED;
597 * Non-cacheable Normal - intended for memory areas that must
598 * not cause dirty cache line writebacks when used
600 if (cpu_arch >= CPU_ARCH_ARMv6) {
601 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
602 /* Non-cacheable Normal is XCB = 001 */
603 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
606 /* For both ARMv6 and non-TEX-remapping ARMv7 */
607 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
611 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
614 #ifdef CONFIG_ARM_LPAE
616 * Do not generate access flag faults for the kernel mappings.
618 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
619 mem_types[i].prot_pte |= PTE_EXT_AF;
620 if (mem_types[i].prot_sect)
621 mem_types[i].prot_sect |= PMD_SECT_AF;
623 kern_pgprot |= PTE_EXT_AF;
624 vecs_pgprot |= PTE_EXT_AF;
627 * Set PXN for user mappings
629 user_pgprot |= PTE_EXT_PXN;
632 for (i = 0; i < 16; i++) {
633 pteval_t v = pgprot_val(protection_map[i]);
634 protection_map[i] = __pgprot(v | user_pgprot);
637 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
638 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
640 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
641 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
642 L_PTE_DIRTY | kern_pgprot);
644 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
645 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
646 mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd;
647 mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
648 mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
649 mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
650 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
651 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
652 mem_types[MT_ROM].prot_sect |= cp->pmd;
656 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
660 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
663 pr_info("Memory policy: %sData cache %s\n",
664 ecc_mask ? "ECC enabled, " : "", cp->policy);
666 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
667 struct mem_type *t = &mem_types[i];
669 t->prot_l1 |= PMD_DOMAIN(t->domain);
671 t->prot_sect |= PMD_DOMAIN(t->domain);
675 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
676 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
677 unsigned long size, pgprot_t vma_prot)
680 return pgprot_noncached(vma_prot);
681 else if (file->f_flags & O_SYNC)
682 return pgprot_writecombine(vma_prot);
685 EXPORT_SYMBOL(phys_mem_access_prot);
688 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
690 static void __init *early_alloc(unsigned long sz)
692 void *ptr = memblock_alloc(sz, sz);
695 panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
701 static void *__init late_alloc(unsigned long sz)
703 void *ptr = (void *)__get_free_pages(GFP_PGTABLE_KERNEL, get_order(sz));
705 if (!ptr || !pgtable_pte_page_ctor(virt_to_page(ptr)))
710 static pte_t * __init arm_pte_alloc(pmd_t *pmd, unsigned long addr,
712 void *(*alloc)(unsigned long sz))
714 if (pmd_none(*pmd)) {
715 pte_t *pte = alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
716 __pmd_populate(pmd, __pa(pte), prot);
718 BUG_ON(pmd_bad(*pmd));
719 return pte_offset_kernel(pmd, addr);
722 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr,
725 return arm_pte_alloc(pmd, addr, prot, early_alloc);
728 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
729 unsigned long end, unsigned long pfn,
730 const struct mem_type *type,
731 void *(*alloc)(unsigned long sz),
734 pte_t *pte = arm_pte_alloc(pmd, addr, type->prot_l1, alloc);
736 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)),
737 ng ? PTE_EXT_NG : 0);
739 } while (pte++, addr += PAGE_SIZE, addr != end);
742 static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
743 unsigned long end, phys_addr_t phys,
744 const struct mem_type *type, bool ng)
748 #ifndef CONFIG_ARM_LPAE
750 * In classic MMU format, puds and pmds are folded in to
751 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
752 * group of L1 entries making up one logical pointer to
753 * an L2 table (2MB), where as PMDs refer to the individual
754 * L1 entries (1MB). Hence increment to get the correct
755 * offset for odd 1MB sections.
756 * (See arch/arm/include/asm/pgtable-2level.h)
758 if (addr & SECTION_SIZE)
762 *pmd = __pmd(phys | type->prot_sect | (ng ? PMD_SECT_nG : 0));
763 phys += SECTION_SIZE;
764 } while (pmd++, addr += SECTION_SIZE, addr != end);
769 static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
770 unsigned long end, phys_addr_t phys,
771 const struct mem_type *type,
772 void *(*alloc)(unsigned long sz), bool ng)
774 pmd_t *pmd = pmd_offset(pud, addr);
779 * With LPAE, we must loop over to map
780 * all the pmds for the given range.
782 next = pmd_addr_end(addr, end);
785 * Try a section mapping - addr, next and phys must all be
786 * aligned to a section boundary.
788 if (type->prot_sect &&
789 ((addr | next | phys) & ~SECTION_MASK) == 0) {
790 __map_init_section(pmd, addr, next, phys, type, ng);
792 alloc_init_pte(pmd, addr, next,
793 __phys_to_pfn(phys), type, alloc, ng);
798 } while (pmd++, addr = next, addr != end);
801 static void __init alloc_init_pud(p4d_t *p4d, unsigned long addr,
802 unsigned long end, phys_addr_t phys,
803 const struct mem_type *type,
804 void *(*alloc)(unsigned long sz), bool ng)
806 pud_t *pud = pud_offset(p4d, addr);
810 next = pud_addr_end(addr, end);
811 alloc_init_pmd(pud, addr, next, phys, type, alloc, ng);
813 } while (pud++, addr = next, addr != end);
816 static void __init alloc_init_p4d(pgd_t *pgd, unsigned long addr,
817 unsigned long end, phys_addr_t phys,
818 const struct mem_type *type,
819 void *(*alloc)(unsigned long sz), bool ng)
821 p4d_t *p4d = p4d_offset(pgd, addr);
825 next = p4d_addr_end(addr, end);
826 alloc_init_pud(p4d, addr, next, phys, type, alloc, ng);
828 } while (p4d++, addr = next, addr != end);
831 #ifndef CONFIG_ARM_LPAE
832 static void __init create_36bit_mapping(struct mm_struct *mm,
834 const struct mem_type *type,
837 unsigned long addr, length, end;
842 phys = __pfn_to_phys(md->pfn);
843 length = PAGE_ALIGN(md->length);
845 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
846 pr_err("MM: CPU does not support supersection mapping for 0x%08llx at 0x%08lx\n",
847 (long long)__pfn_to_phys((u64)md->pfn), addr);
851 /* N.B. ARMv6 supersections are only defined to work with domain 0.
852 * Since domain assignments can in fact be arbitrary, the
853 * 'domain == 0' check below is required to insure that ARMv6
854 * supersections are only allocated for domain 0 regardless
855 * of the actual domain assignments in use.
858 pr_err("MM: invalid domain in supersection mapping for 0x%08llx at 0x%08lx\n",
859 (long long)__pfn_to_phys((u64)md->pfn), addr);
863 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
864 pr_err("MM: cannot create mapping for 0x%08llx at 0x%08lx invalid alignment\n",
865 (long long)__pfn_to_phys((u64)md->pfn), addr);
870 * Shift bits [35:32] of address into bits [23:20] of PMD
873 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
875 pgd = pgd_offset(mm, addr);
878 p4d_t *p4d = p4d_offset(pgd, addr);
879 pud_t *pud = pud_offset(p4d, addr);
880 pmd_t *pmd = pmd_offset(pud, addr);
883 for (i = 0; i < 16; i++)
884 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER |
885 (ng ? PMD_SECT_nG : 0));
887 addr += SUPERSECTION_SIZE;
888 phys += SUPERSECTION_SIZE;
889 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
890 } while (addr != end);
892 #endif /* !CONFIG_ARM_LPAE */
894 static void __init __create_mapping(struct mm_struct *mm, struct map_desc *md,
895 void *(*alloc)(unsigned long sz),
898 unsigned long addr, length, end;
900 const struct mem_type *type;
903 type = &mem_types[md->type];
905 #ifndef CONFIG_ARM_LPAE
907 * Catch 36-bit addresses
909 if (md->pfn >= 0x100000) {
910 create_36bit_mapping(mm, md, type, ng);
915 addr = md->virtual & PAGE_MASK;
916 phys = __pfn_to_phys(md->pfn);
917 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
919 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
920 pr_warn("BUG: map for 0x%08llx at 0x%08lx can not be mapped using pages, ignoring.\n",
921 (long long)__pfn_to_phys(md->pfn), addr);
925 pgd = pgd_offset(mm, addr);
928 unsigned long next = pgd_addr_end(addr, end);
930 alloc_init_p4d(pgd, addr, next, phys, type, alloc, ng);
934 } while (pgd++, addr != end);
938 * Create the page directory entries and any necessary
939 * page tables for the mapping specified by `md'. We
940 * are able to cope here with varying sizes and address
941 * offsets, and we take full advantage of sections and
944 static void __init create_mapping(struct map_desc *md)
946 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
947 pr_warn("BUG: not creating mapping for 0x%08llx at 0x%08lx in user region\n",
948 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
952 if (md->type == MT_DEVICE &&
953 md->virtual >= PAGE_OFFSET && md->virtual < FIXADDR_START &&
954 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
955 pr_warn("BUG: mapping for 0x%08llx at 0x%08lx out of vmalloc space\n",
956 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
959 __create_mapping(&init_mm, md, early_alloc, false);
962 void __init create_mapping_late(struct mm_struct *mm, struct map_desc *md,
965 #ifdef CONFIG_ARM_LPAE
969 p4d = p4d_alloc(mm, pgd_offset(mm, md->virtual), md->virtual);
972 pud = pud_alloc(mm, p4d, md->virtual);
975 pmd_alloc(mm, pud, 0);
977 __create_mapping(mm, md, late_alloc, ng);
981 * Create the architecture specific mappings
983 void __init iotable_init(struct map_desc *io_desc, int nr)
986 struct vm_struct *vm;
987 struct static_vm *svm;
992 svm = memblock_alloc(sizeof(*svm) * nr, __alignof__(*svm));
994 panic("%s: Failed to allocate %zu bytes align=0x%zx\n",
995 __func__, sizeof(*svm) * nr, __alignof__(*svm));
997 for (md = io_desc; nr; md++, nr--) {
1001 vm->addr = (void *)(md->virtual & PAGE_MASK);
1002 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
1003 vm->phys_addr = __pfn_to_phys(md->pfn);
1004 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
1005 vm->flags |= VM_ARM_MTYPE(md->type);
1006 vm->caller = iotable_init;
1007 add_static_vm_early(svm++);
1011 void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
1014 struct vm_struct *vm;
1015 struct static_vm *svm;
1017 svm = memblock_alloc(sizeof(*svm), __alignof__(*svm));
1019 panic("%s: Failed to allocate %zu bytes align=0x%zx\n",
1020 __func__, sizeof(*svm), __alignof__(*svm));
1023 vm->addr = (void *)addr;
1025 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
1026 vm->caller = caller;
1027 add_static_vm_early(svm);
1030 #ifndef CONFIG_ARM_LPAE
1033 * The Linux PMD is made of two consecutive section entries covering 2MB
1034 * (see definition in include/asm/pgtable-2level.h). However a call to
1035 * create_mapping() may optimize static mappings by using individual
1036 * 1MB section mappings. This leaves the actual PMD potentially half
1037 * initialized if the top or bottom section entry isn't used, leaving it
1038 * open to problems if a subsequent ioremap() or vmalloc() tries to use
1039 * the virtual space left free by that unused section entry.
1041 * Let's avoid the issue by inserting dummy vm entries covering the unused
1042 * PMD halves once the static mappings are in place.
1045 static void __init pmd_empty_section_gap(unsigned long addr)
1047 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
1050 static void __init fill_pmd_gaps(void)
1052 struct static_vm *svm;
1053 struct vm_struct *vm;
1054 unsigned long addr, next = 0;
1057 list_for_each_entry(svm, &static_vmlist, list) {
1059 addr = (unsigned long)vm->addr;
1064 * Check if this vm starts on an odd section boundary.
1065 * If so and the first section entry for this PMD is free
1066 * then we block the corresponding virtual address.
1068 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1069 pmd = pmd_off_k(addr);
1071 pmd_empty_section_gap(addr & PMD_MASK);
1075 * Then check if this vm ends on an odd section boundary.
1076 * If so and the second section entry for this PMD is empty
1077 * then we block the corresponding virtual address.
1080 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1081 pmd = pmd_off_k(addr) + 1;
1083 pmd_empty_section_gap(addr);
1086 /* no need to look at any vm entry until we hit the next PMD */
1087 next = (addr + PMD_SIZE - 1) & PMD_MASK;
1092 #define fill_pmd_gaps() do { } while (0)
1095 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
1096 static void __init pci_reserve_io(void)
1098 struct static_vm *svm;
1100 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
1104 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
1107 #define pci_reserve_io() do { } while (0)
1110 #ifdef CONFIG_DEBUG_LL
1111 void __init debug_ll_io_init(void)
1113 struct map_desc map;
1115 debug_ll_addr(&map.pfn, &map.virtual);
1116 if (!map.pfn || !map.virtual)
1118 map.pfn = __phys_to_pfn(map.pfn);
1119 map.virtual &= PAGE_MASK;
1120 map.length = PAGE_SIZE;
1121 map.type = MT_DEVICE;
1122 iotable_init(&map, 1);
1126 static unsigned long __initdata vmalloc_size = 240 * SZ_1M;
1129 * vmalloc=size forces the vmalloc area to be exactly 'size'
1130 * bytes. This can be used to increase (or decrease) the vmalloc
1131 * area - the default is 240MiB.
1133 static int __init early_vmalloc(char *arg)
1135 unsigned long vmalloc_reserve = memparse(arg, NULL);
1136 unsigned long vmalloc_max;
1138 if (vmalloc_reserve < SZ_16M) {
1139 vmalloc_reserve = SZ_16M;
1140 pr_warn("vmalloc area is too small, limiting to %luMiB\n",
1141 vmalloc_reserve >> 20);
1144 vmalloc_max = VMALLOC_END - (PAGE_OFFSET + SZ_32M + VMALLOC_OFFSET);
1145 if (vmalloc_reserve > vmalloc_max) {
1146 vmalloc_reserve = vmalloc_max;
1147 pr_warn("vmalloc area is too big, limiting to %luMiB\n",
1148 vmalloc_reserve >> 20);
1151 vmalloc_size = vmalloc_reserve;
1154 early_param("vmalloc", early_vmalloc);
1156 phys_addr_t arm_lowmem_limit __initdata = 0;
1158 void __init adjust_lowmem_bounds(void)
1160 phys_addr_t block_start, block_end, memblock_limit = 0;
1161 u64 vmalloc_limit, i;
1162 phys_addr_t lowmem_limit = 0;
1165 * Let's use our own (unoptimized) equivalent of __pa() that is
1166 * not affected by wrap-arounds when sizeof(phys_addr_t) == 4.
1167 * The result is used as the upper bound on physical memory address
1168 * and may itself be outside the valid range for which phys_addr_t
1169 * and therefore __pa() is defined.
1171 vmalloc_limit = (u64)VMALLOC_END - vmalloc_size - VMALLOC_OFFSET -
1172 PAGE_OFFSET + PHYS_OFFSET;
1175 * The first usable region must be PMD aligned. Mark its start
1176 * as MEMBLOCK_NOMAP if it isn't
1178 for_each_mem_range(i, &block_start, &block_end) {
1179 if (!IS_ALIGNED(block_start, PMD_SIZE)) {
1182 len = round_up(block_start, PMD_SIZE) - block_start;
1183 memblock_mark_nomap(block_start, len);
1188 for_each_mem_range(i, &block_start, &block_end) {
1189 if (block_start < vmalloc_limit) {
1190 if (block_end > lowmem_limit)
1192 * Compare as u64 to ensure vmalloc_limit does
1193 * not get truncated. block_end should always
1194 * fit in phys_addr_t so there should be no
1195 * issue with assignment.
1197 lowmem_limit = min_t(u64,
1202 * Find the first non-pmd-aligned page, and point
1203 * memblock_limit at it. This relies on rounding the
1204 * limit down to be pmd-aligned, which happens at the
1205 * end of this function.
1207 * With this algorithm, the start or end of almost any
1208 * bank can be non-pmd-aligned. The only exception is
1209 * that the start of the bank 0 must be section-
1210 * aligned, since otherwise memory would need to be
1211 * allocated when mapping the start of bank 0, which
1212 * occurs before any free memory is mapped.
1214 if (!memblock_limit) {
1215 if (!IS_ALIGNED(block_start, PMD_SIZE))
1216 memblock_limit = block_start;
1217 else if (!IS_ALIGNED(block_end, PMD_SIZE))
1218 memblock_limit = lowmem_limit;
1224 arm_lowmem_limit = lowmem_limit;
1226 high_memory = __va(arm_lowmem_limit - 1) + 1;
1228 if (!memblock_limit)
1229 memblock_limit = arm_lowmem_limit;
1232 * Round the memblock limit down to a pmd size. This
1233 * helps to ensure that we will allocate memory from the
1234 * last full pmd, which should be mapped.
1236 memblock_limit = round_down(memblock_limit, PMD_SIZE);
1238 if (!IS_ENABLED(CONFIG_HIGHMEM) || cache_is_vipt_aliasing()) {
1239 if (memblock_end_of_DRAM() > arm_lowmem_limit) {
1240 phys_addr_t end = memblock_end_of_DRAM();
1242 pr_notice("Ignoring RAM at %pa-%pa\n",
1243 &memblock_limit, &end);
1244 pr_notice("Consider using a HIGHMEM enabled kernel.\n");
1246 memblock_remove(memblock_limit, end - memblock_limit);
1250 memblock_set_current_limit(memblock_limit);
1253 static __init void prepare_page_table(void)
1259 * Clear out all the mappings below the kernel image.
1263 * KASan's shadow memory inserts itself between the TASK_SIZE
1264 * and MODULES_VADDR. Do not clear the KASan shadow memory mappings.
1266 for (addr = 0; addr < KASAN_SHADOW_START; addr += PMD_SIZE)
1267 pmd_clear(pmd_off_k(addr));
1269 * Skip over the KASan shadow area. KASAN_SHADOW_END is sometimes
1270 * equal to MODULES_VADDR and then we exit the pmd clearing. If we
1271 * are using a thumb-compiled kernel, there there will be 8MB more
1272 * to clear as KASan always offset to 16 MB below MODULES_VADDR.
1274 for (addr = KASAN_SHADOW_END; addr < MODULES_VADDR; addr += PMD_SIZE)
1275 pmd_clear(pmd_off_k(addr));
1277 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1278 pmd_clear(pmd_off_k(addr));
1281 #ifdef CONFIG_XIP_KERNEL
1282 /* The XIP kernel is mapped in the module area -- skip over it */
1283 addr = ((unsigned long)_exiprom + PMD_SIZE - 1) & PMD_MASK;
1285 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1286 pmd_clear(pmd_off_k(addr));
1289 * Find the end of the first block of lowmem.
1291 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1292 if (end >= arm_lowmem_limit)
1293 end = arm_lowmem_limit;
1296 * Clear out all the kernel space mappings, except for the first
1297 * memory bank, up to the vmalloc region.
1299 for (addr = __phys_to_virt(end);
1300 addr < VMALLOC_START; addr += PMD_SIZE)
1301 pmd_clear(pmd_off_k(addr));
1304 #ifdef CONFIG_ARM_LPAE
1305 /* the first page is reserved for pgd */
1306 #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
1307 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1309 #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
1313 * Reserve the special regions of memory
1315 void __init arm_mm_memblock_reserve(void)
1318 * Reserve the page tables. These are already in use,
1319 * and can only be in node 0.
1321 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1323 #ifdef CONFIG_SA1111
1325 * Because of the SA1111 DMA bug, we want to preserve our
1326 * precious DMA-able memory...
1328 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1333 * Set up the device mappings. Since we clear out the page tables for all
1334 * mappings above VMALLOC_START, except early fixmap, we might remove debug
1335 * device mappings. This means earlycon can be used to debug this function
1336 * Any other function or debugging method which may touch any device _will_
1339 static void __init devicemaps_init(const struct machine_desc *mdesc)
1341 struct map_desc map;
1346 * Allocate the vector page early.
1348 vectors = early_alloc(PAGE_SIZE * 2);
1350 early_trap_init(vectors);
1353 * Clear page table except top pmd used by early fixmaps
1355 for (addr = VMALLOC_START; addr < (FIXADDR_TOP & PMD_MASK); addr += PMD_SIZE)
1356 pmd_clear(pmd_off_k(addr));
1358 if (__atags_pointer) {
1359 /* create a read-only mapping of the device tree */
1360 map.pfn = __phys_to_pfn(__atags_pointer & SECTION_MASK);
1361 map.virtual = FDT_FIXED_BASE;
1362 map.length = FDT_FIXED_SIZE;
1364 create_mapping(&map);
1368 * Map the kernel if it is XIP.
1369 * It is always first in the modulearea.
1371 #ifdef CONFIG_XIP_KERNEL
1372 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1373 map.virtual = MODULES_VADDR;
1374 map.length = ((unsigned long)_exiprom - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1376 create_mapping(&map);
1380 * Map the cache flushing regions.
1383 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1384 map.virtual = FLUSH_BASE;
1386 map.type = MT_CACHECLEAN;
1387 create_mapping(&map);
1389 #ifdef FLUSH_BASE_MINICACHE
1390 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1391 map.virtual = FLUSH_BASE_MINICACHE;
1393 map.type = MT_MINICLEAN;
1394 create_mapping(&map);
1398 * Create a mapping for the machine vectors at the high-vectors
1399 * location (0xffff0000). If we aren't using high-vectors, also
1400 * create a mapping at the low-vectors virtual address.
1402 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1403 map.virtual = 0xffff0000;
1404 map.length = PAGE_SIZE;
1405 #ifdef CONFIG_KUSER_HELPERS
1406 map.type = MT_HIGH_VECTORS;
1408 map.type = MT_LOW_VECTORS;
1410 create_mapping(&map);
1412 if (!vectors_high()) {
1414 map.length = PAGE_SIZE * 2;
1415 map.type = MT_LOW_VECTORS;
1416 create_mapping(&map);
1419 /* Now create a kernel read-only mapping */
1421 map.virtual = 0xffff0000 + PAGE_SIZE;
1422 map.length = PAGE_SIZE;
1423 map.type = MT_LOW_VECTORS;
1424 create_mapping(&map);
1427 * Ask the machine support to map in the statically mapped devices.
1435 /* Reserve fixed i/o space in VMALLOC region */
1439 * Finally flush the caches and tlb to ensure that we're in a
1440 * consistent state wrt the writebuffer. This also ensures that
1441 * any write-allocated cache lines in the vector page are written
1442 * back. After this point, we can start to touch devices again.
1444 local_flush_tlb_all();
1447 /* Enable asynchronous aborts */
1451 static void __init kmap_init(void)
1453 #ifdef CONFIG_HIGHMEM
1454 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1455 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1458 early_pte_alloc(pmd_off_k(FIXADDR_START), FIXADDR_START,
1459 _PAGE_KERNEL_TABLE);
1462 static void __init map_lowmem(void)
1464 phys_addr_t start, end;
1467 /* Map all the lowmem memory banks. */
1468 for_each_mem_range(i, &start, &end) {
1469 struct map_desc map;
1471 pr_debug("map lowmem start: 0x%08llx, end: 0x%08llx\n",
1472 (long long)start, (long long)end);
1473 if (end > arm_lowmem_limit)
1474 end = arm_lowmem_limit;
1479 * If our kernel image is in the VMALLOC area we need to remove
1480 * the kernel physical memory from lowmem since the kernel will
1481 * be mapped separately.
1483 * The kernel will typically be at the very start of lowmem,
1484 * but any placement relative to memory ranges is possible.
1486 * If the memblock contains the kernel, we have to chisel out
1487 * the kernel memory from it and map each part separately. We
1488 * get 6 different theoretical cases:
1490 * +--------+ +--------+
1491 * +-- start --+ +--------+ | Kernel | | Kernel |
1492 * | | | Kernel | | case 2 | | case 5 |
1493 * | | | case 1 | +--------+ | | +--------+
1494 * | Memory | +--------+ | | | Kernel |
1495 * | range | +--------+ | | | case 6 |
1496 * | | | Kernel | +--------+ | | +--------+
1497 * | | | case 3 | | Kernel | | |
1498 * +-- end ----+ +--------+ | case 4 | | |
1499 * +--------+ +--------+
1502 /* Case 5: kernel covers range, don't map anything, should be rare */
1503 if ((start > kernel_sec_start) && (end < kernel_sec_end))
1506 /* Cases where the kernel is starting inside the range */
1507 if ((kernel_sec_start >= start) && (kernel_sec_start <= end)) {
1508 /* Case 6: kernel is embedded in the range, we need two mappings */
1509 if ((start < kernel_sec_start) && (end > kernel_sec_end)) {
1510 /* Map memory below the kernel */
1511 map.pfn = __phys_to_pfn(start);
1512 map.virtual = __phys_to_virt(start);
1513 map.length = kernel_sec_start - start;
1514 map.type = MT_MEMORY_RW;
1515 create_mapping(&map);
1516 /* Map memory above the kernel */
1517 map.pfn = __phys_to_pfn(kernel_sec_end);
1518 map.virtual = __phys_to_virt(kernel_sec_end);
1519 map.length = end - kernel_sec_end;
1520 map.type = MT_MEMORY_RW;
1521 create_mapping(&map);
1524 /* Case 1: kernel and range start at the same address, should be common */
1525 if (kernel_sec_start == start)
1526 start = kernel_sec_end;
1527 /* Case 3: kernel and range end at the same address, should be rare */
1528 if (kernel_sec_end == end)
1529 end = kernel_sec_start;
1530 } else if ((kernel_sec_start < start) && (kernel_sec_end > start) && (kernel_sec_end < end)) {
1531 /* Case 2: kernel ends inside range, starts below it */
1532 start = kernel_sec_end;
1533 } else if ((kernel_sec_start > start) && (kernel_sec_start < end) && (kernel_sec_end > end)) {
1534 /* Case 4: kernel starts inside range, ends above it */
1535 end = kernel_sec_start;
1537 map.pfn = __phys_to_pfn(start);
1538 map.virtual = __phys_to_virt(start);
1539 map.length = end - start;
1540 map.type = MT_MEMORY_RW;
1541 create_mapping(&map);
1545 static void __init map_kernel(void)
1548 * We use the well known kernel section start and end and split the area in the
1552 * +----------------+ kernel_x_start
1555 * +----------------+ kernel_x_end / kernel_nx_start
1556 * | Non-executable |
1558 * +----------------+ kernel_nx_end
1562 * Notice that we are dealing with section sized mappings here so all of this
1563 * will be bumped to the closest section boundary. This means that some of the
1564 * non-executable part of the kernel memory is actually mapped as executable.
1565 * This will only persist until we turn on proper memory management later on
1566 * and we remap the whole kernel with page granularity.
1568 phys_addr_t kernel_x_start = kernel_sec_start;
1569 phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE);
1570 phys_addr_t kernel_nx_start = kernel_x_end;
1571 phys_addr_t kernel_nx_end = kernel_sec_end;
1572 struct map_desc map;
1574 map.pfn = __phys_to_pfn(kernel_x_start);
1575 map.virtual = __phys_to_virt(kernel_x_start);
1576 map.length = kernel_x_end - kernel_x_start;
1577 map.type = MT_MEMORY_RWX;
1578 create_mapping(&map);
1580 /* If the nx part is small it may end up covered by the tail of the RWX section */
1581 if (kernel_x_end == kernel_nx_end)
1584 map.pfn = __phys_to_pfn(kernel_nx_start);
1585 map.virtual = __phys_to_virt(kernel_nx_start);
1586 map.length = kernel_nx_end - kernel_nx_start;
1587 map.type = MT_MEMORY_RW;
1588 create_mapping(&map);
1591 #ifdef CONFIG_ARM_PV_FIXUP
1592 typedef void pgtables_remap(long long offset, unsigned long pgd);
1593 pgtables_remap lpae_pgtables_remap_asm;
1596 * early_paging_init() recreates boot time page table setup, allowing machines
1597 * to switch over to a high (>4G) address space on LPAE systems
1599 static void __init early_paging_init(const struct machine_desc *mdesc)
1601 pgtables_remap *lpae_pgtables_remap;
1602 unsigned long pa_pgd;
1603 unsigned int cr, ttbcr;
1606 if (!mdesc->pv_fixup)
1609 offset = mdesc->pv_fixup();
1614 * Offset the kernel section physical offsets so that the kernel
1615 * mapping will work out later on.
1617 kernel_sec_start += offset;
1618 kernel_sec_end += offset;
1621 * Get the address of the remap function in the 1:1 identity
1622 * mapping setup by the early page table assembly code. We
1623 * must get this prior to the pv update. The following barrier
1624 * ensures that this is complete before we fixup any P:V offsets.
1626 lpae_pgtables_remap = (pgtables_remap *)(unsigned long)__pa(lpae_pgtables_remap_asm);
1627 pa_pgd = __pa(swapper_pg_dir);
1630 pr_info("Switching physical address space to 0x%08llx\n",
1631 (u64)PHYS_OFFSET + offset);
1633 /* Re-set the phys pfn offset, and the pv offset */
1634 __pv_offset += offset;
1635 __pv_phys_pfn_offset += PFN_DOWN(offset);
1637 /* Run the patch stub to update the constants */
1638 fixup_pv_table(&__pv_table_begin,
1639 (&__pv_table_end - &__pv_table_begin) << 2);
1642 * We changing not only the virtual to physical mapping, but also
1643 * the physical addresses used to access memory. We need to flush
1644 * all levels of cache in the system with caching disabled to
1645 * ensure that all data is written back, and nothing is prefetched
1646 * into the caches. We also need to prevent the TLB walkers
1647 * allocating into the caches too. Note that this is ARMv7 LPAE
1651 set_cr(cr & ~(CR_I | CR_C));
1652 asm("mrc p15, 0, %0, c2, c0, 2" : "=r" (ttbcr));
1653 asm volatile("mcr p15, 0, %0, c2, c0, 2"
1654 : : "r" (ttbcr & ~(3 << 8 | 3 << 10)));
1658 * Fixup the page tables - this must be in the idmap region as
1659 * we need to disable the MMU to do this safely, and hence it
1660 * needs to be assembly. It's fairly simple, as we're using the
1661 * temporary tables setup by the initial assembly code.
1663 lpae_pgtables_remap(offset, pa_pgd);
1665 /* Re-enable the caches and cacheable TLB walks */
1666 asm volatile("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr));
1672 static void __init early_paging_init(const struct machine_desc *mdesc)
1676 if (!mdesc->pv_fixup)
1679 offset = mdesc->pv_fixup();
1683 pr_crit("Physical address space modification is only to support Keystone2.\n");
1684 pr_crit("Please enable ARM_LPAE and ARM_PATCH_PHYS_VIRT support to use this\n");
1685 pr_crit("feature. Your kernel may crash now, have a good day.\n");
1686 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1691 static void __init early_fixmap_shutdown(void)
1694 unsigned long va = fix_to_virt(__end_of_permanent_fixed_addresses - 1);
1696 pte_offset_fixmap = pte_offset_late_fixmap;
1697 pmd_clear(fixmap_pmd(va));
1698 local_flush_tlb_kernel_page(va);
1700 for (i = 0; i < __end_of_permanent_fixed_addresses; i++) {
1702 struct map_desc map;
1704 map.virtual = fix_to_virt(i);
1705 pte = pte_offset_early_fixmap(pmd_off_k(map.virtual), map.virtual);
1707 /* Only i/o device mappings are supported ATM */
1708 if (pte_none(*pte) ||
1709 (pte_val(*pte) & L_PTE_MT_MASK) != L_PTE_MT_DEV_SHARED)
1712 map.pfn = pte_pfn(*pte);
1713 map.type = MT_DEVICE;
1714 map.length = PAGE_SIZE;
1716 create_mapping(&map);
1721 * paging_init() sets up the page tables, initialises the zone memory
1722 * maps, and sets up the zero page, bad page and bad page tables.
1724 void __init paging_init(const struct machine_desc *mdesc)
1728 pr_debug("physical kernel sections: 0x%08llx-0x%08llx\n",
1729 kernel_sec_start, kernel_sec_end);
1731 prepare_page_table();
1733 memblock_set_current_limit(arm_lowmem_limit);
1734 pr_debug("lowmem limit is %08llx\n", (long long)arm_lowmem_limit);
1736 * After this point early_alloc(), i.e. the memblock allocator, can
1740 dma_contiguous_remap();
1741 early_fixmap_shutdown();
1742 devicemaps_init(mdesc);
1746 top_pmd = pmd_off_k(0xffff0000);
1748 /* allocate the zero page. */
1749 zero_page = early_alloc(PAGE_SIZE);
1753 empty_zero_page = virt_to_page(zero_page);
1754 __flush_dcache_page(NULL, empty_zero_page);
1757 void __init early_mm_init(const struct machine_desc *mdesc)
1759 build_mem_type_table();
1760 early_paging_init(mdesc);
1763 void set_pte_at(struct mm_struct *mm, unsigned long addr,
1764 pte_t *ptep, pte_t pteval)
1766 unsigned long ext = 0;
1768 if (addr < TASK_SIZE && pte_valid_user(pteval)) {
1769 if (!pte_special(pteval))
1770 __sync_icache_dcache(pteval);
1774 set_pte_ext(ptep, pteval, ext);