2 * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
4 * Copyright (C) 2007 ARM Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/spinlock.h>
24 #include <linux/of_address.h>
26 #include <asm/cacheflush.h>
27 #include <asm/hardware/cache-l2x0.h>
28 #include "cache-aurora-l2.h"
30 #define CACHE_LINE_SIZE 32
32 static void __iomem *l2x0_base;
33 static DEFINE_RAW_SPINLOCK(l2x0_lock);
34 static u32 l2x0_way_mask; /* Bitmask of active ways */
36 static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
38 /* Aurora don't have the cache ID register available, so we have to
39 * pass it though the device tree */
40 static u32 cache_id_part_number_from_dt;
42 struct l2x0_regs l2x0_saved_regs;
45 void (*setup)(const struct device_node *, u32 *, u32 *);
47 struct outer_cache_fns outer_cache;
50 static bool of_init = false;
52 static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
54 /* wait for cache operation by line or way to complete */
55 while (readl_relaxed(reg) & mask)
59 #ifdef CONFIG_CACHE_PL310
60 static inline void cache_wait(void __iomem *reg, unsigned long mask)
62 /* cache operations by line are atomic on PL310 */
65 #define cache_wait cache_wait_way
68 static inline void cache_sync(void)
70 void __iomem *base = l2x0_base;
72 writel_relaxed(0, base + sync_reg_offset);
73 cache_wait(base + L2X0_CACHE_SYNC, 1);
76 static inline void l2x0_clean_line(unsigned long addr)
78 void __iomem *base = l2x0_base;
79 cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
80 writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
83 static inline void l2x0_inv_line(unsigned long addr)
85 void __iomem *base = l2x0_base;
86 cache_wait(base + L2X0_INV_LINE_PA, 1);
87 writel_relaxed(addr, base + L2X0_INV_LINE_PA);
90 #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
91 static inline void debug_writel(unsigned long val)
93 if (outer_cache.set_debug)
94 outer_cache.set_debug(val);
97 static void pl310_set_debug(unsigned long val)
99 writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
102 /* Optimised out for non-errata case */
103 static inline void debug_writel(unsigned long val)
107 #define pl310_set_debug NULL
110 #ifdef CONFIG_PL310_ERRATA_588369
111 static inline void l2x0_flush_line(unsigned long addr)
113 void __iomem *base = l2x0_base;
115 /* Clean by PA followed by Invalidate by PA */
116 cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
117 writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
118 cache_wait(base + L2X0_INV_LINE_PA, 1);
119 writel_relaxed(addr, base + L2X0_INV_LINE_PA);
123 static inline void l2x0_flush_line(unsigned long addr)
125 void __iomem *base = l2x0_base;
126 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
127 writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
131 static void l2x0_cache_sync(void)
135 raw_spin_lock_irqsave(&l2x0_lock, flags);
137 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
140 static void __l2x0_flush_all(void)
143 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
144 cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
149 static void l2x0_flush_all(void)
154 raw_spin_lock_irqsave(&l2x0_lock, flags);
156 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
159 static void l2x0_clean_all(void)
164 raw_spin_lock_irqsave(&l2x0_lock, flags);
165 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
166 cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
168 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
171 static void l2x0_inv_all(void)
175 /* invalidate all ways */
176 raw_spin_lock_irqsave(&l2x0_lock, flags);
177 /* Invalidating when L2 is enabled is a nono */
178 BUG_ON(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN);
179 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
180 cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
182 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
185 static void l2x0_inv_range(unsigned long start, unsigned long end)
187 void __iomem *base = l2x0_base;
190 raw_spin_lock_irqsave(&l2x0_lock, flags);
191 if (start & (CACHE_LINE_SIZE - 1)) {
192 start &= ~(CACHE_LINE_SIZE - 1);
194 l2x0_flush_line(start);
196 start += CACHE_LINE_SIZE;
199 if (end & (CACHE_LINE_SIZE - 1)) {
200 end &= ~(CACHE_LINE_SIZE - 1);
202 l2x0_flush_line(end);
206 while (start < end) {
207 unsigned long blk_end = start + min(end - start, 4096UL);
209 while (start < blk_end) {
210 l2x0_inv_line(start);
211 start += CACHE_LINE_SIZE;
215 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
216 raw_spin_lock_irqsave(&l2x0_lock, flags);
219 cache_wait(base + L2X0_INV_LINE_PA, 1);
221 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
224 static void l2x0_clean_range(unsigned long start, unsigned long end)
226 void __iomem *base = l2x0_base;
229 if ((end - start) >= l2x0_size) {
234 raw_spin_lock_irqsave(&l2x0_lock, flags);
235 start &= ~(CACHE_LINE_SIZE - 1);
236 while (start < end) {
237 unsigned long blk_end = start + min(end - start, 4096UL);
239 while (start < blk_end) {
240 l2x0_clean_line(start);
241 start += CACHE_LINE_SIZE;
245 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
246 raw_spin_lock_irqsave(&l2x0_lock, flags);
249 cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
251 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
254 static void l2x0_flush_range(unsigned long start, unsigned long end)
256 void __iomem *base = l2x0_base;
259 if ((end - start) >= l2x0_size) {
264 raw_spin_lock_irqsave(&l2x0_lock, flags);
265 start &= ~(CACHE_LINE_SIZE - 1);
266 while (start < end) {
267 unsigned long blk_end = start + min(end - start, 4096UL);
270 while (start < blk_end) {
271 l2x0_flush_line(start);
272 start += CACHE_LINE_SIZE;
277 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
278 raw_spin_lock_irqsave(&l2x0_lock, flags);
281 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
283 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
286 static void l2x0_disable(void)
290 raw_spin_lock_irqsave(&l2x0_lock, flags);
292 writel_relaxed(0, l2x0_base + L2X0_CTRL);
294 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
297 static void l2x0_unlock(u32 cache_id)
303 case L2X0_CACHE_ID_PART_L310:
306 case AURORA_CACHE_ID:
310 /* L210 and unknown types */
315 for (i = 0; i < lockregs; i++) {
316 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
317 i * L2X0_LOCKDOWN_STRIDE);
318 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
319 i * L2X0_LOCKDOWN_STRIDE);
323 void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
329 int way_size_shift = L2X0_WAY_SIZE_SHIFT;
333 if (cache_id_part_number_from_dt)
334 cache_id = cache_id_part_number_from_dt;
336 cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID)
337 & L2X0_CACHE_ID_PART_MASK;
338 aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
343 /* Determine the number of ways */
345 case L2X0_CACHE_ID_PART_L310:
351 #ifdef CONFIG_PL310_ERRATA_753970
352 /* Unmapped register. */
353 sync_reg_offset = L2X0_DUMMY_REG;
355 outer_cache.set_debug = pl310_set_debug;
357 case L2X0_CACHE_ID_PART_L210:
358 ways = (aux >> 13) & 0xf;
362 case AURORA_CACHE_ID:
363 sync_reg_offset = AURORA_SYNC_REG;
364 ways = (aux >> 13) & 0xf;
365 ways = 2 << ((ways + 1) >> 2);
366 way_size_shift = AURORA_WAY_SIZE_SHIFT;
370 /* Assume unknown chips have 8 ways */
372 type = "L2x0 series";
376 l2x0_way_mask = (1 << ways) - 1;
379 * L2 cache Size = Way size * Number of ways
381 way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
382 way_size = 1 << (way_size + way_size_shift);
384 l2x0_size = ways * way_size * SZ_1K;
387 * Check if l2x0 controller is already enabled.
388 * If you are booting from non-secure mode
389 * accessing the below registers will fault.
391 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
392 /* Make sure that I&D is not locked down when starting */
393 l2x0_unlock(cache_id);
395 /* l2x0 controller is disabled */
396 writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
401 writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL);
404 /* Re-read it in case some bits are reserved. */
405 aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
407 /* Save the value for resuming. */
408 l2x0_saved_regs.aux_ctrl = aux;
411 outer_cache.inv_range = l2x0_inv_range;
412 outer_cache.clean_range = l2x0_clean_range;
413 outer_cache.flush_range = l2x0_flush_range;
414 outer_cache.sync = l2x0_cache_sync;
415 outer_cache.flush_all = l2x0_flush_all;
416 outer_cache.inv_all = l2x0_inv_all;
417 outer_cache.disable = l2x0_disable;
420 printk(KERN_INFO "%s cache controller enabled\n", type);
421 printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
422 ways, cache_id, aux, l2x0_size);
426 static int l2_wt_override;
429 * Note that the end addresses passed to Linux primitives are
430 * noninclusive, while the hardware cache range operations use
431 * inclusive start and end addresses.
433 static unsigned long calc_range_end(unsigned long start, unsigned long end)
436 * Limit the number of cache lines processed at once,
437 * since cache range operations stall the CPU pipeline
440 if (end > start + MAX_RANGE_SIZE)
441 end = start + MAX_RANGE_SIZE;
444 * Cache range operations can't straddle a page boundary.
446 if (end > PAGE_ALIGN(start+1))
447 end = PAGE_ALIGN(start+1);
453 * Make sure 'start' and 'end' reference the same page, as L2 is PIPT
454 * and range operations only do a TLB lookup on the start address.
456 static void aurora_pa_range(unsigned long start, unsigned long end,
457 unsigned long offset)
461 raw_spin_lock_irqsave(&l2x0_lock, flags);
462 writel(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG);
463 writel(end, l2x0_base + offset);
464 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
469 static void aurora_inv_range(unsigned long start, unsigned long end)
472 * round start and end adresses up to cache line size
474 start &= ~(CACHE_LINE_SIZE - 1);
475 end = ALIGN(end, CACHE_LINE_SIZE);
478 * Invalidate all full cache lines between 'start' and 'end'.
480 while (start < end) {
481 unsigned long range_end = calc_range_end(start, end);
482 aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
483 AURORA_INVAL_RANGE_REG);
488 static void aurora_clean_range(unsigned long start, unsigned long end)
491 * If L2 is forced to WT, the L2 will always be clean and we
492 * don't need to do anything here.
494 if (!l2_wt_override) {
495 start &= ~(CACHE_LINE_SIZE - 1);
496 end = ALIGN(end, CACHE_LINE_SIZE);
497 while (start != end) {
498 unsigned long range_end = calc_range_end(start, end);
499 aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
500 AURORA_CLEAN_RANGE_REG);
506 static void aurora_flush_range(unsigned long start, unsigned long end)
508 if (!l2_wt_override) {
509 start &= ~(CACHE_LINE_SIZE - 1);
510 end = ALIGN(end, CACHE_LINE_SIZE);
511 while (start != end) {
512 unsigned long range_end = calc_range_end(start, end);
513 aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
514 AURORA_FLUSH_RANGE_REG);
520 static void __init l2x0_of_setup(const struct device_node *np,
521 u32 *aux_val, u32 *aux_mask)
523 u32 data[2] = { 0, 0 };
526 u32 val = 0, mask = 0;
528 of_property_read_u32(np, "arm,tag-latency", &tag);
530 mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK;
531 val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT;
534 of_property_read_u32_array(np, "arm,data-latency",
535 data, ARRAY_SIZE(data));
536 if (data[0] && data[1]) {
537 mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK |
538 L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK;
539 val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) |
540 ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT);
543 of_property_read_u32(np, "arm,dirty-latency", &dirty);
545 mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK;
546 val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT;
554 static void __init pl310_of_setup(const struct device_node *np,
555 u32 *aux_val, u32 *aux_mask)
557 u32 data[3] = { 0, 0, 0 };
558 u32 tag[3] = { 0, 0, 0 };
559 u32 filter[2] = { 0, 0 };
561 of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
562 if (tag[0] && tag[1] && tag[2])
564 ((tag[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) |
565 ((tag[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) |
566 ((tag[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
567 l2x0_base + L2X0_TAG_LATENCY_CTRL);
569 of_property_read_u32_array(np, "arm,data-latency",
570 data, ARRAY_SIZE(data));
571 if (data[0] && data[1] && data[2])
573 ((data[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) |
574 ((data[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) |
575 ((data[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
576 l2x0_base + L2X0_DATA_LATENCY_CTRL);
578 of_property_read_u32_array(np, "arm,filter-ranges",
579 filter, ARRAY_SIZE(filter));
581 writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M),
582 l2x0_base + L2X0_ADDR_FILTER_END);
583 writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L2X0_ADDR_FILTER_EN,
584 l2x0_base + L2X0_ADDR_FILTER_START);
588 static void __init pl310_save(void)
590 u32 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
591 L2X0_CACHE_ID_RTL_MASK;
593 l2x0_saved_regs.tag_latency = readl_relaxed(l2x0_base +
594 L2X0_TAG_LATENCY_CTRL);
595 l2x0_saved_regs.data_latency = readl_relaxed(l2x0_base +
596 L2X0_DATA_LATENCY_CTRL);
597 l2x0_saved_regs.filter_end = readl_relaxed(l2x0_base +
598 L2X0_ADDR_FILTER_END);
599 l2x0_saved_regs.filter_start = readl_relaxed(l2x0_base +
600 L2X0_ADDR_FILTER_START);
602 if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
604 * From r2p0, there is Prefetch offset/control register
606 l2x0_saved_regs.prefetch_ctrl = readl_relaxed(l2x0_base +
609 * From r3p0, there is Power control register
611 if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
612 l2x0_saved_regs.pwr_ctrl = readl_relaxed(l2x0_base +
617 static void aurora_save(void)
619 l2x0_saved_regs.ctrl = readl_relaxed(l2x0_base + L2X0_CTRL);
620 l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
623 static void l2x0_resume(void)
625 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
626 /* restore aux ctrl and enable l2 */
627 l2x0_unlock(readl_relaxed(l2x0_base + L2X0_CACHE_ID));
629 writel_relaxed(l2x0_saved_regs.aux_ctrl, l2x0_base +
634 writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL);
638 static void pl310_resume(void)
642 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
643 /* restore pl310 setup */
644 writel_relaxed(l2x0_saved_regs.tag_latency,
645 l2x0_base + L2X0_TAG_LATENCY_CTRL);
646 writel_relaxed(l2x0_saved_regs.data_latency,
647 l2x0_base + L2X0_DATA_LATENCY_CTRL);
648 writel_relaxed(l2x0_saved_regs.filter_end,
649 l2x0_base + L2X0_ADDR_FILTER_END);
650 writel_relaxed(l2x0_saved_regs.filter_start,
651 l2x0_base + L2X0_ADDR_FILTER_START);
653 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
654 L2X0_CACHE_ID_RTL_MASK;
656 if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
657 writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
658 l2x0_base + L2X0_PREFETCH_CTRL);
659 if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
660 writel_relaxed(l2x0_saved_regs.pwr_ctrl,
661 l2x0_base + L2X0_POWER_CTRL);
668 static void aurora_resume(void)
670 if (!(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
671 writel(l2x0_saved_regs.aux_ctrl, l2x0_base + L2X0_AUX_CTRL);
672 writel(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL);
676 static void __init aurora_broadcast_l2_commands(void)
679 /* Enable Broadcasting of cache commands to L2*/
680 __asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r"(u));
681 u |= AURORA_CTRL_FW; /* Set the FW bit */
682 __asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" : : "r"(u));
686 static void __init aurora_of_setup(const struct device_node *np,
687 u32 *aux_val, u32 *aux_mask)
689 u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU;
690 u32 mask = AURORA_ACR_REPLACEMENT_MASK;
692 of_property_read_u32(np, "cache-id-part",
693 &cache_id_part_number_from_dt);
695 /* Determine and save the write policy */
696 l2_wt_override = of_property_read_bool(np, "wt-override");
698 if (l2_wt_override) {
699 val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY;
700 mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
708 static const struct l2x0_of_data pl310_data = {
709 .setup = pl310_of_setup,
712 .resume = pl310_resume,
713 .inv_range = l2x0_inv_range,
714 .clean_range = l2x0_clean_range,
715 .flush_range = l2x0_flush_range,
716 .sync = l2x0_cache_sync,
717 .flush_all = l2x0_flush_all,
718 .inv_all = l2x0_inv_all,
719 .disable = l2x0_disable,
720 .set_debug = pl310_set_debug,
724 static const struct l2x0_of_data l2x0_data = {
725 .setup = l2x0_of_setup,
728 .resume = l2x0_resume,
729 .inv_range = l2x0_inv_range,
730 .clean_range = l2x0_clean_range,
731 .flush_range = l2x0_flush_range,
732 .sync = l2x0_cache_sync,
733 .flush_all = l2x0_flush_all,
734 .inv_all = l2x0_inv_all,
735 .disable = l2x0_disable,
739 static const struct l2x0_of_data aurora_with_outer_data = {
740 .setup = aurora_of_setup,
743 .resume = aurora_resume,
744 .inv_range = aurora_inv_range,
745 .clean_range = aurora_clean_range,
746 .flush_range = aurora_flush_range,
747 .sync = l2x0_cache_sync,
748 .flush_all = l2x0_flush_all,
749 .inv_all = l2x0_inv_all,
750 .disable = l2x0_disable,
754 static const struct l2x0_of_data aurora_no_outer_data = {
755 .setup = aurora_of_setup,
758 .resume = aurora_resume,
762 static const struct of_device_id l2x0_ids[] __initconst = {
763 { .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
764 { .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
765 { .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
766 { .compatible = "marvell,aurora-system-cache",
767 .data = (void *)&aurora_no_outer_data},
768 { .compatible = "marvell,aurora-outer-cache",
769 .data = (void *)&aurora_with_outer_data},
773 int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
775 struct device_node *np;
776 const struct l2x0_of_data *data;
779 np = of_find_matching_node(NULL, l2x0_ids);
783 if (of_address_to_resource(np, 0, &res))
786 l2x0_base = ioremap(res.start, resource_size(&res));
790 l2x0_saved_regs.phy_base = res.start;
792 data = of_match_node(l2x0_ids, np)->data;
794 /* L2 configuration can only be changed if the cache is disabled */
795 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
797 data->setup(np, &aux_val, &aux_mask);
799 /* For aurora cache in no outer mode select the
800 * correct mode using the coprocessor*/
801 if (data == &aurora_no_outer_data)
802 aurora_broadcast_l2_commands();
809 l2x0_init(l2x0_base, aux_val, aux_mask);
811 memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache));