1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-fa.S
5 * Copyright (C) 2005 Faraday Corp.
6 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
8 * Based on cache-v4wb.S:
9 * Copyright (C) 1997-2002 Russell king
11 * Processors: FA520 FA526 FA626
13 #include <linux/linkage.h>
14 #include <linux/init.h>
15 #include <asm/assembler.h>
18 #include "proc-macros.S"
21 * The size of one data cache line.
23 #define CACHE_DLINESIZE 16
26 * The total size of the data cache.
28 #ifdef CONFIG_ARCH_GEMINI
29 #define CACHE_DSIZE 8192
31 #define CACHE_DSIZE 16384
34 /* FIXME: put optimal value here. Current one is just estimation */
35 #define CACHE_DLIMIT (CACHE_DSIZE * 2)
40 * Unconditionally clean and invalidate the entire icache.
42 ENTRY(fa_flush_icache_all)
44 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
46 ENDPROC(fa_flush_icache_all)
49 * flush_user_cache_all()
51 * Clean and invalidate all cache entries in a particular address
54 ENTRY(fa_flush_user_cache_all)
57 * flush_kern_cache_all()
59 * Clean and invalidate the entire cache.
61 ENTRY(fa_flush_kern_cache_all)
65 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache
67 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
68 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
69 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer
70 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
74 * flush_user_cache_range(start, end, flags)
76 * Invalidate a range of cache entries in the specified
79 * - start - start address (inclusive, page aligned)
80 * - end - end address (exclusive, page aligned)
81 * - flags - vma_area_struct flags describing address space
83 ENTRY(fa_flush_user_cache_range)
85 sub r3, r1, r0 @ calculate total size
86 cmp r3, #CACHE_DLIMIT @ total size >= limit?
87 bhs __flush_whole_cache @ flush whole D cache
90 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
91 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
92 add r0, r0, #CACHE_DLINESIZE
96 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
97 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
98 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
102 * coherent_kern_range(start, end)
104 * Ensure coherency between the Icache and the Dcache in the
105 * region described by start. If you have non-snooping
106 * Harvard caches, you need to implement this function.
108 * - start - virtual start address
109 * - end - virtual end address
111 ENTRY(fa_coherent_kern_range)
115 * coherent_user_range(start, end)
117 * Ensure coherency between the Icache and the Dcache in the
118 * region described by start. If you have non-snooping
119 * Harvard caches, you need to implement this function.
121 * - start - virtual start address
122 * - end - virtual end address
124 ENTRY(fa_coherent_user_range)
125 bic r0, r0, #CACHE_DLINESIZE - 1
126 1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
127 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
128 add r0, r0, #CACHE_DLINESIZE
132 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
133 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
134 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
138 * flush_kern_dcache_area(void *addr, size_t size)
140 * Ensure that the data held in the page kaddr is written back
141 * to the page in question.
143 * - addr - kernel address
144 * - size - size of region
146 ENTRY(fa_flush_kern_dcache_area)
148 1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
149 add r0, r0, #CACHE_DLINESIZE
153 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
154 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
158 * dma_inv_range(start, end)
160 * Invalidate (discard) the specified virtual address range.
161 * May not write back any entries. If 'start' or 'end'
162 * are not cache line aligned, those lines must be written
165 * - start - virtual start address
166 * - end - virtual end address
169 tst r0, #CACHE_DLINESIZE - 1
170 bic r0, r0, #CACHE_DLINESIZE - 1
171 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry
172 tst r1, #CACHE_DLINESIZE - 1
173 bic r1, r1, #CACHE_DLINESIZE - 1
174 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D entry
175 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
176 add r0, r0, #CACHE_DLINESIZE
180 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
184 * dma_clean_range(start, end)
186 * Clean (write back) the specified virtual address range.
188 * - start - virtual start address
189 * - end - virtual end address
192 bic r0, r0, #CACHE_DLINESIZE - 1
193 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
194 add r0, r0, #CACHE_DLINESIZE
198 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
202 * dma_flush_range(start,end)
203 * - start - virtual start address of region
204 * - end - virtual end address of region
206 ENTRY(fa_dma_flush_range)
207 bic r0, r0, #CACHE_DLINESIZE - 1
208 1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry
209 add r0, r0, #CACHE_DLINESIZE
213 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
217 * dma_map_area(start, size, dir)
218 * - start - kernel virtual start address
219 * - size - size of region
220 * - dir - DMA direction
222 ENTRY(fa_dma_map_area)
224 cmp r2, #DMA_TO_DEVICE
225 beq fa_dma_clean_range
228 ENDPROC(fa_dma_map_area)
231 * dma_unmap_area(start, size, dir)
232 * - start - kernel virtual start address
233 * - size - size of region
234 * - dir - DMA direction
236 ENTRY(fa_dma_unmap_area)
238 ENDPROC(fa_dma_unmap_area)
240 .globl fa_flush_kern_cache_louis
241 .equ fa_flush_kern_cache_louis, fa_flush_kern_cache_all
245 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
246 define_cache_functions fa