2 * arch/arm/mach-tegra/fuse.c
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
8 * Colin Cross <ccross@android.com>
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 #include <linux/kernel.h>
23 #include <linux/export.h>
24 #include <linux/random.h>
25 #include <linux/tegra-soc.h>
32 #define FUSE_UID_LOW 0x108
33 #define FUSE_UID_HIGH 0x10c
35 /* Tegra30 and later */
36 #define FUSE_VENDOR_CODE 0x200
37 #define FUSE_FAB_CODE 0x204
38 #define FUSE_LOT_CODE_0 0x208
39 #define FUSE_LOT_CODE_1 0x20c
40 #define FUSE_WAFER_ID 0x210
41 #define FUSE_X_COORDINATE 0x214
42 #define FUSE_Y_COORDINATE 0x218
44 #define FUSE_SKU_INFO 0x110
46 #define TEGRA20_FUSE_SPARE_BIT 0x200
47 #define TEGRA30_FUSE_SPARE_BIT 0x244
50 int tegra_cpu_process_id;
51 int tegra_core_process_id;
53 int tegra_cpu_speedo_id; /* only exist in Tegra30 and later */
54 int tegra_soc_speedo_id;
55 enum tegra_revision tegra_revision;
57 static int tegra_fuse_spare_bit;
58 static void (*tegra_init_speedo_data)(void);
60 /* The BCT to use at boot is specified by board straps that can be read
61 * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
63 int tegra_bct_strapping;
65 #define STRAP_OPT 0x008
66 #define GMI_AD0 (1 << 4)
67 #define GMI_AD1 (1 << 5)
68 #define RAM_ID_MASK (GMI_AD0 | GMI_AD1)
69 #define RAM_CODE_SHIFT 4
71 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
72 [TEGRA_REVISION_UNKNOWN] = "unknown",
73 [TEGRA_REVISION_A01] = "A01",
74 [TEGRA_REVISION_A02] = "A02",
75 [TEGRA_REVISION_A03] = "A03",
76 [TEGRA_REVISION_A03p] = "A03 prime",
77 [TEGRA_REVISION_A04] = "A04",
80 u32 tegra_fuse_readl(unsigned long offset)
82 return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
85 bool tegra_spare_fuse(int bit)
87 return tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);
90 static enum tegra_revision tegra_get_revision(u32 id)
92 u32 minor_rev = (id >> 16) & 0xf;
96 return TEGRA_REVISION_A01;
98 return TEGRA_REVISION_A02;
100 if (tegra_chip_id == TEGRA20 &&
101 (tegra_spare_fuse(18) || tegra_spare_fuse(19)))
102 return TEGRA_REVISION_A03p;
104 return TEGRA_REVISION_A03;
106 return TEGRA_REVISION_A04;
108 return TEGRA_REVISION_UNKNOWN;
112 static void tegra_get_process_id(void)
116 reg = tegra_fuse_readl(tegra_fuse_spare_bit);
117 tegra_cpu_process_id = (reg >> 6) & 3;
118 reg = tegra_fuse_readl(tegra_fuse_spare_bit);
119 tegra_core_process_id = (reg >> 12) & 3;
122 u32 tegra_read_chipid(void)
124 return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
127 static void __init tegra20_fuse_init_randomness(void)
131 randomness[0] = tegra_fuse_readl(FUSE_UID_LOW);
132 randomness[1] = tegra_fuse_readl(FUSE_UID_HIGH);
134 add_device_randomness(randomness, sizeof(randomness));
137 /* Applies to Tegra30 or later */
138 static void __init tegra30_fuse_init_randomness(void)
142 randomness[0] = tegra_fuse_readl(FUSE_VENDOR_CODE);
143 randomness[1] = tegra_fuse_readl(FUSE_FAB_CODE);
144 randomness[2] = tegra_fuse_readl(FUSE_LOT_CODE_0);
145 randomness[3] = tegra_fuse_readl(FUSE_LOT_CODE_1);
146 randomness[4] = tegra_fuse_readl(FUSE_WAFER_ID);
147 randomness[5] = tegra_fuse_readl(FUSE_X_COORDINATE);
148 randomness[6] = tegra_fuse_readl(FUSE_Y_COORDINATE);
150 add_device_randomness(randomness, sizeof(randomness));
153 void __init tegra_init_fuse(void)
158 u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
160 writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
162 reg = tegra_fuse_readl(FUSE_SKU_INFO);
164 tegra_sku_id = reg & 0xFF;
166 reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
168 tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
170 id = tegra_read_chipid();
172 tegra_chip_id = (id >> 8) & 0xff;
174 switch (tegra_chip_id) {
176 tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
177 tegra_init_speedo_data = &tegra20_init_speedo_data;
180 tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT;
181 tegra_init_speedo_data = &tegra30_init_speedo_data;
184 tegra_init_speedo_data = &tegra114_init_speedo_data;
187 pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id);
188 tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
189 tegra_init_speedo_data = &tegra_get_process_id;
192 tegra_revision = tegra_get_revision(id);
193 tegra_init_speedo_data();
194 randomness[3] = (tegra_cpu_process_id << 16) | tegra_core_process_id;
195 randomness[4] = (tegra_cpu_speedo_id << 16) | tegra_soc_speedo_id;
197 add_device_randomness(randomness, sizeof(randomness));
198 switch (tegra_chip_id) {
200 tegra20_fuse_init_randomness();
204 tegra30_fuse_init_randomness();
207 pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
208 tegra_revision_name[tegra_revision],
209 tegra_sku_id, tegra_cpu_process_id,
210 tegra_core_process_id);
213 unsigned long long tegra_chip_uid(void)
215 unsigned long long lo, hi;
217 lo = tegra_fuse_readl(FUSE_UID_LOW);
218 hi = tegra_fuse_readl(FUSE_UID_HIGH);
219 return (hi << 32ull) | lo;
221 EXPORT_SYMBOL(tegra_chip_uid);