arch/arm/mach-shmobile/setup-r8a7779.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * r8a7779 processor support
   4  *
   5  * Copyright (C) 2011, 2013  Renesas Solutions Corp.
   6  * Copyright (C) 2011  Magnus Damm
   7  * Copyright (C) 2013  Cogent Embedded, Inc.
   8  */
   9 #include <linux/init.h>
  10 #include <linux/irqchip.h>
  11
  12 #include <asm/mach/arch.h>
  13 #include <asm/mach/map.h>
  14
  15 #include "common.h"
  16 #include "r8a7779.h"
  17
  18 static struct map_desc r8a7779_io_desc[] __initdata = {
  19         /* 2M identity mapping for 0xf0000000 (MPCORE) */
  20         {
  21                 .virtual        = 0xf0000000,
  22                 .pfn            = __phys_to_pfn(0xf0000000),
  23                 .length         = SZ_2M,
  24                 .type           = MT_DEVICE_NONSHARED
  25         },
  26         /* 16M identity mapping for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
  27         {
  28                 .virtual        = 0xfe000000,
  29                 .pfn            = __phys_to_pfn(0xfe000000),
  30                 .length         = SZ_16M,
  31                 .type           = MT_DEVICE_NONSHARED
  32         },
  33 };
  34
  35 static void __init r8a7779_map_io(void)
  36 {
  37         debug_ll_io_init();
  38         iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
  39 }
  40
  41 #define HPBREG_BASE     0xfe700000
  42
  43 /* IRQ */
  44 #define INT2SMSKCR0     0x822a0 /* Interrupt Submask Clear Register 0 */
  45 #define INT2SMSKCR1     0x822a4 /* Interrupt Submask Clear Register 1 */
  46 #define INT2SMSKCR2     0x822a8 /* Interrupt Submask Clear Register 2 */
  47 #define INT2SMSKCR3     0x822ac /* Interrupt Submask Clear Register 3 */
  48 #define INT2SMSKCR4     0x822b0 /* Interrupt Submask Clear Register 4 */
  49
  50 #define INT2NTSR0       0x00060 /* Interrupt Notification Select Register 0 */
  51 #define INT2NTSR1       0x00064 /* Interrupt Notification Select Register 1 */
  52
  53 static void __init r8a7779_init_irq_dt(void)
  54 {
  55         void __iomem *base = ioremap(HPBREG_BASE, 0x00100000);
  56
  57         irqchip_init();
  58
  59         /* route all interrupts to ARM */
  60         __raw_writel(0xffffffff, base + INT2NTSR0);
  61         __raw_writel(0x3fffffff, base + INT2NTSR1);
  62
  63         /* unmask all known interrupts in INTCS2 */
  64         __raw_writel(0xfffffff0, base + INT2SMSKCR0);
  65         __raw_writel(0xfff7ffff, base + INT2SMSKCR1);
  66         __raw_writel(0xfffbffdf, base + INT2SMSKCR2);
  67         __raw_writel(0xbffffffc, base + INT2SMSKCR3);
  68         __raw_writel(0x003fee3f, base + INT2SMSKCR4);
  69
  70         iounmap(base);
  71 }
  72
  73 static const char *const r8a7779_compat_dt[] __initconst = {
  74         "renesas,r8a7779",
  75         NULL,
  76 };
  77
  78 DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
  79         .smp            = smp_ops(r8a7779_smp_ops),
  80         .map_io         = r8a7779_map_io,
  81         .init_irq       = r8a7779_init_irq_dt,
  82         .init_late      = shmobile_init_late,
  83         .dt_compat      = r8a7779_compat_dt,
  84 MACHINE_END