arch/arm/mach-s3c64xx/common.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright (c) 2011 Samsung Electronics Co., Ltd.
   4 //              http://www.samsung.com
   5 //
   6 // Copyright 2008 Openmoko, Inc.
   7 // Copyright 2008 Simtec Electronics
   8 //      Ben Dooks <ben@simtec.co.uk>
   9 //      http://armlinux.simtec.co.uk/
  10 //
  11 // Common Codes for S3C64XX machines
  12
  13 /*
  14  * NOTE: Code in this file is not used when booting with Device Tree support.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/module.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/ioport.h>
  22 #include <linux/serial_core.h>
  23 #include <linux/serial_s3c.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/reboot.h>
  26 #include <linux/io.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/irq.h>
  29 #include <linux/gpio.h>
  30 #include <linux/irqchip/arm-vic.h>
  31 #include <clocksource/samsung_pwm.h>
  32
  33 #include <asm/mach/arch.h>
  34 #include <asm/mach/map.h>
  35 #include <asm/system_misc.h>
  36
  37 #include <mach/map.h>
  38 #include <mach/irqs.h>
  39 #include <mach/hardware.h>
  40 #include <mach/regs-gpio.h>
  41 #include <mach/gpio-samsung.h>
  42
  43 #include <plat/cpu.h>
  44 #include <plat/devs.h>
  45 #include <plat/pm.h>
  46 #include <plat/gpio-cfg.h>
  47 #include <plat/pwm-core.h>
  48 #include <plat/regs-irqtype.h>
  49
  50 #include "common.h"
  51 #include "irq-uart.h"
  52 #include "watchdog-reset.h"
  53
  54 /* External clock frequency */
  55 static unsigned long xtal_f __ro_after_init = 12000000;
  56 static unsigned long xusbxti_f __ro_after_init = 48000000;
  57
  58 void __init s3c64xx_set_xtal_freq(unsigned long freq)
  59 {
  60         xtal_f = freq;
  61 }
  62
  63 void __init s3c64xx_set_xusbxti_freq(unsigned long freq)
  64 {
  65         xusbxti_f = freq;
  66 }
  67
  68 /* uart registration process */
  69
  70 static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
  71 {
  72         s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
  73 }
  74
  75 /* table of supported CPUs */
  76
  77 static const char name_s3c6400[] = "S3C6400";
  78 static const char name_s3c6410[] = "S3C6410";
  79
  80 static struct cpu_table cpu_ids[] __initdata = {
  81         {
  82                 .idcode         = S3C6400_CPU_ID,
  83                 .idmask         = S3C64XX_CPU_MASK,
  84                 .map_io         = s3c6400_map_io,
  85                 .init_uarts     = s3c64xx_init_uarts,
  86                 .init           = s3c6400_init,
  87                 .name           = name_s3c6400,
  88         }, {
  89                 .idcode         = S3C6410_CPU_ID,
  90                 .idmask         = S3C64XX_CPU_MASK,
  91                 .map_io         = s3c6410_map_io,
  92                 .init_uarts     = s3c64xx_init_uarts,
  93                 .init           = s3c6410_init,
  94                 .name           = name_s3c6410,
  95         },
  96 };
  97
  98 /* minimal IO mapping */
  99
 100 /*
 101  * note, for the boot process to work we have to keep the UART
 102  * virtual address aligned to an 1MiB boundary for the L1
 103  * mapping the head code makes. We keep the UART virtual address
 104  * aligned and add in the offset when we load the value here.
 105  */
 106 #define UART_OFFS (S3C_PA_UART & 0xfffff)
 107
 108 static struct map_desc s3c_iodesc[] __initdata = {
 109         {
 110                 .virtual        = (unsigned long)S3C_VA_SYS,
 111                 .pfn            = __phys_to_pfn(S3C64XX_PA_SYSCON),
 112                 .length         = SZ_4K,
 113                 .type           = MT_DEVICE,
 114         }, {
 115                 .virtual        = (unsigned long)S3C_VA_MEM,
 116                 .pfn            = __phys_to_pfn(S3C64XX_PA_SROM),
 117                 .length         = SZ_4K,
 118                 .type           = MT_DEVICE,
 119         }, {
 120                 .virtual        = (unsigned long)(S3C_VA_UART + UART_OFFS),
 121                 .pfn            = __phys_to_pfn(S3C_PA_UART),
 122                 .length         = SZ_4K,
 123                 .type           = MT_DEVICE,
 124         }, {
 125                 .virtual        = (unsigned long)VA_VIC0,
 126                 .pfn            = __phys_to_pfn(S3C64XX_PA_VIC0),
 127                 .length         = SZ_16K,
 128                 .type           = MT_DEVICE,
 129         }, {
 130                 .virtual        = (unsigned long)VA_VIC1,
 131                 .pfn            = __phys_to_pfn(S3C64XX_PA_VIC1),
 132                 .length         = SZ_16K,
 133                 .type           = MT_DEVICE,
 134         }, {
 135                 .virtual        = (unsigned long)S3C_VA_TIMER,
 136                 .pfn            = __phys_to_pfn(S3C_PA_TIMER),
 137                 .length         = SZ_16K,
 138                 .type           = MT_DEVICE,
 139         }, {
 140                 .virtual        = (unsigned long)S3C64XX_VA_GPIO,
 141                 .pfn            = __phys_to_pfn(S3C64XX_PA_GPIO),
 142                 .length         = SZ_4K,
 143                 .type           = MT_DEVICE,
 144         }, {
 145                 .virtual        = (unsigned long)S3C64XX_VA_MODEM,
 146                 .pfn            = __phys_to_pfn(S3C64XX_PA_MODEM),
 147                 .length         = SZ_4K,
 148                 .type           = MT_DEVICE,
 149         }, {
 150                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 151                 .pfn            = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
 152                 .length         = SZ_4K,
 153                 .type           = MT_DEVICE,
 154         }, {
 155                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 156                 .pfn            = __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
 157                 .length         = SZ_1K,
 158                 .type           = MT_DEVICE,
 159         },
 160 };
 161
 162 static struct bus_type s3c64xx_subsys = {
 163         .name           = "s3c64xx-core",
 164         .dev_name       = "s3c64xx-core",
 165 };
 166
 167 static struct device s3c64xx_dev = {
 168         .bus    = &s3c64xx_subsys,
 169 };
 170
 171 static struct samsung_pwm_variant s3c64xx_pwm_variant = {
 172         .bits           = 32,
 173         .div_base       = 0,
 174         .has_tint_cstat = true,
 175         .tclk_mask      = (1 << 7) | (1 << 6) | (1 << 5),
 176 };
 177
 178 void __init samsung_set_timer_source(unsigned int event, unsigned int source)
 179 {
 180         s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
 181         s3c64xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
 182 }
 183
 184 void __init samsung_timer_init(void)
 185 {
 186         unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
 187                 IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
 188                 IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
 189         };
 190
 191         samsung_pwm_clocksource_init(S3C_VA_TIMER,
 192                                         timer_irqs, &s3c64xx_pwm_variant);
 193 }
 194
 195 /* read cpu identification code */
 196
 197 void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
 198 {
 199         /* initialise the io descriptors we need for initialisation */
 200         iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
 201         iotable_init(mach_desc, size);
 202
 203         /* detect cpu id */
 204         s3c64xx_init_cpu();
 205
 206         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 207
 208         samsung_pwm_set_platdata(&s3c64xx_pwm_variant);
 209 }
 210
 211 static __init int s3c64xx_dev_init(void)
 212 {
 213         /* Not applicable when using DT. */
 214         if (of_have_populated_dt() || !soc_is_s3c64xx())
 215                 return 0;
 216
 217         subsys_system_register(&s3c64xx_subsys, NULL);
 218         return device_register(&s3c64xx_dev);
 219 }
 220 core_initcall(s3c64xx_dev_init);
 221
 222 /*
 223  * setup the sources the vic should advertise resume
 224  * for, even though it is not doing the wake
 225  * (set_irq_wake needs to be valid)
 226  */
 227 #define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
 228 #define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
 229                          1 << (IRQ_PENDN - IRQ_VIC1_BASE) |     \
 230                          1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) |    \
 231                          1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) |    \
 232                          1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
 233
 234 void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
 235 {
 236         /*
 237          * FIXME: there is no better place to put this at the moment
 238          * (s3c64xx_clk_init needs ioremap and must happen before init_time
 239          * samsung_wdt_reset_init needs clocks)
 240          */
 241         s3c64xx_clk_init(NULL, xtal_f, xusbxti_f, soc_is_s3c6400(), S3C_VA_SYS);
 242         samsung_wdt_reset_init(S3C_VA_WATCHDOG);
 243
 244         printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
 245
 246         /* initialise the pair of VICs */
 247         vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
 248         vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
 249 }
 250
 251 #define eint_offset(irq)        ((irq) - IRQ_EINT(0))
 252 #define eint_irq_to_bit(irq)    ((u32)(1 << eint_offset(irq)))
 253
 254 static inline void s3c_irq_eint_mask(struct irq_data *data)
 255 {
 256         u32 mask;
 257
 258         mask = __raw_readl(S3C64XX_EINT0MASK);
 259         mask |= (u32)data->chip_data;
 260         __raw_writel(mask, S3C64XX_EINT0MASK);
 261 }
 262
 263 static void s3c_irq_eint_unmask(struct irq_data *data)
 264 {
 265         u32 mask;
 266
 267         mask = __raw_readl(S3C64XX_EINT0MASK);
 268         mask &= ~((u32)data->chip_data);
 269         __raw_writel(mask, S3C64XX_EINT0MASK);
 270 }
 271
 272 static inline void s3c_irq_eint_ack(struct irq_data *data)
 273 {
 274         __raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
 275 }
 276
 277 static void s3c_irq_eint_maskack(struct irq_data *data)
 278 {
 279         /* compiler should in-line these */
 280         s3c_irq_eint_mask(data);
 281         s3c_irq_eint_ack(data);
 282 }
 283
 284 static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
 285 {
 286         int offs = eint_offset(data->irq);
 287         int pin, pin_val;
 288         int shift;
 289         u32 ctrl, mask;
 290         u32 newvalue = 0;
 291         void __iomem *reg;
 292
 293         if (offs > 27)
 294                 return -EINVAL;
 295
 296         if (offs <= 15)
 297                 reg = S3C64XX_EINT0CON0;
 298         else
 299                 reg = S3C64XX_EINT0CON1;
 300
 301         switch (type) {
 302         case IRQ_TYPE_NONE:
 303                 printk(KERN_WARNING "No edge setting!\n");
 304                 break;
 305
 306         case IRQ_TYPE_EDGE_RISING:
 307                 newvalue = S3C2410_EXTINT_RISEEDGE;
 308                 break;
 309
 310         case IRQ_TYPE_EDGE_FALLING:
 311                 newvalue = S3C2410_EXTINT_FALLEDGE;
 312                 break;
 313
 314         case IRQ_TYPE_EDGE_BOTH:
 315                 newvalue = S3C2410_EXTINT_BOTHEDGE;
 316                 break;
 317
 318         case IRQ_TYPE_LEVEL_LOW:
 319                 newvalue = S3C2410_EXTINT_LOWLEV;
 320                 break;
 321
 322         case IRQ_TYPE_LEVEL_HIGH:
 323                 newvalue = S3C2410_EXTINT_HILEV;
 324                 break;
 325
 326         default:
 327                 printk(KERN_ERR "No such irq type %d", type);
 328                 return -1;
 329         }
 330
 331         if (offs <= 15)
 332                 shift = (offs / 2) * 4;
 333         else
 334                 shift = ((offs - 16) / 2) * 4;
 335         mask = 0x7 << shift;
 336
 337         ctrl = __raw_readl(reg);
 338         ctrl &= ~mask;
 339         ctrl |= newvalue << shift;
 340         __raw_writel(ctrl, reg);
 341
 342         /* set the GPIO pin appropriately */
 343
 344         if (offs < 16) {
 345                 pin = S3C64XX_GPN(offs);
 346                 pin_val = S3C_GPIO_SFN(2);
 347         } else if (offs < 23) {
 348                 pin = S3C64XX_GPL(offs + 8 - 16);
 349                 pin_val = S3C_GPIO_SFN(3);
 350         } else {
 351                 pin = S3C64XX_GPM(offs - 23);
 352                 pin_val = S3C_GPIO_SFN(3);
 353         }
 354
 355         s3c_gpio_cfgpin(pin, pin_val);
 356
 357         return 0;
 358 }
 359
 360 static struct irq_chip s3c_irq_eint = {
 361         .name           = "s3c-eint",
 362         .irq_mask       = s3c_irq_eint_mask,
 363         .irq_unmask     = s3c_irq_eint_unmask,
 364         .irq_mask_ack   = s3c_irq_eint_maskack,
 365         .irq_ack        = s3c_irq_eint_ack,
 366         .irq_set_type   = s3c_irq_eint_set_type,
 367         .irq_set_wake   = s3c_irqext_wake,
 368 };
 369
 370 /* s3c_irq_demux_eint
 371  *
 372  * This function demuxes the IRQ from the group0 external interrupts,
 373  * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
 374  * the specific handlers s3c_irq_demux_eintX_Y.
 375  */
 376 static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
 377 {
 378         u32 status = __raw_readl(S3C64XX_EINT0PEND);
 379         u32 mask = __raw_readl(S3C64XX_EINT0MASK);
 380         unsigned int irq;
 381
 382         status &= ~mask;
 383         status >>= start;
 384         status &= (1 << (end - start + 1)) - 1;
 385
 386         for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
 387                 if (status & 1)
 388                         generic_handle_irq(irq);
 389
 390                 status >>= 1;
 391         }
 392 }
 393
 394 static void s3c_irq_demux_eint0_3(struct irq_desc *desc)
 395 {
 396         s3c_irq_demux_eint(0, 3);
 397 }
 398
 399 static void s3c_irq_demux_eint4_11(struct irq_desc *desc)
 400 {
 401         s3c_irq_demux_eint(4, 11);
 402 }
 403
 404 static void s3c_irq_demux_eint12_19(struct irq_desc *desc)
 405 {
 406         s3c_irq_demux_eint(12, 19);
 407 }
 408
 409 static void s3c_irq_demux_eint20_27(struct irq_desc *desc)
 410 {
 411         s3c_irq_demux_eint(20, 27);
 412 }
 413
 414 static int __init s3c64xx_init_irq_eint(void)
 415 {
 416         int irq;
 417
 418         /* On DT-enabled systems EINTs are handled by pinctrl-s3c64xx driver. */
 419         if (of_have_populated_dt() || !soc_is_s3c64xx())
 420                 return -ENODEV;
 421
 422         for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
 423                 irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
 424                 irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
 425                 irq_clear_status_flags(irq, IRQ_NOREQUEST);
 426         }
 427
 428         irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
 429         irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
 430         irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
 431         irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
 432
 433         return 0;
 434 }
 435 arch_initcall(s3c64xx_init_irq_eint);
 436
 437 void s3c64xx_restart(enum reboot_mode mode, const char *cmd)
 438 {
 439         if (mode != REBOOT_SOFT)
 440                 samsung_wdt_reset();
 441
 442         /* if all else fails, or mode was for soft, jump to 0 */
 443         soft_restart(0);
 444 }